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Commit 7d740a066fb9c6681c2898c7977209725c9e552f

Authored by Yoshihiro Shimoda
Committed by Paul Mundt
1 parent 0465b9fb5f
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

sh: Add support for SH7763 CPU subtype. 

Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

Showing 16 changed files with 564 additions and 12 deletions Side-by-side Diff

... ... @@ -265,6 +265,12 @@
265 265  
266 266 # SH-4A Processor Support
267 267  
  268 +config CPU_SUBTYPE_SH7763
  269 + bool "Support SH7763 processor"
  270 + select CPU_SH4A
  271 + help
  272 + Select SH7763 if you have a SH4A SH7763(R5S77631) CPU.
  273 +
268 274 config CPU_SUBTYPE_SH7770
269 275 bool "Support SH7770 processor"
270 276 select CPU_SH4A
... ... @@ -551,7 +557,8 @@
551 557  
552 558 config SH_TIMER_IRQ
553 559 int
554   - default "28" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
  560 + default "28" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || \
  561 + CPU_SUBTYPE_SH7763
555 562 default "86" if CPU_SUBTYPE_SH7619
556 563 default "140" if CPU_SUBTYPE_SH7206
557 564 default "16"
arch/sh/Kconfig.debug
Diff comments   View file @ 7d740a0
... ... @@ -29,7 +29,7 @@
29 29 config EARLY_SCIF_CONSOLE_PORT
30 30 hex
31 31 depends on EARLY_SCIF_CONSOLE
32   - default "0xffe00000" if CPU_SUBTYPE_SH7780
  32 + default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763
33 33 default "0xffea0000" if CPU_SUBTYPE_SH7785
34 34 default "0xfffe8000" if CPU_SUBTYPE_SH7203
35 35 default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
arch/sh/drivers/pci/Makefile
Diff comments   View file @ 7d740a0
... ... @@ -7,6 +7,7 @@
7 7  
8 8 obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o
9 9 obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o
  10 +obj-$(CONFIG_CPU_SUBTYPE_SH7763) += pci-sh7780.o ops-sh4.o
10 11 obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o
11 12 obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o
12 13 obj-$(CONFIG_CPU_SH5) += pci-sh5.o ops-sh5.o
arch/sh/drivers/pci/pci-sh4.h
Diff comments   View file @ 7d740a0
1 1 #ifndef __PCI_SH4_H
2 2 #define __PCI_SH4_H
3 3  
4   -#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
  4 +#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
  5 + defined(CONFIG_CPU_SUBTYPE_SH7785) || \
  6 + defined(CONFIG_CPU_SUBTYPE_SH7763)
5 7 #include "pci-sh7780.h"
6 8 #else
7 9 #include "pci-sh7751.h"
arch/sh/drivers/pci/pci-sh7780.c
Diff comments   View file @ 7d740a0
... ... @@ -58,6 +58,7 @@
58 58 id = pci_read_reg(SH7780_PCIVID);
59 59 if ((id & 0xffff) == SH7780_VENDOR_ID) {
60 60 switch ((id >> 16) & 0xffff) {
  61 + case SH7763_DEVICE_ID:
61 62 case SH7780_DEVICE_ID:
62 63 case SH7781_DEVICE_ID:
63 64 case SH7785_DEVICE_ID:
arch/sh/drivers/pci/pci-sh7780.h
Diff comments   View file @ 7d740a0
... ... @@ -16,6 +16,7 @@
16 16 #define SH7780_VENDOR_ID 0x1912
17 17 #define SH7781_DEVICE_ID 0x0001
18 18 #define SH7780_DEVICE_ID 0x0002
  19 +#define SH7763_DEVICE_ID 0x0004
19 20 #define SH7785_DEVICE_ID 0x0007
20 21  
21 22 /* SH7780 Control Registers */
arch/sh/kernel/cpu/sh4/probe.c
Diff comments   View file @ 7d740a0
... ... @@ -98,6 +98,8 @@
98 98 case 0x200A:
99 99 if (prr == 0x61)
100 100 boot_cpu_data.type = CPU_SH7781;
  101 + else if (prr == 0xa1)
  102 + boot_cpu_data.type = CPU_SH7763;
101 103 else
102 104 boot_cpu_data.type = CPU_SH7780;
103 105  
arch/sh/kernel/cpu/sh4a/Makefile
Diff comments   View file @ 7d740a0
... ... @@ -3,6 +3,7 @@
3 3 #
4 4  
5 5 # CPU subtype setup
  6 +obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o
6 7 obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
7 8 obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
8 9 obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
... ... @@ -14,6 +15,7 @@
14 15 smp-$(CONFIG_CPU_SUBTYPE_SHX3) := smp-shx3.o
15 16  
16 17 # Primary on-chip clocks (common)
  18 +clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o
17 19 clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
18 20 clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
19 21 clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
arch/sh/kernel/cpu/sh4a/clock-sh7763.c
Diff comments   View file @ 7d740a0
  1 +/*
  2 + * arch/sh/kernel/cpu/sh4a/clock-sh7763.c
  3 + *
  4 + * SH7763 support for the clock framework
  5 + *
  6 + * Copyright (C) 2005 Paul Mundt
  7 + * Copyright (C) 2007 Yoshihiro Shimoda
  8 + *
  9 + * This file is subject to the terms and conditions of the GNU General Public
  10 + * License. See the file "COPYING" in the main directory of this archive
  11 + * for more details.
  12 + */
  13 +#include <linux/init.h>
  14 +#include <linux/kernel.h>
  15 +#include <asm/clock.h>
  16 +#include <asm/freq.h>
  17 +#include <asm/io.h>
  18 +
  19 +static int bfc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 };
  20 +static int p0fc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 };
  21 +static int p1fc_divisors[] = { 1, 1, 1, 16, 1, 1, 1, 1 };
  22 +static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 };
  23 +
  24 +static void master_clk_init(struct clk *clk)
  25 +{
  26 + clk->rate *= p0fc_divisors[(ctrl_inl(FRQCR) >> 4) & 0x07];
  27 +}
  28 +
  29 +static struct clk_ops sh7763_master_clk_ops = {
  30 + .init = master_clk_init,
  31 +};
  32 +
  33 +static void module_clk_recalc(struct clk *clk)
  34 +{
  35 + int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07);
  36 + clk->rate = clk->parent->rate / p0fc_divisors[idx];
  37 +}
  38 +
  39 +static struct clk_ops sh7763_module_clk_ops = {
  40 + .recalc = module_clk_recalc,
  41 +};
  42 +
  43 +static void bus_clk_recalc(struct clk *clk)
  44 +{
  45 + int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07);
  46 + clk->rate = clk->parent->rate / bfc_divisors[idx];
  47 +}
  48 +
  49 +static struct clk_ops sh7763_bus_clk_ops = {
  50 + .recalc = bus_clk_recalc,
  51 +};
  52 +
  53 +static void cpu_clk_recalc(struct clk *clk)
  54 +{
  55 + clk->rate = clk->parent->rate;
  56 +}
  57 +
  58 +static struct clk_ops sh7763_cpu_clk_ops = {
  59 + .recalc = cpu_clk_recalc,
  60 +};
  61 +
  62 +static struct clk_ops *sh7763_clk_ops[] = {
  63 + &sh7763_master_clk_ops,
  64 + &sh7763_module_clk_ops,
  65 + &sh7763_bus_clk_ops,
  66 + &sh7763_cpu_clk_ops,
  67 +};
  68 +
  69 +void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
  70 +{
  71 + if (idx < ARRAY_SIZE(sh7763_clk_ops))
  72 + *ops = sh7763_clk_ops[idx];
  73 +}
  74 +
  75 +static void shyway_clk_recalc(struct clk *clk)
  76 +{
  77 + int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07);
  78 + clk->rate = clk->parent->rate / cfc_divisors[idx];
  79 +}
  80 +
  81 +static struct clk_ops sh7763_shyway_clk_ops = {
  82 + .recalc = shyway_clk_recalc,
  83 +};
  84 +
  85 +static struct clk sh7763_shyway_clk = {
  86 + .name = "shyway_clk",
  87 + .flags = CLK_ALWAYS_ENABLED,
  88 + .ops = &sh7763_shyway_clk_ops,
  89 +};
  90 +
  91 +/*
  92 + * Additional SH7763-specific on-chip clocks that aren't already part of the
  93 + * clock framework
  94 + */
  95 +static struct clk *sh7763_onchip_clocks[] = {
  96 + &sh7763_shyway_clk,
  97 +};
  98 +
  99 +static int __init sh7763_clk_init(void)
  100 +{
  101 + struct clk *clk = clk_get(NULL, "master_clk");
  102 + int i;
  103 +
  104 + for (i = 0; i < ARRAY_SIZE(sh7763_onchip_clocks); i++) {
  105 + struct clk *clkp = sh7763_onchip_clocks[i];
  106 +
  107 + clkp->parent = clk;
  108 + clk_register(clkp);
  109 + clk_enable(clkp);
  110 + }
  111 +
  112 + /*
  113 + * Now that we have the rest of the clocks registered, we need to
  114 + * force the parent clock to propagate so that these clocks will
  115 + * automatically figure out their rate. We cheat by handing the
  116 + * parent clock its current rate and forcing child propagation.
  117 + */
  118 + clk_set_rate(clk, clk_get_rate(clk));
  119 +
  120 + clk_put(clk);
  121 +
  122 + return 0;
  123 +}
  124 +
  125 +arch_initcall(sh7763_clk_init);
arch/sh/kernel/cpu/sh4a/setup-sh7763.c
Diff comments   View file @ 7d740a0
  1 +/*
  2 + * SH7763 Setup
  3 + *
  4 + * Copyright (C) 2006 Paul Mundt
  5 + * Copyright (C) 2007 Yoshihiro Shimoda
  6 + *
  7 + * This file is subject to the terms and conditions of the GNU General Public
  8 + * License. See the file "COPYING" in the main directory of this archive
  9 + * for more details.
  10 + */
  11 +#include <linux/platform_device.h>
  12 +#include <linux/init.h>
  13 +#include <linux/serial.h>
  14 +#include <linux/io.h>
  15 +#include <asm/sci.h>
  16 +
  17 +static struct resource rtc_resources[] = {
  18 + [0] = {
  19 + .start = 0xffe80000,
  20 + .end = 0xffe80000 + 0x58 - 1,
  21 + .flags = IORESOURCE_IO,
  22 + },
  23 + [1] = {
  24 + /* Period IRQ */
  25 + .start = 21,
  26 + .flags = IORESOURCE_IRQ,
  27 + },
  28 + [2] = {
  29 + /* Carry IRQ */
  30 + .start = 22,
  31 + .flags = IORESOURCE_IRQ,
  32 + },
  33 + [3] = {
  34 + /* Alarm IRQ */
  35 + .start = 20,
  36 + .flags = IORESOURCE_IRQ,
  37 + },
  38 +};
  39 +
  40 +static struct platform_device rtc_device = {
  41 + .name = "sh-rtc",
  42 + .id = -1,
  43 + .num_resources = ARRAY_SIZE(rtc_resources),
  44 + .resource = rtc_resources,
  45 +};
  46 +
  47 +static struct plat_sci_port sci_platform_data[] = {
  48 + {
  49 + .mapbase = 0xffe00000,
  50 + .flags = UPF_BOOT_AUTOCONF,
  51 + .type = PORT_SCIF,
  52 + .irqs = { 40, 41, 43, 42 },
  53 + }, {
  54 + .mapbase = 0xffe08000,
  55 + .flags = UPF_BOOT_AUTOCONF,
  56 + .type = PORT_SCIF,
  57 + .irqs = { 76, 77, 79, 78 },
  58 + }, {
  59 + .flags = 0,
  60 + }
  61 +};
  62 +
  63 +static struct platform_device sci_device = {
  64 + .name = "sh-sci",
  65 + .id = -1,
  66 + .dev = {
  67 + .platform_data = sci_platform_data,
  68 + },
  69 +};
  70 +
  71 +static struct resource usb_ohci_resources[] = {
  72 + [0] = {
  73 + .start = 0xffec8000,
  74 + .end = 0xffec80ff,
  75 + .flags = IORESOURCE_MEM,
  76 + },
  77 + [1] = {
  78 + .start = 83,
  79 + .end = 83,
  80 + .flags = IORESOURCE_IRQ,
  81 + },
  82 +};
  83 +
  84 +static u64 usb_ohci_dma_mask = 0xffffffffUL;
  85 +static struct platform_device usb_ohci_device = {
  86 + .name = "sh_ohci",
  87 + .id = -1,
  88 + .dev = {
  89 + .dma_mask = &usb_ohci_dma_mask,
  90 + .coherent_dma_mask = 0xffffffff,
  91 + },
  92 + .num_resources = ARRAY_SIZE(usb_ohci_resources),
  93 + .resource = usb_ohci_resources,
  94 +};
  95 +
  96 +static struct resource usbf_resources[] = {
  97 + [0] = {
  98 + .start = 0xffec0000,
  99 + .end = 0xffec00ff,
  100 + .flags = IORESOURCE_MEM,
  101 + },
  102 + [1] = {
  103 + .start = 84,
  104 + .end = 84,
  105 + .flags = IORESOURCE_IRQ,
  106 + },
  107 +};
  108 +
  109 +static struct platform_device usbf_device = {
  110 + .name = "sh_udc",
  111 + .id = -1,
  112 + .dev = {
  113 + .dma_mask = NULL,
  114 + .coherent_dma_mask = 0xffffffff,
  115 + },
  116 + .num_resources = ARRAY_SIZE(usbf_resources),
  117 + .resource = usbf_resources,
  118 +};
  119 +
  120 +static struct platform_device *sh7763_devices[] __initdata = {
  121 + &rtc_device,
  122 + &sci_device,
  123 + &usb_ohci_device,
  124 + &usbf_device,
  125 +};
  126 +
  127 +static int __init sh7763_devices_setup(void)
  128 +{
  129 + return platform_add_devices(sh7763_devices,
  130 + ARRAY_SIZE(sh7763_devices));
  131 +}
  132 +__initcall(sh7763_devices_setup);
  133 +
  134 +enum {
  135 + UNUSED = 0,
  136 +
  137 + /* interrupt sources */
  138 +
  139 + IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
  140 + IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
  141 + IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
  142 + IRL_HHLL, IRL_HHLH, IRL_HHHL,
  143 +
  144 + IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  145 + RTC_ATI, RTC_PRI, RTC_CUI,
  146 + WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
  147 + HUDI, LCDC,
  148 + DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMAE,
  149 + SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
  150 + DMAC0_DMINT4, DMAC0_DMINT5,
  151 + IIC0, IIC1,
  152 + CMT,
  153 + GEINT0, GEINT1, GEINT2,
  154 + HAC,
  155 + PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
  156 + PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
  157 + STIF0, STIF1,
  158 + SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
  159 + SIOF0, SIOF1, SIOF2,
  160 + USBH, USBFI0, USBFI1,
  161 + TPU, PCC,
  162 + MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
  163 + SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND,
  164 + TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3,
  165 + SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
  166 + GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3,
  167 +
  168 + /* interrupt groups */
  169 +
  170 + TMU012, TMU345, RTC, DMAC, SCIF0, GETHER, PCIC5,
  171 + SCIF1, USBF, MMCIF, SIM, SCIF2, GPIO,
  172 +};
  173 +
  174 +static struct intc_vect vectors[] __initdata = {
  175 + INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
  176 + INTC_VECT(RTC_CUI, 0x4c0),
  177 + INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
  178 + INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),
  179 + INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600),
  180 + INTC_VECT(LCDC, 0x620),
  181 + INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
  182 + INTC_VECT(DMAC0_DMINT2, 0x680), INTC_VECT(DMAC0_DMINT3, 0x6a0),
  183 + INTC_VECT(DMAC0_DMAE, 0x6c0),
  184 + INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
  185 + INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
  186 + INTC_VECT(DMAC0_DMINT4, 0x780), INTC_VECT(DMAC0_DMINT5, 0x7a0),
  187 + INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0),
  188 + INTC_VECT(CMT, 0x900), INTC_VECT(GEINT0, 0x920),
  189 + INTC_VECT(GEINT1, 0x940), INTC_VECT(GEINT2, 0x960),
  190 + INTC_VECT(HAC, 0x980),
  191 + INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
  192 + INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
  193 + INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0),
  194 + INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0),
  195 + INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20),
  196 + INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60),
  197 + INTC_VECT(SCIF1_ERI, 0xb80), INTC_VECT(SCIF1_RXI, 0xba0),
  198 + INTC_VECT(SCIF1_BRI, 0xbc0), INTC_VECT(SCIF1_TXI, 0xbe0),
  199 + INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20),
  200 + INTC_VECT(USBH, 0xc60), INTC_VECT(USBFI0, 0xc80),
  201 + INTC_VECT(USBFI1, 0xca0),
  202 + INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),
  203 + INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20),
  204 + INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60),
  205 + INTC_VECT(SIM_ERI, 0xd80), INTC_VECT(SIM_RXI, 0xda0),
  206 + INTC_VECT(SIM_TXI, 0xdc0), INTC_VECT(SIM_TEND, 0xde0),
  207 + INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
  208 + INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60),
  209 + INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
  210 + INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0),
  211 + INTC_VECT(SCIF1_ERI, 0xf00), INTC_VECT(SCIF1_RXI, 0xf20),
  212 + INTC_VECT(SCIF1_BRI, 0xf40), INTC_VECT(SCIF1_TXI, 0xf60),
  213 + INTC_VECT(GPIO_CH0, 0xf80), INTC_VECT(GPIO_CH1, 0xfa0),
  214 + INTC_VECT(GPIO_CH2, 0xfc0), INTC_VECT(GPIO_CH3, 0xfe0),
  215 +};
  216 +
  217 +static struct intc_group groups[] __initdata = {
  218 + INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
  219 + INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
  220 + INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
  221 + INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
  222 + DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
  223 + INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
  224 + INTC_GROUP(GETHER, GEINT0, GEINT1, GEINT2),
  225 + INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
  226 + INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
  227 + INTC_GROUP(USBF, USBFI0, USBFI1),
  228 + INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
  229 + INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND),
  230 + INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
  231 + INTC_GROUP(GPIO, GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3),
  232 +};
  233 +
  234 +static struct intc_prio priorities[] __initdata = {
  235 + INTC_PRIO(SCIF0, 3),
  236 + INTC_PRIO(SCIF1, 3),
  237 + INTC_PRIO(SCIF2, 3),
  238 +};
  239 +
  240 +static struct intc_mask_reg mask_registers[] __initdata = {
  241 + { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
  242 + { 0, 0, 0, 0, 0, 0, GPIO, 0,
  243 + SSI0, MMCIF, 0, SIOF0, PCIC5, PCIINTD, PCIINTC, PCIINTB,
  244 + PCIINTA, PCISERR, HAC, CMT, 0, 0, 0, DMAC,
  245 + HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
  246 + { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
  247 + { 0, 0, 0, 0, 0, 0, SCIF2, USBF,
  248 + 0, 0, STIF1, STIF0, 0, 0, USBH, GETHER,
  249 + PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1,
  250 + LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } },
  251 +};
  252 +
  253 +static struct intc_prio_reg prio_registers[] __initdata = {
  254 + { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
  255 + TMU2, TMU2_TICPI } },
  256 + { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
  257 + { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
  258 + { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC, ADC } },
  259 + { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
  260 + PCISERR, PCIINTA } },
  261 + { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
  262 + PCIINTD, PCIC5 } },
  263 + { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF0, USBF, MMCIF, SSI0 } },
  264 + { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SCIF2, GPIO } },
  265 + { 0xffd400a0, 0, 32, 8, /* INT2PRI8 */ { SSI3, SSI2, SSI1, 0 } },
  266 + { 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } },
  267 + { 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } },
  268 + { 0xffd400ac, 0, 32, 8, /* INT2PRI11 */ { PCC } },
  269 + { 0xffd400b0, 0, 32, 8, /* INT2PRI12 */ { 0, 0, USBH, GETHER } },
  270 + { 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } },
  271 +};
  272 +
  273 +static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups, priorities,
  274 + mask_registers, prio_registers, NULL);
  275 +
  276 +/* Support for external interrupt pins in IRQ mode */
  277 +
  278 +static struct intc_vect irq_vectors[] __initdata = {
  279 + INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
  280 + INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
  281 + INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
  282 + INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
  283 +};
  284 +
  285 +static struct intc_mask_reg irq_mask_registers[] __initdata = {
  286 + { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
  287 + { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
  288 +};
  289 +
  290 +static struct intc_prio_reg irq_prio_registers[] __initdata = {
  291 + { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
  292 + IRQ4, IRQ5, IRQ6, IRQ7 } },
  293 +};
  294 +
  295 +static struct intc_sense_reg irq_sense_registers[] __initdata = {
  296 + { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
  297 + IRQ4, IRQ5, IRQ6, IRQ7 } },
  298 +};
  299 +
  300 +static DECLARE_INTC_DESC(intc_irq_desc, "sh7763-irq", irq_vectors,
  301 + NULL, NULL, irq_mask_registers, irq_prio_registers,
  302 + irq_sense_registers);
  303 +
  304 +/* External interrupt pins in IRL mode */
  305 +
  306 +static struct intc_vect irl_vectors[] __initdata = {
  307 + INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
  308 + INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
  309 + INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
  310 + INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
  311 + INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
  312 + INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
  313 + INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
  314 + INTC_VECT(IRL_HHHL, 0x3c0),
  315 +};
  316 +
  317 +static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
  318 + { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
  319 + { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
  320 + IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
  321 + IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
  322 + IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
  323 +};
  324 +
  325 +static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
  326 + { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
  327 + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  328 + IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
  329 + IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
  330 + IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
  331 + IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
  332 +};
  333 +
  334 +static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7763-irl7654", irl_vectors,
  335 + NULL, NULL, irl7654_mask_registers, NULL, NULL);
  336 +
  337 +static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
  338 + NULL, NULL, irl3210_mask_registers, NULL, NULL);
  339 +
  340 +#define INTC_ICR0 0xffd00000
  341 +#define INTC_INTMSK0 0xffd00044
  342 +#define INTC_INTMSK1 0xffd00048
  343 +#define INTC_INTMSK2 0xffd40080
  344 +#define INTC_INTMSKCLR1 0xffd00068
  345 +#define INTC_INTMSKCLR2 0xffd40084
  346 +
  347 +void __init plat_irq_setup(void)
  348 +{
  349 + /* disable IRQ7-0 */
  350 + ctrl_outl(0xff000000, INTC_INTMSK0);
  351 +
  352 + /* disable IRL3-0 + IRL7-4 */
  353 + ctrl_outl(0xc0000000, INTC_INTMSK1);
  354 + ctrl_outl(0xfffefffe, INTC_INTMSK2);
  355 +
  356 + register_intc_controller(&intc_desc);
  357 +}
  358 +
  359 +void __init plat_irq_setup_pins(int mode)
  360 +{
  361 + switch (mode) {
  362 + case IRQ_MODE_IRQ:
  363 + /* select IRQ mode for IRL3-0 + IRL7-4 */
  364 + ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
  365 + register_intc_controller(&intc_irq_desc);
  366 + break;
  367 + case IRQ_MODE_IRL7654:
  368 + /* enable IRL7-4 but don't provide any masking */
  369 + ctrl_outl(0x40000000, INTC_INTMSKCLR1);
  370 + ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
  371 + break;
  372 + case IRQ_MODE_IRL3210:
  373 + /* enable IRL0-3 but don't provide any masking */
  374 + ctrl_outl(0x80000000, INTC_INTMSKCLR1);
  375 + ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
  376 + break;
  377 + case IRQ_MODE_IRL7654_MASK:
  378 + /* enable IRL7-4 and mask using cpu intc controller */
  379 + ctrl_outl(0x40000000, INTC_INTMSKCLR1);
  380 + register_intc_controller(&intc_irl7654_desc);
  381 + break;
  382 + case IRQ_MODE_IRL3210_MASK:
  383 + /* enable IRL0-3 and mask using cpu intc controller */
  384 + ctrl_outl(0x80000000, INTC_INTMSKCLR1);
  385 + register_intc_controller(&intc_irl3210_desc);
  386 + break;
  387 + default:
  388 + BUG();
  389 + }
  390 +}
arch/sh/kernel/setup.c
Diff comments   View file @ 7d740a0
... ... @@ -319,10 +319,10 @@
319 319 [CPU_SH7750R] = "SH7750R", [CPU_SH7751] = "SH7751",
320 320 [CPU_SH7751R] = "SH7751R", [CPU_SH7760] = "SH7760",
321 321 [CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
322   - [CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780",
323   - [CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343",
324   - [CPU_SH7785] = "SH7785", [CPU_SH7722] = "SH7722",
325   - [CPU_SHX3] = "SH-X3",
  322 + [CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770",
  323 + [CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781",
  324 + [CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
  325 + [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
326 326 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
327 327 [CPU_SH_NONE] = "Unknown"
328 328 };
drivers/serial/sh-sci.c
Diff comments   View file @ 7d740a0
... ... @@ -395,7 +395,8 @@
395 395 } else {
396 396 #ifdef CONFIG_CPU_SUBTYPE_SH7343
397 397 /* Nothing */
398   -#elif defined(CONFIG_CPU_SUBTYPE_SH7780) || \
  398 +#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
  399 + defined(CONFIG_CPU_SUBTYPE_SH7780) || \
399 400 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
400 401 defined(CONFIG_CPU_SUBTYPE_SHX3)
401 402 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
... ... @@ -408,6 +409,7 @@
408 409 #endif
409 410  
410 411 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
  412 + defined(CONFIG_CPU_SUBTYPE_SH7763) || \
411 413 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
412 414 defined(CONFIG_CPU_SUBTYPE_SH7785)
413 415 static inline int scif_txroom(struct uart_port *port)
drivers/serial/sh-sci.h
Diff comments   View file @ 7d740a0
... ... @@ -120,6 +120,12 @@
120 120 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
121 121 # define SCI_ONLY
122 122 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
  123 +#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
  124 +# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
  125 +# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
  126 +# define SCIF_ORER 0x0001 /* overrun error bit */
  127 +# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  128 +# define SCIF_ONLY
123 129 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
124 130 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
125 131 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
... ... @@ -419,6 +425,7 @@
419 425 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
420 426 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
421 427 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
  428 + defined(CONFIG_CPU_SUBTYPE_SH7763) || \
422 429 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
423 430 defined(CONFIG_CPU_SUBTYPE_SH7785)
424 431 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
... ... @@ -588,6 +595,15 @@
588 595 int ch = (port->mapbase - SMR0) >> 3;
589 596 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
590 597 }
  598 +#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
  599 +static inline int sci_rxd_in(struct uart_port *port)
  600 +{
  601 + if (port->mapbase == 0xffe00000)
  602 + return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
  603 + if (port->mapbase == 0xffe08000)
  604 + return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
  605 + return 1;
  606 +}
591 607 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
592 608 static inline int sci_rxd_in(struct uart_port *port)
593 609 {
... ... @@ -698,7 +714,8 @@
698 714 * -- Mitch Davis - 15 Jul 2000
699 715 */
700 716  
701   -#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
  717 +#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
  718 + defined(CONFIG_CPU_SUBTYPE_SH7780) || \
702 719 defined(CONFIG_CPU_SUBTYPE_SH7785)
703 720 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
704 721 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
include/asm-sh/bugs.h
Diff comments   View file @ 7d740a0
... ... @@ -35,7 +35,7 @@
35 35 case CPU_SH7750 ... CPU_SH4_501:
36 36 *p++ = '4';
37 37 break;
38   - case CPU_SH7770 ... CPU_SHX3:
  38 + case CPU_SH7763 ... CPU_SHX3:
39 39 *p++ = '4';
40 40 *p++ = 'a';
41 41 break;
include/asm-sh/cpu-sh4/freq.h
Diff comments   View file @ 7d740a0
... ... @@ -16,7 +16,8 @@
16 16 #define SCLKACR 0xa4150008
17 17 #define SCLKBCR 0xa415000c
18 18 #define IrDACLKCR 0xa4150010
19   -#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
  19 +#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
  20 + defined(CONFIG_CPU_SUBTYPE_SH7780)
20 21 #define FRQCR 0xffc80000
21 22 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
22 23 #define FRQCR0 0xffc80000
include/asm-sh/processor.h
Diff comments   View file @ 7d740a0
... ... @@ -30,7 +30,7 @@
30 30 CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
31 31  
32 32 /* SH-4A types */
33   - CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3,
  33 + CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3,
34 34  
35 35 /* SH4AL-DSP types */
36 36 CPU_SH7343, CPU_SH7722,