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Commit 7d8dd20e56be0196fd015feb19ca38449c607794

Authored by Tushar Behera
Committed by Linus Walleij
1 parent 5f007db68c
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

pinctrl: SPEAr: Update error check for unsigned variables 

Checking '< 0' for unsigned variables always returns false. For error
codes, use IS_ERR_VALUE() instead.

Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

drivers/pinctrl/spear/pinctrl-plgpio.c
Diff comments   View file @ 7d8dd20
1 /* 1 /*
2 * SPEAr platform PLGPIO driver 2 * SPEAr platform PLGPIO driver
3 * 3 *
4 * Copyright (C) 2012 ST Microelectronics 4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@linaro.org> 5 * Viresh Kumar <viresh.kumar@linaro.org>
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any 8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied. 9 * warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12 #include <linux/clk.h> 12 #include <linux/clk.h>
13 #include <linux/err.h> 13 #include <linux/err.h>
14 #include <linux/gpio.h> 14 #include <linux/gpio.h>
15 #include <linux/io.h> 15 #include <linux/io.h>
16 #include <linux/irq.h> 16 #include <linux/irq.h>
17 #include <linux/irqdomain.h> 17 #include <linux/irqdomain.h>
18 #include <linux/module.h> 18 #include <linux/module.h>
19 #include <linux/pinctrl/consumer.h> 19 #include <linux/pinctrl/consumer.h>
20 #include <linux/platform_device.h> 20 #include <linux/platform_device.h>
21 #include <linux/pm.h> 21 #include <linux/pm.h>
22 #include <linux/spinlock.h> 22 #include <linux/spinlock.h>
23 #include <asm/mach/irq.h> 23 #include <asm/mach/irq.h>
24 24
25 #define MAX_GPIO_PER_REG 32 25 #define MAX_GPIO_PER_REG 32
26 #define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG) 26 #define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG)
27 #define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \ 27 #define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \
28 * sizeof(int *)) 28 * sizeof(int *))
29 29
30 /* 30 /*
31 * plgpio pins in all machines are not one to one mapped, bitwise with registers 31 * plgpio pins in all machines are not one to one mapped, bitwise with registers
32 * bits. These set of macros define register masks for which below functions 32 * bits. These set of macros define register masks for which below functions
33 * (pin_to_offset and offset_to_pin) are required to be called. 33 * (pin_to_offset and offset_to_pin) are required to be called.
34 */ 34 */
35 #define PTO_ENB_REG 0x001 35 #define PTO_ENB_REG 0x001
36 #define PTO_WDATA_REG 0x002 36 #define PTO_WDATA_REG 0x002
37 #define PTO_DIR_REG 0x004 37 #define PTO_DIR_REG 0x004
38 #define PTO_IE_REG 0x008 38 #define PTO_IE_REG 0x008
39 #define PTO_RDATA_REG 0x010 39 #define PTO_RDATA_REG 0x010
40 #define PTO_MIS_REG 0x020 40 #define PTO_MIS_REG 0x020
41 41
42 struct plgpio_regs { 42 struct plgpio_regs {
43 u32 enb; /* enable register */ 43 u32 enb; /* enable register */
44 u32 wdata; /* write data register */ 44 u32 wdata; /* write data register */
45 u32 dir; /* direction set register */ 45 u32 dir; /* direction set register */
46 u32 rdata; /* read data register */ 46 u32 rdata; /* read data register */
47 u32 ie; /* interrupt enable register */ 47 u32 ie; /* interrupt enable register */
48 u32 mis; /* mask interrupt status register */ 48 u32 mis; /* mask interrupt status register */
49 u32 eit; /* edge interrupt type */ 49 u32 eit; /* edge interrupt type */
50 }; 50 };
51 51
52 /* 52 /*
53 * struct plgpio: plgpio driver specific structure 53 * struct plgpio: plgpio driver specific structure
54 * 54 *
55 * lock: lock for guarding gpio registers 55 * lock: lock for guarding gpio registers
56 * base: base address of plgpio block 56 * base: base address of plgpio block
57 * irq_base: irq number of plgpio0 57 * irq_base: irq number of plgpio0
58 * chip: gpio framework specific chip information structure 58 * chip: gpio framework specific chip information structure
59 * p2o: function ptr for pin to offset conversion. This is required only for 59 * p2o: function ptr for pin to offset conversion. This is required only for
60 * machines where mapping b/w pin and offset is not 1-to-1. 60 * machines where mapping b/w pin and offset is not 1-to-1.
61 * o2p: function ptr for offset to pin conversion. This is required only for 61 * o2p: function ptr for offset to pin conversion. This is required only for
62 * machines where mapping b/w pin and offset is not 1-to-1. 62 * machines where mapping b/w pin and offset is not 1-to-1.
63 * p2o_regs: mask of registers for which p2o and o2p are applicable 63 * p2o_regs: mask of registers for which p2o and o2p are applicable
64 * regs: register offsets 64 * regs: register offsets
65 * csave_regs: context save registers for standby/sleep/hibernate cases 65 * csave_regs: context save registers for standby/sleep/hibernate cases
66 */ 66 */
67 struct plgpio { 67 struct plgpio {
68 spinlock_t lock; 68 spinlock_t lock;
69 void __iomem *base; 69 void __iomem *base;
70 struct clk *clk; 70 struct clk *clk;
71 unsigned irq_base; 71 unsigned irq_base;
72 struct irq_domain *irq_domain; 72 struct irq_domain *irq_domain;
73 struct gpio_chip chip; 73 struct gpio_chip chip;
74 int (*p2o)(int pin); /* pin_to_offset */ 74 int (*p2o)(int pin); /* pin_to_offset */
75 int (*o2p)(int offset); /* offset_to_pin */ 75 int (*o2p)(int offset); /* offset_to_pin */
76 u32 p2o_regs; 76 u32 p2o_regs;
77 struct plgpio_regs regs; 77 struct plgpio_regs regs;
78 #ifdef CONFIG_PM 78 #ifdef CONFIG_PM
79 struct plgpio_regs *csave_regs; 79 struct plgpio_regs *csave_regs;
80 #endif 80 #endif
81 }; 81 };
82 82
83 /* register manipulation inline functions */ 83 /* register manipulation inline functions */
84 static inline u32 is_plgpio_set(void __iomem *base, u32 pin, u32 reg) 84 static inline u32 is_plgpio_set(void __iomem *base, u32 pin, u32 reg)
85 { 85 {
86 u32 offset = PIN_OFFSET(pin); 86 u32 offset = PIN_OFFSET(pin);
87 void __iomem *reg_off = REG_OFFSET(base, reg, pin); 87 void __iomem *reg_off = REG_OFFSET(base, reg, pin);
88 u32 val = readl_relaxed(reg_off); 88 u32 val = readl_relaxed(reg_off);
89 89
90 return !!(val & (1 << offset)); 90 return !!(val & (1 << offset));
91 } 91 }
92 92
93 static inline void plgpio_reg_set(void __iomem *base, u32 pin, u32 reg) 93 static inline void plgpio_reg_set(void __iomem *base, u32 pin, u32 reg)
94 { 94 {
95 u32 offset = PIN_OFFSET(pin); 95 u32 offset = PIN_OFFSET(pin);
96 void __iomem *reg_off = REG_OFFSET(base, reg, pin); 96 void __iomem *reg_off = REG_OFFSET(base, reg, pin);
97 u32 val = readl_relaxed(reg_off); 97 u32 val = readl_relaxed(reg_off);
98 98
99 writel_relaxed(val | (1 << offset), reg_off); 99 writel_relaxed(val | (1 << offset), reg_off);
100 } 100 }
101 101
102 static inline void plgpio_reg_reset(void __iomem *base, u32 pin, u32 reg) 102 static inline void plgpio_reg_reset(void __iomem *base, u32 pin, u32 reg)
103 { 103 {
104 u32 offset = PIN_OFFSET(pin); 104 u32 offset = PIN_OFFSET(pin);
105 void __iomem *reg_off = REG_OFFSET(base, reg, pin); 105 void __iomem *reg_off = REG_OFFSET(base, reg, pin);
106 u32 val = readl_relaxed(reg_off); 106 u32 val = readl_relaxed(reg_off);
107 107
108 writel_relaxed(val & ~(1 << offset), reg_off); 108 writel_relaxed(val & ~(1 << offset), reg_off);
109 } 109 }
110 110
111 /* gpio framework specific routines */ 111 /* gpio framework specific routines */
112 static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset) 112 static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset)
113 { 113 {
114 struct plgpio *plgpio = container_of(chip, struct plgpio, chip); 114 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
115 unsigned long flags; 115 unsigned long flags;
116 116
117 /* get correct offset for "offset" pin */ 117 /* get correct offset for "offset" pin */
118 if (plgpio->p2o && (plgpio->p2o_regs & PTO_DIR_REG)) { 118 if (plgpio->p2o && (plgpio->p2o_regs & PTO_DIR_REG)) {
119 offset = plgpio->p2o(offset); 119 offset = plgpio->p2o(offset);
120 if (offset == -1) 120 if (offset == -1)
121 return -EINVAL; 121 return -EINVAL;
122 } 122 }
123 123
124 spin_lock_irqsave(&plgpio->lock, flags); 124 spin_lock_irqsave(&plgpio->lock, flags);
125 plgpio_reg_set(plgpio->base, offset, plgpio->regs.dir); 125 plgpio_reg_set(plgpio->base, offset, plgpio->regs.dir);
126 spin_unlock_irqrestore(&plgpio->lock, flags); 126 spin_unlock_irqrestore(&plgpio->lock, flags);
127 127
128 return 0; 128 return 0;
129 } 129 }
130 130
131 static int plgpio_direction_output(struct gpio_chip *chip, unsigned offset, 131 static int plgpio_direction_output(struct gpio_chip *chip, unsigned offset,
132 int value) 132 int value)
133 { 133 {
134 struct plgpio *plgpio = container_of(chip, struct plgpio, chip); 134 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
135 unsigned long flags; 135 unsigned long flags;
136 unsigned dir_offset = offset, wdata_offset = offset, tmp; 136 unsigned dir_offset = offset, wdata_offset = offset, tmp;
137 137
138 /* get correct offset for "offset" pin */ 138 /* get correct offset for "offset" pin */
139 if (plgpio->p2o && (plgpio->p2o_regs & (PTO_DIR_REG | PTO_WDATA_REG))) { 139 if (plgpio->p2o && (plgpio->p2o_regs & (PTO_DIR_REG | PTO_WDATA_REG))) {
140 tmp = plgpio->p2o(offset); 140 tmp = plgpio->p2o(offset);
141 if (tmp == -1) 141 if (tmp == -1)
142 return -EINVAL; 142 return -EINVAL;
143 143
144 if (plgpio->p2o_regs & PTO_DIR_REG) 144 if (plgpio->p2o_regs & PTO_DIR_REG)
145 dir_offset = tmp; 145 dir_offset = tmp;
146 if (plgpio->p2o_regs & PTO_WDATA_REG) 146 if (plgpio->p2o_regs & PTO_WDATA_REG)
147 wdata_offset = tmp; 147 wdata_offset = tmp;
148 } 148 }
149 149
150 spin_lock_irqsave(&plgpio->lock, flags); 150 spin_lock_irqsave(&plgpio->lock, flags);
151 if (value) 151 if (value)
152 plgpio_reg_set(plgpio->base, wdata_offset, 152 plgpio_reg_set(plgpio->base, wdata_offset,
153 plgpio->regs.wdata); 153 plgpio->regs.wdata);
154 else 154 else
155 plgpio_reg_reset(plgpio->base, wdata_offset, 155 plgpio_reg_reset(plgpio->base, wdata_offset,
156 plgpio->regs.wdata); 156 plgpio->regs.wdata);
157 157
158 plgpio_reg_reset(plgpio->base, dir_offset, plgpio->regs.dir); 158 plgpio_reg_reset(plgpio->base, dir_offset, plgpio->regs.dir);
159 spin_unlock_irqrestore(&plgpio->lock, flags); 159 spin_unlock_irqrestore(&plgpio->lock, flags);
160 160
161 return 0; 161 return 0;
162 } 162 }
163 163
164 static int plgpio_get_value(struct gpio_chip *chip, unsigned offset) 164 static int plgpio_get_value(struct gpio_chip *chip, unsigned offset)
165 { 165 {
166 struct plgpio *plgpio = container_of(chip, struct plgpio, chip); 166 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
167 167
168 if (offset >= chip->ngpio) 168 if (offset >= chip->ngpio)
169 return -EINVAL; 169 return -EINVAL;
170 170
171 /* get correct offset for "offset" pin */ 171 /* get correct offset for "offset" pin */
172 if (plgpio->p2o && (plgpio->p2o_regs & PTO_RDATA_REG)) { 172 if (plgpio->p2o && (plgpio->p2o_regs & PTO_RDATA_REG)) {
173 offset = plgpio->p2o(offset); 173 offset = plgpio->p2o(offset);
174 if (offset == -1) 174 if (offset == -1)
175 return -EINVAL; 175 return -EINVAL;
176 } 176 }
177 177
178 return is_plgpio_set(plgpio->base, offset, plgpio->regs.rdata); 178 return is_plgpio_set(plgpio->base, offset, plgpio->regs.rdata);
179 } 179 }
180 180
181 static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value) 181 static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
182 { 182 {
183 struct plgpio *plgpio = container_of(chip, struct plgpio, chip); 183 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
184 184
185 if (offset >= chip->ngpio) 185 if (offset >= chip->ngpio)
186 return; 186 return;
187 187
188 /* get correct offset for "offset" pin */ 188 /* get correct offset for "offset" pin */
189 if (plgpio->p2o && (plgpio->p2o_regs & PTO_WDATA_REG)) { 189 if (plgpio->p2o && (plgpio->p2o_regs & PTO_WDATA_REG)) {
190 offset = plgpio->p2o(offset); 190 offset = plgpio->p2o(offset);
191 if (offset == -1) 191 if (offset == -1)
192 return; 192 return;
193 } 193 }
194 194
195 if (value) 195 if (value)
196 plgpio_reg_set(plgpio->base, offset, plgpio->regs.wdata); 196 plgpio_reg_set(plgpio->base, offset, plgpio->regs.wdata);
197 else 197 else
198 plgpio_reg_reset(plgpio->base, offset, plgpio->regs.wdata); 198 plgpio_reg_reset(plgpio->base, offset, plgpio->regs.wdata);
199 } 199 }
200 200
201 static int plgpio_request(struct gpio_chip *chip, unsigned offset) 201 static int plgpio_request(struct gpio_chip *chip, unsigned offset)
202 { 202 {
203 struct plgpio *plgpio = container_of(chip, struct plgpio, chip); 203 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
204 int gpio = chip->base + offset; 204 int gpio = chip->base + offset;
205 unsigned long flags; 205 unsigned long flags;
206 int ret = 0; 206 int ret = 0;
207 207
208 if (offset >= chip->ngpio) 208 if (offset >= chip->ngpio)
209 return -EINVAL; 209 return -EINVAL;
210 210
211 ret = pinctrl_request_gpio(gpio); 211 ret = pinctrl_request_gpio(gpio);
212 if (ret) 212 if (ret)
213 return ret; 213 return ret;
214 214
215 if (!IS_ERR(plgpio->clk)) { 215 if (!IS_ERR(plgpio->clk)) {
216 ret = clk_enable(plgpio->clk); 216 ret = clk_enable(plgpio->clk);
217 if (ret) 217 if (ret)
218 goto err0; 218 goto err0;
219 } 219 }
220 220
221 if (plgpio->regs.enb == -1) 221 if (plgpio->regs.enb == -1)
222 return 0; 222 return 0;
223 223
224 /* 224 /*
225 * put gpio in IN mode before enabling it. This make enabling gpio safe 225 * put gpio in IN mode before enabling it. This make enabling gpio safe
226 */ 226 */
227 ret = plgpio_direction_input(chip, offset); 227 ret = plgpio_direction_input(chip, offset);
228 if (ret) 228 if (ret)
229 goto err1; 229 goto err1;
230 230
231 /* get correct offset for "offset" pin */ 231 /* get correct offset for "offset" pin */
232 if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) { 232 if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
233 offset = plgpio->p2o(offset); 233 offset = plgpio->p2o(offset);
234 if (offset == -1) { 234 if (offset == -1) {
235 ret = -EINVAL; 235 ret = -EINVAL;
236 goto err1; 236 goto err1;
237 } 237 }
238 } 238 }
239 239
240 spin_lock_irqsave(&plgpio->lock, flags); 240 spin_lock_irqsave(&plgpio->lock, flags);
241 plgpio_reg_set(plgpio->base, offset, plgpio->regs.enb); 241 plgpio_reg_set(plgpio->base, offset, plgpio->regs.enb);
242 spin_unlock_irqrestore(&plgpio->lock, flags); 242 spin_unlock_irqrestore(&plgpio->lock, flags);
243 return 0; 243 return 0;
244 244
245 err1: 245 err1:
246 if (!IS_ERR(plgpio->clk)) 246 if (!IS_ERR(plgpio->clk))
247 clk_disable(plgpio->clk); 247 clk_disable(plgpio->clk);
248 err0: 248 err0:
249 pinctrl_free_gpio(gpio); 249 pinctrl_free_gpio(gpio);
250 return ret; 250 return ret;
251 } 251 }
252 252
253 static void plgpio_free(struct gpio_chip *chip, unsigned offset) 253 static void plgpio_free(struct gpio_chip *chip, unsigned offset)
254 { 254 {
255 struct plgpio *plgpio = container_of(chip, struct plgpio, chip); 255 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
256 int gpio = chip->base + offset; 256 int gpio = chip->base + offset;
257 unsigned long flags; 257 unsigned long flags;
258 258
259 if (offset >= chip->ngpio) 259 if (offset >= chip->ngpio)
260 return; 260 return;
261 261
262 if (plgpio->regs.enb == -1) 262 if (plgpio->regs.enb == -1)
263 goto disable_clk; 263 goto disable_clk;
264 264
265 /* get correct offset for "offset" pin */ 265 /* get correct offset for "offset" pin */
266 if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) { 266 if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
267 offset = plgpio->p2o(offset); 267 offset = plgpio->p2o(offset);
268 if (offset == -1) 268 if (offset == -1)
269 return; 269 return;
270 } 270 }
271 271
272 spin_lock_irqsave(&plgpio->lock, flags); 272 spin_lock_irqsave(&plgpio->lock, flags);
273 plgpio_reg_reset(plgpio->base, offset, plgpio->regs.enb); 273 plgpio_reg_reset(plgpio->base, offset, plgpio->regs.enb);
274 spin_unlock_irqrestore(&plgpio->lock, flags); 274 spin_unlock_irqrestore(&plgpio->lock, flags);
275 275
276 disable_clk: 276 disable_clk:
277 if (!IS_ERR(plgpio->clk)) 277 if (!IS_ERR(plgpio->clk))
278 clk_disable(plgpio->clk); 278 clk_disable(plgpio->clk);
279 279
280 pinctrl_free_gpio(gpio); 280 pinctrl_free_gpio(gpio);
281 } 281 }
282 282
283 static int plgpio_to_irq(struct gpio_chip *chip, unsigned offset) 283 static int plgpio_to_irq(struct gpio_chip *chip, unsigned offset)
284 { 284 {
285 struct plgpio *plgpio = container_of(chip, struct plgpio, chip); 285 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
286 286
287 if (plgpio->irq_base < 0) 287 if (IS_ERR_VALUE(plgpio->irq_base))
288 return -EINVAL; 288 return -EINVAL;
289 289
290 return irq_find_mapping(plgpio->irq_domain, offset); 290 return irq_find_mapping(plgpio->irq_domain, offset);
291 } 291 }
292 292
293 /* PLGPIO IRQ */ 293 /* PLGPIO IRQ */
294 static void plgpio_irq_disable(struct irq_data *d) 294 static void plgpio_irq_disable(struct irq_data *d)
295 { 295 {
296 struct plgpio *plgpio = irq_data_get_irq_chip_data(d); 296 struct plgpio *plgpio = irq_data_get_irq_chip_data(d);
297 int offset = d->irq - plgpio->irq_base; 297 int offset = d->irq - plgpio->irq_base;
298 unsigned long flags; 298 unsigned long flags;
299 299
300 /* get correct offset for "offset" pin */ 300 /* get correct offset for "offset" pin */
301 if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) { 301 if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
302 offset = plgpio->p2o(offset); 302 offset = plgpio->p2o(offset);
303 if (offset == -1) 303 if (offset == -1)
304 return; 304 return;
305 } 305 }
306 306
307 spin_lock_irqsave(&plgpio->lock, flags); 307 spin_lock_irqsave(&plgpio->lock, flags);
308 plgpio_reg_set(plgpio->base, offset, plgpio->regs.ie); 308 plgpio_reg_set(plgpio->base, offset, plgpio->regs.ie);
309 spin_unlock_irqrestore(&plgpio->lock, flags); 309 spin_unlock_irqrestore(&plgpio->lock, flags);
310 } 310 }
311 311
312 static void plgpio_irq_enable(struct irq_data *d) 312 static void plgpio_irq_enable(struct irq_data *d)
313 { 313 {
314 struct plgpio *plgpio = irq_data_get_irq_chip_data(d); 314 struct plgpio *plgpio = irq_data_get_irq_chip_data(d);
315 int offset = d->irq - plgpio->irq_base; 315 int offset = d->irq - plgpio->irq_base;
316 unsigned long flags; 316 unsigned long flags;
317 317
318 /* get correct offset for "offset" pin */ 318 /* get correct offset for "offset" pin */
319 if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) { 319 if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
320 offset = plgpio->p2o(offset); 320 offset = plgpio->p2o(offset);
321 if (offset == -1) 321 if (offset == -1)
322 return; 322 return;
323 } 323 }
324 324
325 spin_lock_irqsave(&plgpio->lock, flags); 325 spin_lock_irqsave(&plgpio->lock, flags);
326 plgpio_reg_reset(plgpio->base, offset, plgpio->regs.ie); 326 plgpio_reg_reset(plgpio->base, offset, plgpio->regs.ie);
327 spin_unlock_irqrestore(&plgpio->lock, flags); 327 spin_unlock_irqrestore(&plgpio->lock, flags);
328 } 328 }
329 329
330 static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger) 330 static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger)
331 { 331 {
332 struct plgpio *plgpio = irq_data_get_irq_chip_data(d); 332 struct plgpio *plgpio = irq_data_get_irq_chip_data(d);
333 int offset = d->irq - plgpio->irq_base; 333 int offset = d->irq - plgpio->irq_base;
334 void __iomem *reg_off; 334 void __iomem *reg_off;
335 unsigned int supported_type = 0, val; 335 unsigned int supported_type = 0, val;
336 336
337 if (offset >= plgpio->chip.ngpio) 337 if (offset >= plgpio->chip.ngpio)
338 return -EINVAL; 338 return -EINVAL;
339 339
340 if (plgpio->regs.eit == -1) 340 if (plgpio->regs.eit == -1)
341 supported_type = IRQ_TYPE_LEVEL_HIGH; 341 supported_type = IRQ_TYPE_LEVEL_HIGH;
342 else 342 else
343 supported_type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 343 supported_type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
344 344
345 if (!(trigger & supported_type)) 345 if (!(trigger & supported_type))
346 return -EINVAL; 346 return -EINVAL;
347 347
348 if (plgpio->regs.eit == -1) 348 if (plgpio->regs.eit == -1)
349 return 0; 349 return 0;
350 350
351 reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset); 351 reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset);
352 val = readl_relaxed(reg_off); 352 val = readl_relaxed(reg_off);
353 353
354 offset = PIN_OFFSET(offset); 354 offset = PIN_OFFSET(offset);
355 if (trigger & IRQ_TYPE_EDGE_RISING) 355 if (trigger & IRQ_TYPE_EDGE_RISING)
356 writel_relaxed(val | (1 << offset), reg_off); 356 writel_relaxed(val | (1 << offset), reg_off);
357 else 357 else
358 writel_relaxed(val & ~(1 << offset), reg_off); 358 writel_relaxed(val & ~(1 << offset), reg_off);
359 359
360 return 0; 360 return 0;
361 } 361 }
362 362
363 static struct irq_chip plgpio_irqchip = { 363 static struct irq_chip plgpio_irqchip = {
364 .name = "PLGPIO", 364 .name = "PLGPIO",
365 .irq_enable = plgpio_irq_enable, 365 .irq_enable = plgpio_irq_enable,
366 .irq_disable = plgpio_irq_disable, 366 .irq_disable = plgpio_irq_disable,
367 .irq_set_type = plgpio_irq_set_type, 367 .irq_set_type = plgpio_irq_set_type,
368 }; 368 };
369 369
370 static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc) 370 static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc)
371 { 371 {
372 struct plgpio *plgpio = irq_get_handler_data(irq); 372 struct plgpio *plgpio = irq_get_handler_data(irq);
373 struct irq_chip *irqchip = irq_desc_get_chip(desc); 373 struct irq_chip *irqchip = irq_desc_get_chip(desc);
374 int regs_count, count, pin, offset, i = 0; 374 int regs_count, count, pin, offset, i = 0;
375 unsigned long pending; 375 unsigned long pending;
376 376
377 count = plgpio->chip.ngpio; 377 count = plgpio->chip.ngpio;
378 regs_count = DIV_ROUND_UP(count, MAX_GPIO_PER_REG); 378 regs_count = DIV_ROUND_UP(count, MAX_GPIO_PER_REG);
379 379
380 chained_irq_enter(irqchip, desc); 380 chained_irq_enter(irqchip, desc);
381 /* check all plgpio MIS registers for a possible interrupt */ 381 /* check all plgpio MIS registers for a possible interrupt */
382 for (; i < regs_count; i++) { 382 for (; i < regs_count; i++) {
383 pending = readl_relaxed(plgpio->base + plgpio->regs.mis + 383 pending = readl_relaxed(plgpio->base + plgpio->regs.mis +
384 i * sizeof(int *)); 384 i * sizeof(int *));
385 if (!pending) 385 if (!pending)
386 continue; 386 continue;
387 387
388 /* clear interrupts */ 388 /* clear interrupts */
389 writel_relaxed(~pending, plgpio->base + plgpio->regs.mis + 389 writel_relaxed(~pending, plgpio->base + plgpio->regs.mis +
390 i * sizeof(int *)); 390 i * sizeof(int *));
391 /* 391 /*
392 * clear extra bits in last register having gpios < MAX/REG 392 * clear extra bits in last register having gpios < MAX/REG
393 * ex: Suppose there are max 102 plgpios. then last register 393 * ex: Suppose there are max 102 plgpios. then last register
394 * must have only (102 - MAX_GPIO_PER_REG * 3) = 6 relevant bits 394 * must have only (102 - MAX_GPIO_PER_REG * 3) = 6 relevant bits
395 * so, we must not take other 28 bits into consideration for 395 * so, we must not take other 28 bits into consideration for
396 * checking interrupt. so clear those bits. 396 * checking interrupt. so clear those bits.
397 */ 397 */
398 count = count - i * MAX_GPIO_PER_REG; 398 count = count - i * MAX_GPIO_PER_REG;
399 if (count < MAX_GPIO_PER_REG) 399 if (count < MAX_GPIO_PER_REG)
400 pending &= (1 << count) - 1; 400 pending &= (1 << count) - 1;
401 401
402 for_each_set_bit(offset, &pending, MAX_GPIO_PER_REG) { 402 for_each_set_bit(offset, &pending, MAX_GPIO_PER_REG) {
403 /* get correct pin for "offset" */ 403 /* get correct pin for "offset" */
404 if (plgpio->o2p && (plgpio->p2o_regs & PTO_MIS_REG)) { 404 if (plgpio->o2p && (plgpio->p2o_regs & PTO_MIS_REG)) {
405 pin = plgpio->o2p(offset); 405 pin = plgpio->o2p(offset);
406 if (pin == -1) 406 if (pin == -1)
407 continue; 407 continue;
408 } else 408 } else
409 pin = offset; 409 pin = offset;
410 410
411 /* get correct irq line number */ 411 /* get correct irq line number */
412 pin = i * MAX_GPIO_PER_REG + pin; 412 pin = i * MAX_GPIO_PER_REG + pin;
413 generic_handle_irq(plgpio_to_irq(&plgpio->chip, pin)); 413 generic_handle_irq(plgpio_to_irq(&plgpio->chip, pin));
414 } 414 }
415 } 415 }
416 chained_irq_exit(irqchip, desc); 416 chained_irq_exit(irqchip, desc);
417 } 417 }
418 418
419 /* 419 /*
420 * pin to offset and offset to pin converter functions 420 * pin to offset and offset to pin converter functions
421 * 421 *
422 * In spear310 there is inconsistency among bit positions in plgpio regiseters, 422 * In spear310 there is inconsistency among bit positions in plgpio regiseters,
423 * for different plgpio pins. For example: for pin 27, bit offset is 23, pin 423 * for different plgpio pins. For example: for pin 27, bit offset is 23, pin
424 * 28-33 are not supported, pin 95 has offset bit 95, bit 100 has offset bit 1 424 * 28-33 are not supported, pin 95 has offset bit 95, bit 100 has offset bit 1
425 */ 425 */
426 static int spear310_p2o(int pin) 426 static int spear310_p2o(int pin)
427 { 427 {
428 int offset = pin; 428 int offset = pin;
429 429
430 if (pin <= 27) 430 if (pin <= 27)
431 offset += 4; 431 offset += 4;
432 else if (pin <= 33) 432 else if (pin <= 33)
433 offset = -1; 433 offset = -1;
434 else if (pin <= 97) 434 else if (pin <= 97)
435 offset -= 2; 435 offset -= 2;
436 else if (pin <= 101) 436 else if (pin <= 101)
437 offset = 101 - pin; 437 offset = 101 - pin;
438 else 438 else
439 offset = -1; 439 offset = -1;
440 440
441 return offset; 441 return offset;
442 } 442 }
443 443
444 int spear310_o2p(int offset) 444 int spear310_o2p(int offset)
445 { 445 {
446 if (offset <= 3) 446 if (offset <= 3)
447 return 101 - offset; 447 return 101 - offset;
448 else if (offset <= 31) 448 else if (offset <= 31)
449 return offset - 4; 449 return offset - 4;
450 else 450 else
451 return offset + 2; 451 return offset + 2;
452 } 452 }
453 453
454 static int __devinit plgpio_probe_dt(struct platform_device *pdev, 454 static int __devinit plgpio_probe_dt(struct platform_device *pdev,
455 struct plgpio *plgpio) 455 struct plgpio *plgpio)
456 { 456 {
457 struct device_node *np = pdev->dev.of_node; 457 struct device_node *np = pdev->dev.of_node;
458 int ret = -EINVAL; 458 int ret = -EINVAL;
459 u32 val; 459 u32 val;
460 460
461 if (of_machine_is_compatible("st,spear310")) { 461 if (of_machine_is_compatible("st,spear310")) {
462 plgpio->p2o = spear310_p2o; 462 plgpio->p2o = spear310_p2o;
463 plgpio->o2p = spear310_o2p; 463 plgpio->o2p = spear310_o2p;
464 plgpio->p2o_regs = PTO_WDATA_REG | PTO_DIR_REG | PTO_IE_REG | 464 plgpio->p2o_regs = PTO_WDATA_REG | PTO_DIR_REG | PTO_IE_REG |
465 PTO_RDATA_REG | PTO_MIS_REG; 465 PTO_RDATA_REG | PTO_MIS_REG;
466 } 466 }
467 467
468 if (!of_property_read_u32(np, "st-plgpio,ngpio", &val)) { 468 if (!of_property_read_u32(np, "st-plgpio,ngpio", &val)) {
469 plgpio->chip.ngpio = val; 469 plgpio->chip.ngpio = val;
470 } else { 470 } else {
471 dev_err(&pdev->dev, "DT: Invalid ngpio field\n"); 471 dev_err(&pdev->dev, "DT: Invalid ngpio field\n");
472 goto end; 472 goto end;
473 } 473 }
474 474
475 if (!of_property_read_u32(np, "st-plgpio,enb-reg", &val)) 475 if (!of_property_read_u32(np, "st-plgpio,enb-reg", &val))
476 plgpio->regs.enb = val; 476 plgpio->regs.enb = val;
477 else 477 else
478 plgpio->regs.enb = -1; 478 plgpio->regs.enb = -1;
479 479
480 if (!of_property_read_u32(np, "st-plgpio,wdata-reg", &val)) { 480 if (!of_property_read_u32(np, "st-plgpio,wdata-reg", &val)) {
481 plgpio->regs.wdata = val; 481 plgpio->regs.wdata = val;
482 } else { 482 } else {
483 dev_err(&pdev->dev, "DT: Invalid wdata reg\n"); 483 dev_err(&pdev->dev, "DT: Invalid wdata reg\n");
484 goto end; 484 goto end;
485 } 485 }
486 486
487 if (!of_property_read_u32(np, "st-plgpio,dir-reg", &val)) { 487 if (!of_property_read_u32(np, "st-plgpio,dir-reg", &val)) {
488 plgpio->regs.dir = val; 488 plgpio->regs.dir = val;
489 } else { 489 } else {
490 dev_err(&pdev->dev, "DT: Invalid dir reg\n"); 490 dev_err(&pdev->dev, "DT: Invalid dir reg\n");
491 goto end; 491 goto end;
492 } 492 }
493 493
494 if (!of_property_read_u32(np, "st-plgpio,ie-reg", &val)) { 494 if (!of_property_read_u32(np, "st-plgpio,ie-reg", &val)) {
495 plgpio->regs.ie = val; 495 plgpio->regs.ie = val;
496 } else { 496 } else {
497 dev_err(&pdev->dev, "DT: Invalid ie reg\n"); 497 dev_err(&pdev->dev, "DT: Invalid ie reg\n");
498 goto end; 498 goto end;
499 } 499 }
500 500
501 if (!of_property_read_u32(np, "st-plgpio,rdata-reg", &val)) { 501 if (!of_property_read_u32(np, "st-plgpio,rdata-reg", &val)) {
502 plgpio->regs.rdata = val; 502 plgpio->regs.rdata = val;
503 } else { 503 } else {
504 dev_err(&pdev->dev, "DT: Invalid rdata reg\n"); 504 dev_err(&pdev->dev, "DT: Invalid rdata reg\n");
505 goto end; 505 goto end;
506 } 506 }
507 507
508 if (!of_property_read_u32(np, "st-plgpio,mis-reg", &val)) { 508 if (!of_property_read_u32(np, "st-plgpio,mis-reg", &val)) {
509 plgpio->regs.mis = val; 509 plgpio->regs.mis = val;
510 } else { 510 } else {
511 dev_err(&pdev->dev, "DT: Invalid mis reg\n"); 511 dev_err(&pdev->dev, "DT: Invalid mis reg\n");
512 goto end; 512 goto end;
513 } 513 }
514 514
515 if (!of_property_read_u32(np, "st-plgpio,eit-reg", &val)) 515 if (!of_property_read_u32(np, "st-plgpio,eit-reg", &val))
516 plgpio->regs.eit = val; 516 plgpio->regs.eit = val;
517 else 517 else
518 plgpio->regs.eit = -1; 518 plgpio->regs.eit = -1;
519 519
520 return 0; 520 return 0;
521 521
522 end: 522 end:
523 return ret; 523 return ret;
524 } 524 }
525 static int __devinit plgpio_probe(struct platform_device *pdev) 525 static int __devinit plgpio_probe(struct platform_device *pdev)
526 { 526 {
527 struct device_node *np = pdev->dev.of_node; 527 struct device_node *np = pdev->dev.of_node;
528 struct plgpio *plgpio; 528 struct plgpio *plgpio;
529 struct resource *res; 529 struct resource *res;
530 int ret, irq, i; 530 int ret, irq, i;
531 531
532 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 532 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
533 if (!res) { 533 if (!res) {
534 dev_err(&pdev->dev, "invalid IORESOURCE_MEM\n"); 534 dev_err(&pdev->dev, "invalid IORESOURCE_MEM\n");
535 return -EBUSY; 535 return -EBUSY;
536 } 536 }
537 537
538 plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL); 538 plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL);
539 if (!plgpio) { 539 if (!plgpio) {
540 dev_err(&pdev->dev, "memory allocation fail\n"); 540 dev_err(&pdev->dev, "memory allocation fail\n");
541 return -ENOMEM; 541 return -ENOMEM;
542 } 542 }
543 543
544 plgpio->base = devm_request_and_ioremap(&pdev->dev, res); 544 plgpio->base = devm_request_and_ioremap(&pdev->dev, res);
545 if (!plgpio->base) { 545 if (!plgpio->base) {
546 dev_err(&pdev->dev, "request and ioremap fail\n"); 546 dev_err(&pdev->dev, "request and ioremap fail\n");
547 return -ENOMEM; 547 return -ENOMEM;
548 } 548 }
549 549
550 ret = plgpio_probe_dt(pdev, plgpio); 550 ret = plgpio_probe_dt(pdev, plgpio);
551 if (ret) { 551 if (ret) {
552 dev_err(&pdev->dev, "DT probe failed\n"); 552 dev_err(&pdev->dev, "DT probe failed\n");
553 return ret; 553 return ret;
554 } 554 }
555 555
556 plgpio->clk = devm_clk_get(&pdev->dev, NULL); 556 plgpio->clk = devm_clk_get(&pdev->dev, NULL);
557 if (IS_ERR(plgpio->clk)) 557 if (IS_ERR(plgpio->clk))
558 dev_warn(&pdev->dev, "clk_get() failed, work without it\n"); 558 dev_warn(&pdev->dev, "clk_get() failed, work without it\n");
559 559
560 #ifdef CONFIG_PM 560 #ifdef CONFIG_PM
561 plgpio->csave_regs = devm_kzalloc(&pdev->dev, 561 plgpio->csave_regs = devm_kzalloc(&pdev->dev,
562 sizeof(*plgpio->csave_regs) * 562 sizeof(*plgpio->csave_regs) *
563 DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG), 563 DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG),
564 GFP_KERNEL); 564 GFP_KERNEL);
565 if (!plgpio->csave_regs) { 565 if (!plgpio->csave_regs) {
566 dev_err(&pdev->dev, "csave registers memory allocation fail\n"); 566 dev_err(&pdev->dev, "csave registers memory allocation fail\n");
567 return -ENOMEM; 567 return -ENOMEM;
568 } 568 }
569 #endif 569 #endif
570 570
571 platform_set_drvdata(pdev, plgpio); 571 platform_set_drvdata(pdev, plgpio);
572 spin_lock_init(&plgpio->lock); 572 spin_lock_init(&plgpio->lock);
573 573
574 plgpio->irq_base = -1; 574 plgpio->irq_base = -1;
575 plgpio->chip.base = -1; 575 plgpio->chip.base = -1;
576 plgpio->chip.request = plgpio_request; 576 plgpio->chip.request = plgpio_request;
577 plgpio->chip.free = plgpio_free; 577 plgpio->chip.free = plgpio_free;
578 plgpio->chip.direction_input = plgpio_direction_input; 578 plgpio->chip.direction_input = plgpio_direction_input;
579 plgpio->chip.direction_output = plgpio_direction_output; 579 plgpio->chip.direction_output = plgpio_direction_output;
580 plgpio->chip.get = plgpio_get_value; 580 plgpio->chip.get = plgpio_get_value;
581 plgpio->chip.set = plgpio_set_value; 581 plgpio->chip.set = plgpio_set_value;
582 plgpio->chip.to_irq = plgpio_to_irq; 582 plgpio->chip.to_irq = plgpio_to_irq;
583 plgpio->chip.label = dev_name(&pdev->dev); 583 plgpio->chip.label = dev_name(&pdev->dev);
584 plgpio->chip.dev = &pdev->dev; 584 plgpio->chip.dev = &pdev->dev;
585 plgpio->chip.owner = THIS_MODULE; 585 plgpio->chip.owner = THIS_MODULE;
586 586
587 if (!IS_ERR(plgpio->clk)) { 587 if (!IS_ERR(plgpio->clk)) {
588 ret = clk_prepare(plgpio->clk); 588 ret = clk_prepare(plgpio->clk);
589 if (ret) { 589 if (ret) {
590 dev_err(&pdev->dev, "clk prepare failed\n"); 590 dev_err(&pdev->dev, "clk prepare failed\n");
591 return ret; 591 return ret;
592 } 592 }
593 } 593 }
594 594
595 ret = gpiochip_add(&plgpio->chip); 595 ret = gpiochip_add(&plgpio->chip);
596 if (ret) { 596 if (ret) {
597 dev_err(&pdev->dev, "unable to add gpio chip\n"); 597 dev_err(&pdev->dev, "unable to add gpio chip\n");
598 goto unprepare_clk; 598 goto unprepare_clk;
599 } 599 }
600 600
601 irq = platform_get_irq(pdev, 0); 601 irq = platform_get_irq(pdev, 0);
602 if (irq < 0) { 602 if (irq < 0) {
603 dev_info(&pdev->dev, "irqs not supported\n"); 603 dev_info(&pdev->dev, "irqs not supported\n");
604 return 0; 604 return 0;
605 } 605 }
606 606
607 plgpio->irq_base = irq_alloc_descs(-1, 0, plgpio->chip.ngpio, 0); 607 plgpio->irq_base = irq_alloc_descs(-1, 0, plgpio->chip.ngpio, 0);
608 if (IS_ERR_VALUE(plgpio->irq_base)) { 608 if (IS_ERR_VALUE(plgpio->irq_base)) {
609 /* we would not support irq for gpio */ 609 /* we would not support irq for gpio */
610 dev_warn(&pdev->dev, "couldn't allocate irq base\n"); 610 dev_warn(&pdev->dev, "couldn't allocate irq base\n");
611 return 0; 611 return 0;
612 } 612 }
613 613
614 plgpio->irq_domain = irq_domain_add_legacy(np, plgpio->chip.ngpio, 614 plgpio->irq_domain = irq_domain_add_legacy(np, plgpio->chip.ngpio,
615 plgpio->irq_base, 0, &irq_domain_simple_ops, NULL); 615 plgpio->irq_base, 0, &irq_domain_simple_ops, NULL);
616 if (WARN_ON(!plgpio->irq_domain)) { 616 if (WARN_ON(!plgpio->irq_domain)) {
617 dev_err(&pdev->dev, "irq domain init failed\n"); 617 dev_err(&pdev->dev, "irq domain init failed\n");
618 irq_free_descs(plgpio->irq_base, plgpio->chip.ngpio); 618 irq_free_descs(plgpio->irq_base, plgpio->chip.ngpio);
619 ret = -ENXIO; 619 ret = -ENXIO;
620 goto remove_gpiochip; 620 goto remove_gpiochip;
621 } 621 }
622 622
623 irq_set_chained_handler(irq, plgpio_irq_handler); 623 irq_set_chained_handler(irq, plgpio_irq_handler);
624 for (i = 0; i < plgpio->chip.ngpio; i++) { 624 for (i = 0; i < plgpio->chip.ngpio; i++) {
625 irq_set_chip_and_handler(i + plgpio->irq_base, &plgpio_irqchip, 625 irq_set_chip_and_handler(i + plgpio->irq_base, &plgpio_irqchip,
626 handle_simple_irq); 626 handle_simple_irq);
627 set_irq_flags(i + plgpio->irq_base, IRQF_VALID); 627 set_irq_flags(i + plgpio->irq_base, IRQF_VALID);
628 irq_set_chip_data(i + plgpio->irq_base, plgpio); 628 irq_set_chip_data(i + plgpio->irq_base, plgpio);
629 } 629 }
630 630
631 irq_set_handler_data(irq, plgpio); 631 irq_set_handler_data(irq, plgpio);
632 dev_info(&pdev->dev, "PLGPIO registered with IRQs\n"); 632 dev_info(&pdev->dev, "PLGPIO registered with IRQs\n");
633 633
634 return 0; 634 return 0;
635 635
636 remove_gpiochip: 636 remove_gpiochip:
637 dev_info(&pdev->dev, "Remove gpiochip\n"); 637 dev_info(&pdev->dev, "Remove gpiochip\n");
638 if (gpiochip_remove(&plgpio->chip)) 638 if (gpiochip_remove(&plgpio->chip))
639 dev_err(&pdev->dev, "unable to remove gpiochip\n"); 639 dev_err(&pdev->dev, "unable to remove gpiochip\n");
640 unprepare_clk: 640 unprepare_clk:
641 if (!IS_ERR(plgpio->clk)) 641 if (!IS_ERR(plgpio->clk))
642 clk_unprepare(plgpio->clk); 642 clk_unprepare(plgpio->clk);
643 643
644 return ret; 644 return ret;
645 } 645 }
646 646
647 #ifdef CONFIG_PM 647 #ifdef CONFIG_PM
648 static int plgpio_suspend(struct device *dev) 648 static int plgpio_suspend(struct device *dev)
649 { 649 {
650 struct plgpio *plgpio = dev_get_drvdata(dev); 650 struct plgpio *plgpio = dev_get_drvdata(dev);
651 int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG); 651 int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
652 void __iomem *off; 652 void __iomem *off;
653 653
654 for (i = 0; i < reg_count; i++) { 654 for (i = 0; i < reg_count; i++) {
655 off = plgpio->base + i * sizeof(int *); 655 off = plgpio->base + i * sizeof(int *);
656 656
657 if (plgpio->regs.enb != -1) 657 if (plgpio->regs.enb != -1)
658 plgpio->csave_regs[i].enb = 658 plgpio->csave_regs[i].enb =
659 readl_relaxed(plgpio->regs.enb + off); 659 readl_relaxed(plgpio->regs.enb + off);
660 if (plgpio->regs.eit != -1) 660 if (plgpio->regs.eit != -1)
661 plgpio->csave_regs[i].eit = 661 plgpio->csave_regs[i].eit =
662 readl_relaxed(plgpio->regs.eit + off); 662 readl_relaxed(plgpio->regs.eit + off);
663 plgpio->csave_regs[i].wdata = readl_relaxed(plgpio->regs.wdata + 663 plgpio->csave_regs[i].wdata = readl_relaxed(plgpio->regs.wdata +
664 off); 664 off);
665 plgpio->csave_regs[i].dir = readl_relaxed(plgpio->regs.dir + 665 plgpio->csave_regs[i].dir = readl_relaxed(plgpio->regs.dir +
666 off); 666 off);
667 plgpio->csave_regs[i].ie = readl_relaxed(plgpio->regs.ie + off); 667 plgpio->csave_regs[i].ie = readl_relaxed(plgpio->regs.ie + off);
668 } 668 }
669 669
670 return 0; 670 return 0;
671 } 671 }
672 672
673 /* 673 /*
674 * This is used to correct the values in end registers. End registers contain 674 * This is used to correct the values in end registers. End registers contain
675 * extra bits that might be used for other purpose in platform. So, we shouldn't 675 * extra bits that might be used for other purpose in platform. So, we shouldn't
676 * overwrite these bits. This macro, reads given register again, preserves other 676 * overwrite these bits. This macro, reads given register again, preserves other
677 * bit values (non-plgpio bits), and retain captured value (plgpio bits). 677 * bit values (non-plgpio bits), and retain captured value (plgpio bits).
678 */ 678 */
679 #define plgpio_prepare_reg(__reg, _off, _mask, _tmp) \ 679 #define plgpio_prepare_reg(__reg, _off, _mask, _tmp) \
680 { \ 680 { \
681 _tmp = readl_relaxed(plgpio->regs.__reg + _off); \ 681 _tmp = readl_relaxed(plgpio->regs.__reg + _off); \
682 _tmp &= ~_mask; \ 682 _tmp &= ~_mask; \
683 plgpio->csave_regs[i].__reg = \ 683 plgpio->csave_regs[i].__reg = \
684 _tmp | (plgpio->csave_regs[i].__reg & _mask); \ 684 _tmp | (plgpio->csave_regs[i].__reg & _mask); \
685 } 685 }
686 686
687 static int plgpio_resume(struct device *dev) 687 static int plgpio_resume(struct device *dev)
688 { 688 {
689 struct plgpio *plgpio = dev_get_drvdata(dev); 689 struct plgpio *plgpio = dev_get_drvdata(dev);
690 int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG); 690 int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
691 void __iomem *off; 691 void __iomem *off;
692 u32 mask, tmp; 692 u32 mask, tmp;
693 693
694 for (i = 0; i < reg_count; i++) { 694 for (i = 0; i < reg_count; i++) {
695 off = plgpio->base + i * sizeof(int *); 695 off = plgpio->base + i * sizeof(int *);
696 696
697 if (i == reg_count - 1) { 697 if (i == reg_count - 1) {
698 mask = (1 << (plgpio->chip.ngpio - i * 698 mask = (1 << (plgpio->chip.ngpio - i *
699 MAX_GPIO_PER_REG)) - 1; 699 MAX_GPIO_PER_REG)) - 1;
700 700
701 if (plgpio->regs.enb != -1) 701 if (plgpio->regs.enb != -1)
702 plgpio_prepare_reg(enb, off, mask, tmp); 702 plgpio_prepare_reg(enb, off, mask, tmp);
703 703
704 if (plgpio->regs.eit != -1) 704 if (plgpio->regs.eit != -1)
705 plgpio_prepare_reg(eit, off, mask, tmp); 705 plgpio_prepare_reg(eit, off, mask, tmp);
706 706
707 plgpio_prepare_reg(wdata, off, mask, tmp); 707 plgpio_prepare_reg(wdata, off, mask, tmp);
708 plgpio_prepare_reg(dir, off, mask, tmp); 708 plgpio_prepare_reg(dir, off, mask, tmp);
709 plgpio_prepare_reg(ie, off, mask, tmp); 709 plgpio_prepare_reg(ie, off, mask, tmp);
710 } 710 }
711 711
712 writel_relaxed(plgpio->csave_regs[i].wdata, plgpio->regs.wdata + 712 writel_relaxed(plgpio->csave_regs[i].wdata, plgpio->regs.wdata +
713 off); 713 off);
714 writel_relaxed(plgpio->csave_regs[i].dir, plgpio->regs.dir + 714 writel_relaxed(plgpio->csave_regs[i].dir, plgpio->regs.dir +
715 off); 715 off);
716 716
717 if (plgpio->regs.eit != -1) 717 if (plgpio->regs.eit != -1)
718 writel_relaxed(plgpio->csave_regs[i].eit, 718 writel_relaxed(plgpio->csave_regs[i].eit,
719 plgpio->regs.eit + off); 719 plgpio->regs.eit + off);
720 720
721 writel_relaxed(plgpio->csave_regs[i].ie, plgpio->regs.ie + off); 721 writel_relaxed(plgpio->csave_regs[i].ie, plgpio->regs.ie + off);
722 722
723 if (plgpio->regs.enb != -1) 723 if (plgpio->regs.enb != -1)
724 writel_relaxed(plgpio->csave_regs[i].enb, 724 writel_relaxed(plgpio->csave_regs[i].enb,
725 plgpio->regs.enb + off); 725 plgpio->regs.enb + off);
726 } 726 }
727 727
728 return 0; 728 return 0;
729 } 729 }
730 #endif 730 #endif
731 731
732 static SIMPLE_DEV_PM_OPS(plgpio_dev_pm_ops, plgpio_suspend, plgpio_resume); 732 static SIMPLE_DEV_PM_OPS(plgpio_dev_pm_ops, plgpio_suspend, plgpio_resume);
733 733
734 static const struct of_device_id plgpio_of_match[] = { 734 static const struct of_device_id plgpio_of_match[] = {
735 { .compatible = "st,spear-plgpio" }, 735 { .compatible = "st,spear-plgpio" },
736 {} 736 {}
737 }; 737 };
738 MODULE_DEVICE_TABLE(of, plgpio_of_match); 738 MODULE_DEVICE_TABLE(of, plgpio_of_match);
739 739
740 static struct platform_driver plgpio_driver = { 740 static struct platform_driver plgpio_driver = {
741 .probe = plgpio_probe, 741 .probe = plgpio_probe,
742 .driver = { 742 .driver = {
743 .owner = THIS_MODULE, 743 .owner = THIS_MODULE,
744 .name = "spear-plgpio", 744 .name = "spear-plgpio",
745 .pm = &plgpio_dev_pm_ops, 745 .pm = &plgpio_dev_pm_ops,
746 .of_match_table = of_match_ptr(plgpio_of_match), 746 .of_match_table = of_match_ptr(plgpio_of_match),
747 }, 747 },
748 }; 748 };
749 749
750 static int __init plgpio_init(void) 750 static int __init plgpio_init(void)
751 { 751 {
752 return platform_driver_register(&plgpio_driver); 752 return platform_driver_register(&plgpio_driver);
753 } 753 }
754 subsys_initcall(plgpio_init); 754 subsys_initcall(plgpio_init);
755 755
756 MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>"); 756 MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
757 MODULE_DESCRIPTION("ST Microlectronics SPEAr PLGPIO driver"); 757 MODULE_DESCRIPTION("ST Microlectronics SPEAr PLGPIO driver");
758 MODULE_LICENSE("GPL"); 758 MODULE_LICENSE("GPL");
759 759