ixgbe: consolidate packet buffer allocation

Consolidate packet buffer allocation currently being done in the DCB path and main path. This allows the feature set and packet buffer requirements to be done once. This is prep work to allow DCB to coexist with other features namely, flow director. CC: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: John Fastabend <john.r.fastabend@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

ixgbe: consolidate packet buffer allocation
Consolidate packet buffer allocation currently being done in the DCB path and main path. This allows the feature set and packet buffer requirements to be done once. This is prep work to allow DCB to coexist with other features namely, flow director. CC: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: John Fastabend <john.r.fastabend@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
John Fastabend · Jeff Kirsher
1 parent 1fcd86b511
Showing 13 changed files with 160 additions and 170 deletions Side-by-side Diff
drivers/net/ixgbe/ixgbe_82598.c
drivers/net/ixgbe/ixgbe_82599.c
drivers/net/ixgbe/ixgbe_common.c
drivers/net/ixgbe/ixgbe_common.h
drivers/net/ixgbe/ixgbe_dcb.c
drivers/net/ixgbe/ixgbe_dcb.h
drivers/net/ixgbe/ixgbe_dcb_82598.c
drivers/net/ixgbe/ixgbe_dcb_82598.h
drivers/net/ixgbe/ixgbe_dcb_82599.c
drivers/net/ixgbe/ixgbe_dcb_82599.h
drivers/net/ixgbe/ixgbe_main.c
drivers/net/ixgbe/ixgbe_type.h
drivers/net/ixgbe/ixgbe_x540.c
@@ -1242,6 +1242,47 @@
 	}
 }
  
+/**
+ * ixgbe_set_rxpba_82598 - Configure packet buffers
+ * @hw: pointer to hardware structure
+ * @dcb_config: pointer to ixgbe_dcb_config structure
+ *
+ * Configure packet buffers.
+ */
+static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, u32 headroom,
+				  int strategy)
+{
+	u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
+	u8  i = 0;
+
+	if (!num_pb)
+		return;
+
+	/* Setup Rx packet buffer sizes */
+	switch (strategy) {
+	case PBA_STRATEGY_WEIGHTED:
+		/* Setup the first four at 80KB */
+		rxpktsize = IXGBE_RXPBSIZE_80KB;
+		for (; i < 4; i++)
+			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
+		/* Setup the last four at 48KB...don't re-init i */
+		rxpktsize = IXGBE_RXPBSIZE_48KB;
+		/* Fall Through */
+	case PBA_STRATEGY_EQUAL:
+	default:
+		/* Divide the remaining Rx packet buffer evenly among the TCs */
+		for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
+			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
+		break;
+	}
+
+	/* Setup Tx packet buffer sizes */
+	for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
+		IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
+
+	return;
+}
+
 static struct ixgbe_mac_operations mac_ops_82598 = {
 	.init_hw		= &ixgbe_init_hw_generic,
 	.reset_hw		= &ixgbe_reset_hw_82598,
@@ -1257,6 +1298,7 @@
 	.read_analog_reg8	= &ixgbe_read_analog_reg8_82598,
 	.write_analog_reg8	= &ixgbe_write_analog_reg8_82598,
 	.setup_link		= &ixgbe_setup_mac_link_82598,
+	.set_rxpba		= &ixgbe_set_rxpba_82598,
 	.check_link		= &ixgbe_check_mac_link_82598,
 	.get_link_capabilities	= &ixgbe_get_link_capabilities_82598,
 	.led_on			= &ixgbe_led_on_generic,
@@ -1114,27 +1114,8 @@
 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
 {
 	u32 fdirctrl = 0;
-	u32 pbsize;
 	int i;
  
-	/*
-	 * Before enabling Flow Director, the Rx Packet Buffer size
-	 * must be reduced.  The new value is the current size minus
-	 * flow director memory usage size.
-	 */
-	pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
-	IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
-	    (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
-
-	/*
-	 * The defaults in the HW for RX PB 1-7 are not zero and so should be
-	 * initialized to zero for non DCB mode otherwise actual total RX PB
-	 * would be bigger than programmed and filter space would run into
-	 * the PB 0 region.
-	 */
-	for (i = 1; i < 8; i++)
-		IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
-
 	/* Send interrupt when 64 filters are left */
 	fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
  
  
@@ -1202,27 +1183,8 @@
 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
 {
 	u32 fdirctrl = 0;
-	u32 pbsize;
 	int i;
  
-	/*
-	 * Before enabling Flow Director, the Rx Packet Buffer size
-	 * must be reduced.  The new value is the current size minus
-	 * flow director memory usage size.
-	 */
-	pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
-	IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
-	    (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
-
-	/*
-	 * The defaults in the HW for RX PB 1-7 are not zero and so should be
-	 * initialized to zero for non DCB mode otherwise actual total RX PB
-	 * would be bigger than programmed and filter space would run into
-	 * the PB 0 region.
-	 */
-	for (i = 1; i < 8; i++)
-		IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
-
 	/* Send interrupt when 64 filters are left */
 	fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
  
@@ -2146,6 +2108,7 @@
 	.read_analog_reg8       = &ixgbe_read_analog_reg8_82599,
 	.write_analog_reg8      = &ixgbe_write_analog_reg8_82599,
 	.setup_link             = &ixgbe_setup_mac_link_82599,
+	.set_rxpba		= &ixgbe_set_rxpba_generic,
 	.check_link             = &ixgbe_check_mac_link_generic,
 	.get_link_capabilities  = &ixgbe_get_link_capabilities_82599,
 	.led_on                 = &ixgbe_led_on_generic,
@@ -3267,4 +3267,70 @@
  
 	return 0;
 }
+
+/**
+ * ixgbe_set_rxpba_generic - Initialize RX packet buffer
+ * @hw: pointer to hardware structure
+ * @num_pb: number of packet buffers to allocate
+ * @headroom: reserve n KB of headroom
+ * @strategy: packet buffer allocation strategy
+ **/
+void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
+			     int num_pb,
+			     u32 headroom,
+			     int strategy)
+{
+	u32 pbsize = hw->mac.rx_pb_size;
+	int i = 0;
+	u32 rxpktsize, txpktsize, txpbthresh;
+
+	/* Reserve headroom */
+	pbsize -= headroom;
+
+	if (!num_pb)
+		num_pb = 1;
+
+	/* Divide remaining packet buffer space amongst the number
+	 * of packet buffers requested using supplied strategy.
+	 */
+	switch (strategy) {
+	case (PBA_STRATEGY_WEIGHTED):
+		/* pba_80_48 strategy weight first half of packet buffer with
+		 * 5/8 of the packet buffer space.
+		 */
+		rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
+		pbsize -= rxpktsize * (num_pb / 2);
+		rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
+		for (; i < (num_pb / 2); i++)
+			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
+		/* Fall through to configure remaining packet buffers */
+	case (PBA_STRATEGY_EQUAL):
+		/* Divide the remaining Rx packet buffer evenly among the TCs */
+		rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
+		for (; i < num_pb; i++)
+			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
+		break;
+	default:
+		break;
+	}
+
+	/*
+	 * Setup Tx packet buffer and threshold equally for all TCs
+	 * TXPBTHRESH register is set in K so divide by 1024 and subtract
+	 * 10 since the largest packet we support is just over 9K.
+	 */
+	txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
+	txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
+	for (i = 0; i < num_pb; i++) {
+		IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
+		IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
+	}
+
+	/* Clear unused TCs, if any, to zero buffer size*/
+	for (; i < IXGBE_MAX_PB; i++) {
+		IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
+		IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
+		IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
+	}
+}
@@ -100,6 +100,9 @@
 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps);
  
+void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb,
+			     u32 headroom, int strategy);
+
 #define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
  
 #ifndef writeq
@@ -258,15 +258,13 @@
  
 	switch (hw->mac.type) {
 	case ixgbe_mac_82598EB:
-		ret = ixgbe_dcb_hw_config_82598(hw, dcb_config->rx_pba_cfg,
-						pfc_en, refill, max, bwgid,
-						ptype);
+		ret = ixgbe_dcb_hw_config_82598(hw, pfc_en, refill, max,
+						bwgid, ptype);
 		break;
 	case ixgbe_mac_82599EB:
 	case ixgbe_mac_X540:
-		ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->rx_pba_cfg,
-						pfc_en, refill, max, bwgid,
-						ptype, prio_tc);
+		ret = ixgbe_dcb_hw_config_82599(hw, pfc_en, refill, max,
+						bwgid, ptype, prio_tc);
 		break;
 	default:
 		break;
@@ -123,11 +123,6 @@
 	u8 tc; /* Traffic class (TC) */
 };
  
-enum dcb_rx_pba_cfg {
-	pba_equal,     /* PBA[0-7] each use 64KB FIFO */
-	pba_80_48      /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */
-};
-
 struct dcb_num_tcs {
 	u8 pg_tcs;
 	u8 pfc_tcs;
@@ -139,8 +134,6 @@
 	struct tc_configuration tc_config[MAX_TRAFFIC_CLASS];
 	u8     bw_percentage[2][MAX_BW_GROUP]; /* One each for Tx/Rx */
 	bool   pfc_mode_enable;
-
-	enum dcb_rx_pba_cfg rx_pba_cfg;
  
 	u32  dcb_cfg_version; /* Not used...OS-specific? */
 	u32  link_speed; /* For bandwidth allocation validation purpose */
@@ -32,45 +32,6 @@
 #include "ixgbe_dcb_82598.h"
  
 /**
- * ixgbe_dcb_config_packet_buffers_82598 - Configure packet buffers
- * @hw: pointer to hardware structure
- * @dcb_config: pointer to ixgbe_dcb_config structure
- *
- * Configure packet buffers for DCB mode.
- */
-static s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw, u8 rx_pba)
-{
-	s32 ret_val = 0;
-	u32 value = IXGBE_RXPBSIZE_64KB;
-	u8  i = 0;
-
-	/* Setup Rx packet buffer sizes */
-	switch (rx_pba) {
-	case pba_80_48:
-		/* Setup the first four at 80KB */
-		value = IXGBE_RXPBSIZE_80KB;
-		for (; i < 4; i++)
-			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);
-		/* Setup the last four at 48KB...don't re-init i */
-		value = IXGBE_RXPBSIZE_48KB;
-		/* Fall Through */
-	case pba_equal:
-	default:
-		for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
-			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);
-
-		/* Setup Tx packet buffer sizes */
-		for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
-			IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i),
-					IXGBE_TXPBSIZE_40KB);
-		}
-		break;
-	}
-
-	return ret_val;
-}
-
-/**
  * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
  * @hw: pointer to hardware structure
  * @dcb_config: pointer to ixgbe_dcb_config structure
  
@@ -321,11 +282,9 @@
  *
  * Configure dcb settings and enable dcb mode.
  */
-s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw,
-			      u8 rx_pba, u8 pfc_en, u16 *refill,
+s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
 			      u16 *max, u8 *bwg_id, u8 *prio_type)
 {
-	ixgbe_dcb_config_packet_buffers_82598(hw, rx_pba);
 	ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, prio_type);
 	ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
 					       bwg_id, prio_type);
@@ -91,8 +91,7 @@
 						u8 *bwg_id,
 						u8 *prio_type);
  
-s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw,
-			      u8 rx_pba, u8 pfc_en, u16 *refill,
+s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
 			      u16 *max, u8 *bwg_id, u8 *prio_type);
  
 #endif /* _DCB_82598_CONFIG_H */
@@ -31,63 +31,6 @@
 #include "ixgbe_dcb_82599.h"
  
 /**
- * ixgbe_dcb_config_packet_buffers_82599 - Configure DCB packet buffers
- * @hw: pointer to hardware structure
- * @rx_pba: method to distribute packet buffer
- *
- * Configure packet buffers for DCB mode.
- */
-static s32 ixgbe_dcb_config_packet_buffers_82599(struct ixgbe_hw *hw, u8 rx_pba)
-{
-	int num_tcs = IXGBE_MAX_PACKET_BUFFERS;
-	u32 rx_pb_size = hw->mac.rx_pb_size << IXGBE_RXPBSIZE_SHIFT;
-	u32 rxpktsize;
-	u32 txpktsize;
-	u32 txpbthresh;
-	u8  i = 0;
-
-	/*
-	 * This really means configure the first half of the TCs
-	 * (Traffic Classes) to use 5/8 of the Rx packet buffer
-	 * space.  To determine the size of the buffer for each TC,
-	 * we are multiplying the average size by 5/4 and applying
-	 * it to half of the traffic classes.
-	 */
-	if (rx_pba == pba_80_48) {
-		rxpktsize = (rx_pb_size * 5) / (num_tcs * 4);
-		rx_pb_size -= rxpktsize * (num_tcs / 2);
-		for (; i < (num_tcs / 2); i++)
-			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
-	}
-
-	/* Divide the remaining Rx packet buffer evenly among the TCs */
-	rxpktsize = rx_pb_size / (num_tcs - i);
-	for (; i < num_tcs; i++)
-		IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
-
-	/*
-	 * Setup Tx packet buffer and threshold equally for all TCs
-	 * TXPBTHRESH register is set in K so divide by 1024 and subtract
-	 * 10 since the largest packet we support is just over 9K.
-	 */
-	txpktsize = IXGBE_TXPBSIZE_MAX / num_tcs;
-	txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
-	for (i = 0; i < num_tcs; i++) {
-		IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
-		IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
-	}
-
-	/* Clear unused TCs, if any, to zero buffer size*/
-	for (; i < MAX_TRAFFIC_CLASS; i++) {
-		IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
-		IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
-		IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
-	}
-
-	return 0;
-}
-
-/**
  * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
  * @hw: pointer to hardware structure
  * @refill: refill credits index by traffic class
@@ -434,7 +377,6 @@
 /**
  * ixgbe_dcb_hw_config_82599 - Configure and enable DCB
  * @hw: pointer to hardware structure
- * @rx_pba: method to distribute packet buffer
  * @refill: refill credits index by traffic class
  * @max: max credits index by traffic class
  * @bwg_id: bandwidth grouping indexed by traffic class
  
@@ -443,11 +385,9 @@
  *
  * Configure dcb settings and enable dcb mode.
  */
-s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw,
-			      u8 rx_pba, u8 pfc_en, u16 *refill,
+s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
 			      u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc)
 {
-	ixgbe_dcb_config_packet_buffers_82599(hw, rx_pba);
 	ixgbe_dcb_config_82599(hw);
 	ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
 					  prio_type, prio_tc);
@@ -86,17 +86,6 @@
 #define IXGBE_RTTPCS_ARBD_SHIFT 22
 #define IXGBE_RTTPCS_ARBD_DCB   0x4        /* Arbitration delay in DCB mode */
  
-#define IXGBE_TXPBSIZE_20KB     0x00005000 /* 20KB Packet Buffer */
-#define IXGBE_TXPBSIZE_40KB     0x0000A000 /* 40KB Packet Buffer */
-#define IXGBE_RXPBSIZE_48KB     0x0000C000 /* 48KB Packet Buffer */
-#define IXGBE_RXPBSIZE_64KB     0x00010000 /* 64KB Packet Buffer */
-#define IXGBE_RXPBSIZE_80KB     0x00014000 /* 80KB Packet Buffer */
-#define IXGBE_RXPBSIZE_128KB    0x00020000 /* 128KB Packet Buffer */
-#define IXGBE_TXPBSIZE_MAX	0x00028000 /* 160KB Packet Buffer*/
-
-#define IXGBE_TXPBTHRESH_DCB    0xA        /* THRESH value for DCB mode */
-#define IXGBE_TXPKT_SIZE_MAX    0xA        /* Max Tx Packet size  */
-
 /* SECTXMINIFG DCB */
 #define IXGBE_SECTX_DCB		0x00001F00 /* DCB TX Buffer IFG */
  
@@ -127,8 +116,7 @@
 						u8 *prio_type,
 						u8 *prio_tc);
  
-s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw,
-			      u8 rx_pba, u8 pfc_en, u16 *refill,
+s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
 			      u16 *max, u8 *bwg_id, u8 *prio_type,
 			      u8 *prio_tc);
  
@@ -3780,12 +3780,27 @@
 }
  
 #endif
+
+static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
+{
+	int hdrm = 0;
+	int num_tc = netdev_get_num_tc(adapter->netdev);
+	struct ixgbe_hw *hw = &adapter->hw;
+
+	if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
+	    adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
+		hdrm = 64 << adapter->fdir_pballoc;
+
+	hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
+}
+
 static void ixgbe_configure(struct ixgbe_adapter *adapter)
 {
 	struct net_device *netdev = adapter->netdev;
 	struct ixgbe_hw *hw = &adapter->hw;
 	int i;
  
+	ixgbe_configure_pb(adapter);
 #ifdef CONFIG_IXGBE_DCB
 	ixgbe_configure_dcb(adapter);
 #endif
@@ -5251,7 +5266,6 @@
 	}
 	adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
 	adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
-	adapter->dcb_cfg.rx_pba_cfg = pba_equal;
 	adapter->dcb_cfg.pfc_mode_enable = false;
 	adapter->dcb_set_bitmap = 0x00;
 	adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
@@ -1118,6 +1118,27 @@
 #define IXGBE_GPIE_VTMODE_32     0x00008000 /* 32 VFs 4 queues per VF */
 #define IXGBE_GPIE_VTMODE_64     0x0000C000 /* 64 VFs 2 queues per VF */
  
+/* Packet Buffer Initialization */
+#define IXGBE_TXPBSIZE_20KB     0x00005000 /* 20KB Packet Buffer */
+#define IXGBE_TXPBSIZE_40KB     0x0000A000 /* 40KB Packet Buffer */
+#define IXGBE_RXPBSIZE_48KB     0x0000C000 /* 48KB Packet Buffer */
+#define IXGBE_RXPBSIZE_64KB     0x00010000 /* 64KB Packet Buffer */
+#define IXGBE_RXPBSIZE_80KB     0x00014000 /* 80KB Packet Buffer */
+#define IXGBE_RXPBSIZE_128KB    0x00020000 /* 128KB Packet Buffer */
+#define IXGBE_RXPBSIZE_MAX      0x00080000 /* 512KB Packet Buffer*/
+#define IXGBE_TXPBSIZE_MAX      0x00028000 /* 160KB Packet Buffer*/
+
+#define IXGBE_TXPKT_SIZE_MAX    0xA        /* Max Tx Packet size  */
+#define IXGBE_MAX_PB		8
+
+/* Packet buffer allocation strategies */
+enum {
+	PBA_STRATEGY_EQUAL	= 0,	/* Distribute PB space equally */
+#define PBA_STRATEGY_EQUAL	PBA_STRATEGY_EQUAL
+	PBA_STRATEGY_WEIGHTED	= 1,	/* Weight front half of TCs */
+#define PBA_STRATEGY_WEIGHTED	PBA_STRATEGY_WEIGHTED
+};
+
 /* Transmit Flow Control status */
 #define IXGBE_TFCS_TXOFF         0x00000001
 #define IXGBE_TFCS_TXOFF0        0x00000100
@@ -2614,6 +2635,9 @@
 	s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
 	s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
 	                             bool *);
+
+	/* Packet Buffer Manipulation */
+	void (*set_rxpba)(struct ixgbe_hw *, int, u32, int);
  
 	/* LED */
 	s32 (*led_on)(struct ixgbe_hw *, u32);
@@ -876,6 +876,7 @@
 	.read_analog_reg8       = NULL,
 	.write_analog_reg8      = NULL,
 	.setup_link             = &ixgbe_setup_mac_link_X540,
+	.set_rxpba		= &ixgbe_set_rxpba_generic,
 	.check_link             = &ixgbe_check_mac_link_generic,
 	.get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
 	.led_on                 = &ixgbe_led_on_generic,
...	...	@@ -1242,6 +1242,47 @@
1242	1242	}
1243	1243	}
1244	1244
	1245	+/**
	1246	+ * ixgbe_set_rxpba_82598 - Configure packet buffers
	1247	+ * @hw: pointer to hardware structure
	1248	+ * @dcb_config: pointer to ixgbe_dcb_config structure
	1249	+ *
	1250	+ * Configure packet buffers.
	1251	+ */
	1252	+static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, u32 headroom,
	1253	+ int strategy)
	1254	+{
	1255	+ u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
	1256	+ u8 i = 0;
	1257	+
	1258	+ if (!num_pb)
	1259	+ return;
	1260	+
	1261	+ /* Setup Rx packet buffer sizes */
	1262	+ switch (strategy) {
	1263	+ case PBA_STRATEGY_WEIGHTED:
	1264	+ /* Setup the first four at 80KB */
	1265	+ rxpktsize = IXGBE_RXPBSIZE_80KB;
	1266	+ for (; i < 4; i++)
	1267	+ IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
	1268	+ /* Setup the last four at 48KB...don't re-init i */
	1269	+ rxpktsize = IXGBE_RXPBSIZE_48KB;
	1270	+ /* Fall Through */
	1271	+ case PBA_STRATEGY_EQUAL:
	1272	+ default:
	1273	+ /* Divide the remaining Rx packet buffer evenly among the TCs */
	1274	+ for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
	1275	+ IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
	1276	+ break;
	1277	+ }
	1278	+
	1279	+ /* Setup Tx packet buffer sizes */
	1280	+ for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
	1281	+ IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
	1282	+
	1283	+ return;
	1284	+}
	1285	+
1245	1286	static struct ixgbe_mac_operations mac_ops_82598 = {
1246	1287	.init_hw = &ixgbe_init_hw_generic,
1247	1288	.reset_hw = &ixgbe_reset_hw_82598,
...	...	@@ -1257,6 +1298,7 @@
1257	1298	.read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
1258	1299	.write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
1259	1300	.setup_link = &ixgbe_setup_mac_link_82598,
	1301	+ .set_rxpba = &ixgbe_set_rxpba_82598,
1260	1302	.check_link = &ixgbe_check_mac_link_82598,
1261	1303	.get_link_capabilities = &ixgbe_get_link_capabilities_82598,
1262	1304	.led_on = &ixgbe_led_on_generic,
...	...	@@ -1114,27 +1114,8 @@
1114	1114	s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1115	1115	{
1116	1116	u32 fdirctrl = 0;
1117		- u32 pbsize;
1118	1117	int i;
1119	1118
1120		- /*
1121		- * Before enabling Flow Director, the Rx Packet Buffer size
1122		- * must be reduced. The new value is the current size minus
1123		- * flow director memory usage size.
1124		- */
1125		- pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1126		- IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1127		- (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1128		-
1129		- /*
1130		- * The defaults in the HW for RX PB 1-7 are not zero and so should be
1131		- * initialized to zero for non DCB mode otherwise actual total RX PB
1132		- * would be bigger than programmed and filter space would run into
1133		- * the PB 0 region.
1134		- */
1135		- for (i = 1; i < 8; i++)
1136		- IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1137		-
1138	1119	/* Send interrupt when 64 filters are left */
1139	1120	fdirctrl \|= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1140	1121
1141	1122
...	...	@@ -1202,27 +1183,8 @@
1202	1183	s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1203	1184	{
1204	1185	u32 fdirctrl = 0;
1205		- u32 pbsize;
1206	1186	int i;
1207	1187
1208		- /*
1209		- * Before enabling Flow Director, the Rx Packet Buffer size
1210		- * must be reduced. The new value is the current size minus
1211		- * flow director memory usage size.
1212		- */
1213		- pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1214		- IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1215		- (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1216		-
1217		- /*
1218		- * The defaults in the HW for RX PB 1-7 are not zero and so should be
1219		- * initialized to zero for non DCB mode otherwise actual total RX PB
1220		- * would be bigger than programmed and filter space would run into
1221		- * the PB 0 region.
1222		- */
1223		- for (i = 1; i < 8; i++)
1224		- IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1225		-
1226	1188	/* Send interrupt when 64 filters are left */
1227	1189	fdirctrl \|= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1228	1190
...	...	@@ -2146,6 +2108,7 @@
2146	2108	.read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2147	2109	.write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2148	2110	.setup_link = &ixgbe_setup_mac_link_82599,
	2111	+ .set_rxpba = &ixgbe_set_rxpba_generic,
2149	2112	.check_link = &ixgbe_check_mac_link_generic,
2150	2113	.get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2151	2114	.led_on = &ixgbe_led_on_generic,
...	...	@@ -3267,4 +3267,70 @@
3267	3267
3268	3268	return 0;
3269	3269	}
	3270	+
	3271	+/**
	3272	+ * ixgbe_set_rxpba_generic - Initialize RX packet buffer
	3273	+ * @hw: pointer to hardware structure
	3274	+ * @num_pb: number of packet buffers to allocate
	3275	+ * @headroom: reserve n KB of headroom
	3276	+ * @strategy: packet buffer allocation strategy
	3277	+ **/
	3278	+void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
	3279	+ int num_pb,
	3280	+ u32 headroom,
	3281	+ int strategy)
	3282	+{
	3283	+ u32 pbsize = hw->mac.rx_pb_size;
	3284	+ int i = 0;
	3285	+ u32 rxpktsize, txpktsize, txpbthresh;
	3286	+
	3287	+ /* Reserve headroom */
	3288	+ pbsize -= headroom;
	3289	+
	3290	+ if (!num_pb)
	3291	+ num_pb = 1;
	3292	+
	3293	+ /* Divide remaining packet buffer space amongst the number
	3294	+ * of packet buffers requested using supplied strategy.
	3295	+ */
	3296	+ switch (strategy) {
	3297	+ case (PBA_STRATEGY_WEIGHTED):
	3298	+ /* pba_80_48 strategy weight first half of packet buffer with
	3299	+ * 5/8 of the packet buffer space.
	3300	+ */
	3301	+ rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
	3302	+ pbsize -= rxpktsize * (num_pb / 2);
	3303	+ rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
	3304	+ for (; i < (num_pb / 2); i++)
	3305	+ IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
	3306	+ /* Fall through to configure remaining packet buffers */
	3307	+ case (PBA_STRATEGY_EQUAL):
	3308	+ /* Divide the remaining Rx packet buffer evenly among the TCs */
	3309	+ rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
	3310	+ for (; i < num_pb; i++)
	3311	+ IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
	3312	+ break;
	3313	+ default:
	3314	+ break;
	3315	+ }
	3316	+
	3317	+ /*
	3318	+ * Setup Tx packet buffer and threshold equally for all TCs
	3319	+ * TXPBTHRESH register is set in K so divide by 1024 and subtract
	3320	+ * 10 since the largest packet we support is just over 9K.
	3321	+ */
	3322	+ txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
	3323	+ txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
	3324	+ for (i = 0; i < num_pb; i++) {
	3325	+ IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
	3326	+ IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
	3327	+ }
	3328	+
	3329	+ /* Clear unused TCs, if any, to zero buffer size*/
	3330	+ for (; i < IXGBE_MAX_PB; i++) {
	3331	+ IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
	3332	+ IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
	3333	+ IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
	3334	+ }
	3335	+}
...	...	@@ -100,6 +100,9 @@
100	100	void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
101	101	s32 ixgbe_get_device_caps_generic(struct ixgbe_hw hw, u16 device_caps);
102	102
	103	+void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb,
	104	+ u32 headroom, int strategy);
	105	+
103	106	#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
104	107
105	108	#ifndef writeq
...	...	@@ -258,15 +258,13 @@
258	258
259	259	switch (hw->mac.type) {
260	260	case ixgbe_mac_82598EB:
261		- ret = ixgbe_dcb_hw_config_82598(hw, dcb_config->rx_pba_cfg,
262		- pfc_en, refill, max, bwgid,
263		- ptype);
	261	+ ret = ixgbe_dcb_hw_config_82598(hw, pfc_en, refill, max,
	262	+ bwgid, ptype);
264	263	break;
265	264	case ixgbe_mac_82599EB:
266	265	case ixgbe_mac_X540:
267		- ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->rx_pba_cfg,
268		- pfc_en, refill, max, bwgid,
269		- ptype, prio_tc);
	266	+ ret = ixgbe_dcb_hw_config_82599(hw, pfc_en, refill, max,
	267	+ bwgid, ptype, prio_tc);
270	268	break;
271	269	default:
272	270	break;
...	...	@@ -123,11 +123,6 @@
123	123	u8 tc; /* Traffic class (TC) */
124	124	};
125	125
126		-enum dcb_rx_pba_cfg {
127		- pba_equal, /* PBA[0-7] each use 64KB FIFO */
128		- pba_80_48 /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */
129		-};
130		-
131	126	struct dcb_num_tcs {
132	127	u8 pg_tcs;
133	128	u8 pfc_tcs;
...	...	@@ -139,8 +134,6 @@
139	134	struct tc_configuration tc_config[MAX_TRAFFIC_CLASS];
140	135	u8 bw_percentage[2][MAX_BW_GROUP]; /* One each for Tx/Rx */
141	136	bool pfc_mode_enable;
142		-
143		- enum dcb_rx_pba_cfg rx_pba_cfg;
144	137
145	138	u32 dcb_cfg_version; /* Not used...OS-specific? */
146	139	u32 link_speed; /* For bandwidth allocation validation purpose */
...	...	@@ -32,45 +32,6 @@
32	32	#include "ixgbe_dcb_82598.h"
33	33
34	34	/**
35		- * ixgbe_dcb_config_packet_buffers_82598 - Configure packet buffers
36		- * @hw: pointer to hardware structure
37		- * @dcb_config: pointer to ixgbe_dcb_config structure
38		- *
39		- * Configure packet buffers for DCB mode.
40		- */
41		-static s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw, u8 rx_pba)
42		-{
43		- s32 ret_val = 0;
44		- u32 value = IXGBE_RXPBSIZE_64KB;
45		- u8 i = 0;
46		-
47		- /* Setup Rx packet buffer sizes */
48		- switch (rx_pba) {
49		- case pba_80_48:
50		- /* Setup the first four at 80KB */
51		- value = IXGBE_RXPBSIZE_80KB;
52		- for (; i < 4; i++)
53		- IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);
54		- /* Setup the last four at 48KB...don't re-init i */
55		- value = IXGBE_RXPBSIZE_48KB;
56		- /* Fall Through */
57		- case pba_equal:
58		- default:
59		- for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
60		- IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);
61		-
62		- /* Setup Tx packet buffer sizes */
63		- for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
64		- IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i),
65		- IXGBE_TXPBSIZE_40KB);
66		- }
67		- break;
68		- }
69		-
70		- return ret_val;
71		-}
72		-
73		-/**
74	35	* ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
75	36	* @hw: pointer to hardware structure
76	37	* @dcb_config: pointer to ixgbe_dcb_config structure
77	38
...	...	@@ -321,11 +282,9 @@
321	282	*
322	283	* Configure dcb settings and enable dcb mode.
323	284	*/
324		-s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw,
325		- u8 rx_pba, u8 pfc_en, u16 *refill,
	285	+s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw hw, u8 pfc_en, u16 refill,
326	286	u16 max, u8 bwg_id, u8 *prio_type)
327	287	{
328		- ixgbe_dcb_config_packet_buffers_82598(hw, rx_pba);
329	288	ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, prio_type);
330	289	ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
331	290	bwg_id, prio_type);
...	...	@@ -91,8 +91,7 @@
91	91	u8 *bwg_id,
92	92	u8 *prio_type);
93	93
94		-s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw,
95		- u8 rx_pba, u8 pfc_en, u16 *refill,
	94	+s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw hw, u8 pfc_en, u16 refill,
96	95	u16 max, u8 bwg_id, u8 *prio_type);
97	96
98	97	#endif /* _DCB_82598_CONFIG_H */
...	...	@@ -31,63 +31,6 @@
31	31	#include "ixgbe_dcb_82599.h"
32	32
33	33	/**
34		- * ixgbe_dcb_config_packet_buffers_82599 - Configure DCB packet buffers
35		- * @hw: pointer to hardware structure
36		- * @rx_pba: method to distribute packet buffer
37		- *
38		- * Configure packet buffers for DCB mode.
39		- */
40		-static s32 ixgbe_dcb_config_packet_buffers_82599(struct ixgbe_hw *hw, u8 rx_pba)
41		-{
42		- int num_tcs = IXGBE_MAX_PACKET_BUFFERS;
43		- u32 rx_pb_size = hw->mac.rx_pb_size << IXGBE_RXPBSIZE_SHIFT;
44		- u32 rxpktsize;
45		- u32 txpktsize;
46		- u32 txpbthresh;
47		- u8 i = 0;
48		-
49		- /*
50		- * This really means configure the first half of the TCs
51		- * (Traffic Classes) to use 5/8 of the Rx packet buffer
52		- * space. To determine the size of the buffer for each TC,
53		- * we are multiplying the average size by 5/4 and applying
54		- * it to half of the traffic classes.
55		- */
56		- if (rx_pba == pba_80_48) {
57		- rxpktsize = (rx_pb_size * 5) / (num_tcs * 4);
58		- rx_pb_size -= rxpktsize * (num_tcs / 2);
59		- for (; i < (num_tcs / 2); i++)
60		- IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
61		- }
62		-
63		- /* Divide the remaining Rx packet buffer evenly among the TCs */
64		- rxpktsize = rx_pb_size / (num_tcs - i);
65		- for (; i < num_tcs; i++)
66		- IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
67		-
68		- /*
69		- * Setup Tx packet buffer and threshold equally for all TCs
70		- * TXPBTHRESH register is set in K so divide by 1024 and subtract
71		- * 10 since the largest packet we support is just over 9K.
72		- */
73		- txpktsize = IXGBE_TXPBSIZE_MAX / num_tcs;
74		- txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
75		- for (i = 0; i < num_tcs; i++) {
76		- IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
77		- IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
78		- }
79		-
80		- /* Clear unused TCs, if any, to zero buffer size*/
81		- for (; i < MAX_TRAFFIC_CLASS; i++) {
82		- IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
83		- IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
84		- IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
85		- }
86		-
87		- return 0;
88		-}
89		-
90		-/**
91	34	* ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
92	35	* @hw: pointer to hardware structure
93	36	* @refill: refill credits index by traffic class
...	...	@@ -434,7 +377,6 @@
434	377	/**
435	378	* ixgbe_dcb_hw_config_82599 - Configure and enable DCB
436	379	* @hw: pointer to hardware structure
437		- * @rx_pba: method to distribute packet buffer
438	380	* @refill: refill credits index by traffic class
439	381	* @max: max credits index by traffic class
440	382	* @bwg_id: bandwidth grouping indexed by traffic class
441	383
...	...	@@ -443,11 +385,9 @@
443	385	*
444	386	* Configure dcb settings and enable dcb mode.
445	387	*/
446		-s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw,
447		- u8 rx_pba, u8 pfc_en, u16 *refill,
	388	+s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw hw, u8 pfc_en, u16 refill,
448	389	u16 max, u8 bwg_id, u8 prio_type, u8 prio_tc)
449	390	{
450		- ixgbe_dcb_config_packet_buffers_82599(hw, rx_pba);
451	391	ixgbe_dcb_config_82599(hw);
452	392	ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
453	393	prio_type, prio_tc);
...	...	@@ -86,17 +86,6 @@
86	86	#define IXGBE_RTTPCS_ARBD_SHIFT 22
87	87	#define IXGBE_RTTPCS_ARBD_DCB 0x4 /* Arbitration delay in DCB mode */
88	88
89		-#define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */
90		-#define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */
91		-#define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */
92		-#define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */
93		-#define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */
94		-#define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */
95		-#define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer*/
96		-
97		-#define IXGBE_TXPBTHRESH_DCB 0xA /* THRESH value for DCB mode */
98		-#define IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
99		-
100	89	/* SECTXMINIFG DCB */
101	90	#define IXGBE_SECTX_DCB 0x00001F00 /* DCB TX Buffer IFG */
102	91
...	...	@@ -127,8 +116,7 @@
127	116	u8 *prio_type,
128	117	u8 *prio_tc);
129	118
130		-s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw,
131		- u8 rx_pba, u8 pfc_en, u16 *refill,
	119	+s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw hw, u8 pfc_en, u16 refill,
132	120	u16 max, u8 bwg_id, u8 *prio_type,
133	121	u8 *prio_tc);
134	122