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Commit 81b279d80a63628e580c71a31d30a8c3b3047ad4

Authored by Sekhar Nori
Committed by Grant Likely
1 parent ab2dde9924
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

gpio/davinci: fix enabling unbanked GPIO IRQs 

Unbanked GPIO IRQ handling code made a copy of just
the irq_chip structure for GPIO IRQ lines which caused
problems after the generic IRQ chip conversion because
there was no valid irq_chip_type structure with the
right "regs" populated. irq_gc_mask_set_bit() was
therefore accessing random addresses.

Fix it by making a copy of irq_chip_type structure
instead. This will ensure sane register offsets.

Cc: <stable@vger.kernel.org> # v3.0.x+
Reported-by: Jon Povey <Jon.Povey@racelogic.co.uk>
Tested-by: Jon Povey <Jon.Povey@racelogic.co.uk>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

Showing 1 changed file with 6 additions and 5 deletions Side-by-side Diff

drivers/gpio/gpio-davinci.c
Diff comments   View file @ 81b279d
... ... @@ -386,7 +386,7 @@
386 386 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
387 387 */
388 388 if (soc_info->gpio_unbanked) {
389   - static struct irq_chip gpio_irqchip_unbanked;
  389 + static struct irq_chip_type gpio_unbanked;
390 390  
391 391 /* pass "bank 0" GPIO IRQs to AINTC */
392 392 chips[0].chip.to_irq = gpio_to_irq_unbanked;
... ... @@ -394,9 +394,10 @@
394 394  
395 395 /* AINTC handles mask/unmask; GPIO handles triggering */
396 396 irq = bank_irq;
397   - gpio_irqchip_unbanked = *irq_get_chip(irq);
398   - gpio_irqchip_unbanked.name = "GPIO-AINTC";
399   - gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked;
  397 + gpio_unbanked = *container_of(irq_get_chip(irq),
  398 + struct irq_chip_type, chip);
  399 + gpio_unbanked.chip.name = "GPIO-AINTC";
  400 + gpio_unbanked.chip.irq_set_type = gpio_irq_type_unbanked;
400 401  
401 402 /* default trigger: both edges */
402 403 g = gpio2regs(0);
... ... @@ -405,7 +406,7 @@
405 406  
406 407 /* set the direct IRQs up to use that irqchip */
407 408 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
408   - irq_set_chip(irq, &gpio_irqchip_unbanked);
  409 + irq_set_chip(irq, &gpio_unbanked.chip);
409 410 irq_set_handler_data(irq, &chips[gpio / 32]);
410 411 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
411 412 }