[ARM] 4432/5: davinci: pin mux support

Support pin multiplexing configurations driver for TI DaVinci SoC Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com> Acked-by: Kevin Hilman <khilman@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

[ARM] 4432/5: davinci: pin mux support
Support pin multiplexing configurations driver for TI DaVinci SoC Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com> Acked-by: Kevin Hilman <khilman@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Vladimir Barinov · Russell King
1 parent 3d9edf09d4
Showing 4 changed files with 154 additions and 31 deletions Side-by-side Diff
arch/arm/mach-davinci/Makefile
arch/arm/mach-davinci/mux.c
arch/arm/mach-davinci/psc.c
include/asm-arm/arch-davinci/mux.h
@@ -5,7 +5,7 @@
  
 # Common objects
 obj-y 			:= time.o irq.o clock.o serial.o io.o id.o psc.o \
-			   gpio.o
+			   gpio.o mux.o
  
 # Board specific
 obj-$(CONFIG_MACH_DAVINCI_EVM)  += board-evm.o
+/*
+ * DaVinci pin multiplexing configurations
+ *
+ * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/io.h>
+#include <linux/spinlock.h>
+
+#include <asm/hardware.h>
+
+#include <asm/arch/mux.h>
+
+/* System control register offsets */
+#define PINMUX0         0x00
+#define PINMUX1         0x04
+
+static DEFINE_SPINLOCK(mux_lock);
+
+void davinci_mux_peripheral(unsigned int mux, unsigned int enable)
+{
+	u32 pinmux, muxreg = PINMUX0;
+
+	if (mux >= DAVINCI_MUX_LEVEL2) {
+		muxreg = PINMUX1;
+		mux -= DAVINCI_MUX_LEVEL2;
+	}
+
+	spin_lock(&mux_lock);
+	pinmux = davinci_readl(DAVINCI_SYSTEM_MODULE_BASE + muxreg);
+	if (enable)
+		pinmux |= (1 << mux);
+	else
+		pinmux &= ~(1 << mux);
+	davinci_writel(pinmux, DAVINCI_SYSTEM_MODULE_BASE + muxreg);
+	spin_unlock(&mux_lock);
+}
@@ -25,39 +25,40 @@
 #include <asm/io.h>
 #include <asm/hardware.h>
 #include <asm/arch/psc.h>
+#include <asm/arch/mux.h>
  
-#define PTCMD	     __REG(0x01C41120)
-#define PDSTAT	     __REG(0x01C41200)
-#define PDCTL1	     __REG(0x01C41304)
-#define EPCPR	     __REG(0x01C41070)
-#define PTSTAT	     __REG(0x01C41128)
+/* PSC register offsets */
+#define EPCPR		0x070
+#define PTCMD		0x120
+#define PTSTAT		0x128
+#define PDSTAT		0x200
+#define PDCTL1		0x304
+#define MDSTAT		0x800
+#define MDCTL		0xA00
  
-#define MDSTAT	     IO_ADDRESS(0x01C41800)
-#define MDCTL	     IO_ADDRESS(0x01C41A00)
+/* System control register offsets */
+#define VDD3P3V_PWDN	0x48
  
-#define PINMUX0	     __REG(0x01c40000)
-#define PINMUX1	     __REG(0x01c40004)
-#define VDD3P3V_PWDN __REG(0x01C40048)
-
 static void davinci_psc_mux(unsigned int id)
 {
 	switch (id) {
 	case DAVINCI_LPSC_ATA:
-		PINMUX0 |= (1 << 17) | (1 << 16);
+		davinci_mux_peripheral(DAVINCI_MUX_HDIREN, 1);
+		davinci_mux_peripheral(DAVINCI_MUX_ATAEN, 1);
 		break;
 	case DAVINCI_LPSC_MMC_SD:
 		/* VDD power manupulations are done in U-Boot for CPMAC
 		 * so applies to MMC as well
 		 */
 		/*Set up the pull regiter for MMC */
-		VDD3P3V_PWDN = 0x0;
-		PINMUX1 &= (~(1 << 9));
+		davinci_writel(0, DAVINCI_SYSTEM_MODULE_BASE + VDD3P3V_PWDN);
+		davinci_mux_peripheral(DAVINCI_MUX_MSTK, 0);
 		break;
 	case DAVINCI_LPSC_I2C:
-		PINMUX1 |= (1 << 7);
+		davinci_mux_peripheral(DAVINCI_MUX_I2C, 1);
 		break;
 	case DAVINCI_LPSC_McBSP:
-		PINMUX1 |= (1 << 10);
+		davinci_mux_peripheral(DAVINCI_MUX_ASP, 1);
 		break;
 	default:
 		break;
  
  
  
  
  
  
  
  
@@ -67,33 +68,59 @@
 /* Enable or disable a PSC domain */
 void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
 {
-	volatile unsigned int *mdstat = (unsigned int *)((int)MDSTAT + 4 * id);
-	volatile unsigned int *mdctl = (unsigned int *)((int)MDCTL + 4 * id);
+	u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask;
  
 	if (id < 0)
 		return;
  
+	mdctl = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id);
 	if (enable)
-		*mdctl |= 0x00000003;	/* Enable Module */
+		mdctl |= 0x00000003;	/* Enable Module */
 	else
-		*mdctl &= 0xFFFFFFF2;	/* Disable Module */
+		mdctl &= 0xFFFFFFF2;	/* Disable Module */
+	davinci_writel(mdctl, DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id);
  
-	if ((PDSTAT & 0x00000001) == 0) {
-		PDCTL1 |= 0x1;
-		PTCMD = (1 << domain);
-		while ((((EPCPR >> domain) & 1) == 0));
+	pdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDSTAT);
+	if ((pdstat & 0x00000001) == 0) {
+		pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
+		pdctl1 |= 0x1;
+		davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
  
-		PDCTL1 |= 0x100;
-		while (!(((PTSTAT >> domain) & 1) == 0));
+		ptcmd = 1 << domain;
+		davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD);
+
+		do {
+			epcpr = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
+					      EPCPR);
+		} while ((((epcpr >> domain) & 1) == 0));
+
+		pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
+		pdctl1 |= 0x100;
+		davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
+
+		do {
+			ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
+					       PTSTAT);
+		} while (!(((ptstat >> domain) & 1) == 0));
 	} else {
-		PTCMD = (1 << domain);
-		while (!(((PTSTAT >> domain) & 1) == 0));
+		ptcmd = 1 << domain;
+		davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD);
+
+		do {
+			ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
+					       PTSTAT);
+		} while (!(((ptstat >> domain) & 1) == 0));
 	}
  
 	if (enable)
-		while (!((*mdstat & 0x0000001F) == 0x3));
+		mdstat_mask = 0x3;
 	else
-		while (!((*mdstat & 0x0000001F) == 0x2));
+		mdstat_mask = 0x2;
+
+	do {
+		mdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
+				       MDSTAT + 4 * id);
+	} while (!((mdstat & 0x0000001F) == mdstat_mask));
  
 	if (enable)
 		davinci_psc_mux(id);
+/*
+ * DaVinci pin multiplexing defines
+ *
+ * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_MUX_H
+#define __ASM_ARCH_MUX_H
+
+#define DAVINCI_MUX_AEAW0	0
+#define DAVINCI_MUX_AEAW1	1
+#define DAVINCI_MUX_AEAW2	2
+#define DAVINCI_MUX_AEAW3	3
+#define DAVINCI_MUX_AEAW4	4
+#define DAVINCI_MUX_AECS4	10
+#define DAVINCI_MUX_AECS5	11
+#define DAVINCI_MUX_VLYNQWD0	12
+#define DAVINCI_MUX_VLYNQWD1	13
+#define DAVINCI_MUX_VLSCREN	14
+#define DAVINCI_MUX_VLYNQEN	15
+#define DAVINCI_MUX_HDIREN	16
+#define DAVINCI_MUX_ATAEN	17
+#define DAVINCI_MUX_RGB666	22
+#define DAVINCI_MUX_RGB888	23
+#define DAVINCI_MUX_LOEEN	24
+#define DAVINCI_MUX_LFLDEN	25
+#define DAVINCI_MUX_CWEN	26
+#define DAVINCI_MUX_CFLDEN	27
+#define DAVINCI_MUX_HPIEN	29
+#define DAVINCI_MUX_1394EN	30
+#define DAVINCI_MUX_EMACEN	31
+
+#define DAVINCI_MUX_LEVEL2	32
+#define DAVINCI_MUX_UART0	(DAVINCI_MUX_LEVEL2 + 0)
+#define DAVINCI_MUX_UART1	(DAVINCI_MUX_LEVEL2 + 1)
+#define DAVINCI_MUX_UART2	(DAVINCI_MUX_LEVEL2 + 2)
+#define DAVINCI_MUX_U2FLO	(DAVINCI_MUX_LEVEL2 + 3)
+#define DAVINCI_MUX_PWM0	(DAVINCI_MUX_LEVEL2 + 4)
+#define DAVINCI_MUX_PWM1	(DAVINCI_MUX_LEVEL2 + 5)
+#define DAVINCI_MUX_PWM2	(DAVINCI_MUX_LEVEL2 + 6)
+#define DAVINCI_MUX_I2C		(DAVINCI_MUX_LEVEL2 + 7)
+#define DAVINCI_MUX_SPI		(DAVINCI_MUX_LEVEL2 + 8)
+#define DAVINCI_MUX_MSTK	(DAVINCI_MUX_LEVEL2 + 9)
+#define DAVINCI_MUX_ASP		(DAVINCI_MUX_LEVEL2 + 10)
+#define DAVINCI_MUX_CLK0	(DAVINCI_MUX_LEVEL2 + 16)
+#define DAVINCI_MUX_CLK1	(DAVINCI_MUX_LEVEL2 + 17)
+#define DAVINCI_MUX_TIMIN	(DAVINCI_MUX_LEVEL2 + 18)
+
+extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable);
+
+#endif /* __ASM_ARCH_MUX_H */
...	...	@@ -5,7 +5,7 @@
5	5
6	6	# Common objects
7	7	obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \
8		- gpio.o
	8	+ gpio.o mux.o
9	9
10	10	# Board specific
11	11	obj-$(CONFIG_MACH_DAVINCI_EVM) += board-evm.o
	1	+/*
	2	+ * DaVinci pin multiplexing configurations
	3	+ *
	4	+ * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
	5	+ *
	6	+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
	7	+ * the terms of the GNU General Public License version 2. This program
	8	+ * is licensed "as is" without any warranty of any kind, whether express
	9	+ * or implied.
	10	+ */
	11	+#include <linux/io.h>
	12	+#include <linux/spinlock.h>
	13	+
	14	+#include <asm/hardware.h>
	15	+
	16	+#include <asm/arch/mux.h>
	17	+
	18	+/* System control register offsets */
	19	+#define PINMUX0 0x00
	20	+#define PINMUX1 0x04
	21	+
	22	+static DEFINE_SPINLOCK(mux_lock);
	23	+
	24	+void davinci_mux_peripheral(unsigned int mux, unsigned int enable)
	25	+{
	26	+ u32 pinmux, muxreg = PINMUX0;
	27	+
	28	+ if (mux >= DAVINCI_MUX_LEVEL2) {
	29	+ muxreg = PINMUX1;
	30	+ mux -= DAVINCI_MUX_LEVEL2;
	31	+ }
	32	+
	33	+ spin_lock(&mux_lock);
	34	+ pinmux = davinci_readl(DAVINCI_SYSTEM_MODULE_BASE + muxreg);
	35	+ if (enable)
	36	+ pinmux \|= (1 << mux);
	37	+ else
	38	+ pinmux &= ~(1 << mux);
	39	+ davinci_writel(pinmux, DAVINCI_SYSTEM_MODULE_BASE + muxreg);
	40	+ spin_unlock(&mux_lock);
	41	+}
...	...	@@ -25,39 +25,40 @@
25	25	#include <asm/io.h>
26	26	#include <asm/hardware.h>
27	27	#include <asm/arch/psc.h>
	28	+#include <asm/arch/mux.h>
28	29
29		-#define PTCMD __REG(0x01C41120)
30		-#define PDSTAT __REG(0x01C41200)
31		-#define PDCTL1 __REG(0x01C41304)
32		-#define EPCPR __REG(0x01C41070)
33		-#define PTSTAT __REG(0x01C41128)
	30	+/* PSC register offsets */
	31	+#define EPCPR 0x070
	32	+#define PTCMD 0x120
	33	+#define PTSTAT 0x128
	34	+#define PDSTAT 0x200
	35	+#define PDCTL1 0x304
	36	+#define MDSTAT 0x800
	37	+#define MDCTL 0xA00
34	38
35		-#define MDSTAT IO_ADDRESS(0x01C41800)
36		-#define MDCTL IO_ADDRESS(0x01C41A00)
	39	+/* System control register offsets */
	40	+#define VDD3P3V_PWDN 0x48
37	41
38		-#define PINMUX0 __REG(0x01c40000)
39		-#define PINMUX1 __REG(0x01c40004)
40		-#define VDD3P3V_PWDN __REG(0x01C40048)
41		-
42	42	static void davinci_psc_mux(unsigned int id)
43	43	{
44	44	switch (id) {
45	45	case DAVINCI_LPSC_ATA:
46		- PINMUX0 \|= (1 << 17) \| (1 << 16);
	46	+ davinci_mux_peripheral(DAVINCI_MUX_HDIREN, 1);
	47	+ davinci_mux_peripheral(DAVINCI_MUX_ATAEN, 1);
47	48	break;
48	49	case DAVINCI_LPSC_MMC_SD:
49	50	/* VDD power manupulations are done in U-Boot for CPMAC
50	51	* so applies to MMC as well
51	52	*/
52	53	/Set up the pull regiter for MMC /
53		- VDD3P3V_PWDN = 0x0;
54		- PINMUX1 &= (~(1 << 9));
	54	+ davinci_writel(0, DAVINCI_SYSTEM_MODULE_BASE + VDD3P3V_PWDN);
	55	+ davinci_mux_peripheral(DAVINCI_MUX_MSTK, 0);
55	56	break;
56	57	case DAVINCI_LPSC_I2C:
57		- PINMUX1 \|= (1 << 7);
	58	+ davinci_mux_peripheral(DAVINCI_MUX_I2C, 1);
58	59	break;
59	60	case DAVINCI_LPSC_McBSP:
60		- PINMUX1 \|= (1 << 10);
	61	+ davinci_mux_peripheral(DAVINCI_MUX_ASP, 1);
61	62	break;
62	63	default:
63	64	break;
64	65
65	66
66	67
67	68
68	69
69	70
70	71
71	72
...	...	@@ -67,33 +68,59 @@
67	68	/* Enable or disable a PSC domain */
68	69	void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
69	70	{
70		- volatile unsigned int mdstat = (unsigned int )((int)MDSTAT + 4 * id);
71		- volatile unsigned int mdctl = (unsigned int )((int)MDCTL + 4 * id);
	71	+ u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask;
72	72
73	73	if (id < 0)
74	74	return;
75	75
	76	+ mdctl = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id);
76	77	if (enable)
77		- mdctl \|= 0x00000003; / Enable Module */
	78	+ mdctl \|= 0x00000003; /* Enable Module */
78	79	else
79		- mdctl &= 0xFFFFFFF2; / Disable Module */
	80	+ mdctl &= 0xFFFFFFF2; /* Disable Module */
	81	+ davinci_writel(mdctl, DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id);
80	82
81		- if ((PDSTAT & 0x00000001) == 0) {
82		- PDCTL1 \|= 0x1;
83		- PTCMD = (1 << domain);
84		- while ((((EPCPR >> domain) & 1) == 0));
	83	+ pdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDSTAT);
	84	+ if ((pdstat & 0x00000001) == 0) {
	85	+ pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
	86	+ pdctl1 \|= 0x1;
	87	+ davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
85	88
86		- PDCTL1 \|= 0x100;
87		- while (!(((PTSTAT >> domain) & 1) == 0));
	89	+ ptcmd = 1 << domain;
	90	+ davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD);
	91	+
	92	+ do {
	93	+ epcpr = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
	94	+ EPCPR);
	95	+ } while ((((epcpr >> domain) & 1) == 0));
	96	+
	97	+ pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
	98	+ pdctl1 \|= 0x100;
	99	+ davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
	100	+
	101	+ do {
	102	+ ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
	103	+ PTSTAT);
	104	+ } while (!(((ptstat >> domain) & 1) == 0));
88	105	} else {
89		- PTCMD = (1 << domain);
90		- while (!(((PTSTAT >> domain) & 1) == 0));
	106	+ ptcmd = 1 << domain;
	107	+ davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD);
	108	+
	109	+ do {
	110	+ ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
	111	+ PTSTAT);
	112	+ } while (!(((ptstat >> domain) & 1) == 0));
91	113	}
92	114
93	115	if (enable)
94		- while (!((*mdstat & 0x0000001F) == 0x3));
	116	+ mdstat_mask = 0x3;
95	117	else
96		- while (!((*mdstat & 0x0000001F) == 0x2));
	118	+ mdstat_mask = 0x2;
	119	+
	120	+ do {
	121	+ mdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
	122	+ MDSTAT + 4 * id);
	123	+ } while (!((mdstat & 0x0000001F) == mdstat_mask));
97	124
98	125	if (enable)
99	126	davinci_psc_mux(id);
	1	+/*
	2	+ * DaVinci pin multiplexing defines
	3	+ *
	4	+ * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
	5	+ *
	6	+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
	7	+ * the terms of the GNU General Public License version 2. This program
	8	+ * is licensed "as is" without any warranty of any kind, whether express
	9	+ * or implied.
	10	+ */
	11	+#ifndef __ASM_ARCH_MUX_H
	12	+#define __ASM_ARCH_MUX_H
	13	+
	14	+#define DAVINCI_MUX_AEAW0 0
	15	+#define DAVINCI_MUX_AEAW1 1
	16	+#define DAVINCI_MUX_AEAW2 2
	17	+#define DAVINCI_MUX_AEAW3 3
	18	+#define DAVINCI_MUX_AEAW4 4
	19	+#define DAVINCI_MUX_AECS4 10
	20	+#define DAVINCI_MUX_AECS5 11
	21	+#define DAVINCI_MUX_VLYNQWD0 12
	22	+#define DAVINCI_MUX_VLYNQWD1 13
	23	+#define DAVINCI_MUX_VLSCREN 14
	24	+#define DAVINCI_MUX_VLYNQEN 15
	25	+#define DAVINCI_MUX_HDIREN 16
	26	+#define DAVINCI_MUX_ATAEN 17
	27	+#define DAVINCI_MUX_RGB666 22
	28	+#define DAVINCI_MUX_RGB888 23
	29	+#define DAVINCI_MUX_LOEEN 24
	30	+#define DAVINCI_MUX_LFLDEN 25
	31	+#define DAVINCI_MUX_CWEN 26
	32	+#define DAVINCI_MUX_CFLDEN 27
	33	+#define DAVINCI_MUX_HPIEN 29
	34	+#define DAVINCI_MUX_1394EN 30
	35	+#define DAVINCI_MUX_EMACEN 31
	36	+
	37	+#define DAVINCI_MUX_LEVEL2 32
	38	+#define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0)
	39	+#define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1)
	40	+#define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2)
	41	+#define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3)
	42	+#define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4)
	43	+#define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5)
	44	+#define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6)
	45	+#define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7)
	46	+#define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8)
	47	+#define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9)
	48	+#define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10)
	49	+#define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16)
	50	+#define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17)
	51	+#define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18)
	52	+
	53	+extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable);
	54	+
	55	+#endif /* __ASM_ARCH_MUX_H */