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Commit 85eacb06260ca4f92ea4554355c36ad33afeb643

Authored by Philipp Zabel
Committed by Greg Kroah-Hartman
1 parent 2ea42608ba
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

staging: drm/imx: ipu-dc: add WCLK/WRG opcodes 

Add WRG and WCLK opcodes to the display controller microcode,
and allow multi instruction codes.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Showing 1 changed file with 24 additions and 15 deletions Side-by-side Diff

drivers/staging/imx-drm/ipu-v3/ipu-dc.c
Diff comments   View file @ 85eacb0
... ... @@ -61,8 +61,10 @@
61 61  
62 62 #define WROD(lf) (0x18 | ((lf) << 1))
63 63 #define WRG 0x01
  64 +#define WCLK 0xc9
64 65  
65 66 #define SYNC_WAVE 0
  67 +#define NULL_WAVE (-1)
66 68  
67 69 #define DC_GEN_SYNC_1_6_SYNC (2 << 1)
68 70 #define DC_GEN_SYNC_PRIORITY_1 (1 << 7)
69 71  
70 72  
... ... @@ -119,16 +121,23 @@
119 121 }
120 122  
121 123 static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
122   - int map, int wave, int glue, int sync)
  124 + int map, int wave, int glue, int sync, int stop)
123 125 {
124 126 struct ipu_dc_priv *priv = dc->priv;
125   - u32 reg;
126   - int stop = 1;
  127 + u32 reg1, reg2;
127 128  
128   - reg = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000);
129   - writel(reg, priv->dc_tmpl_reg + word * 8);
130   - reg = operand >> 12 | opcode << 4 | stop << 9;
131   - writel(reg, priv->dc_tmpl_reg + word * 8 + 4);
  129 + if (opcode == WCLK) {
  130 + reg1 = (operand << 20) & 0xfff00000;
  131 + reg2 = operand >> 12 | opcode << 1 | stop << 9;
  132 + } else if (opcode == WRG) {
  133 + reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000);
  134 + reg2 = operand >> 17 | opcode << 7 | stop << 9;
  135 + } else {
  136 + reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000);
  137 + reg2 = operand >> 12 | opcode << 4 | stop << 9;
  138 + }
  139 + writel(reg1, priv->dc_tmpl_reg + word * 8);
  140 + writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
132 141 }
133 142  
134 143 static int ipu_pixfmt_to_map(u32 fmt)
135 144  
136 145  
... ... @@ -165,24 +174,24 @@
165 174 dc_link_event(dc, DC_EVT_NEW_DATA, 0, 1);
166 175  
167 176 /* Init template microcode */
168   - dc_write_tmpl(dc, 0, WROD(0), 0, map, SYNC_WAVE, 0, 8);
  177 + dc_write_tmpl(dc, 0, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1);
169 178 } else {
170 179 if (dc->di) {
171 180 dc_link_event(dc, DC_EVT_NL, 2, 3);
172 181 dc_link_event(dc, DC_EVT_EOL, 3, 2);
173 182 dc_link_event(dc, DC_EVT_NEW_DATA, 4, 1);
174 183 /* Init template microcode */
175   - dc_write_tmpl(dc, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5);
176   - dc_write_tmpl(dc, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5);
177   - dc_write_tmpl(dc, 4, WROD(0), 0, map, SYNC_WAVE, 0, 5);
  184 + dc_write_tmpl(dc, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
  185 + dc_write_tmpl(dc, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 1);
  186 + dc_write_tmpl(dc, 4, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
178 187 } else {
179 188 dc_link_event(dc, DC_EVT_NL, 5, 3);
180 189 dc_link_event(dc, DC_EVT_EOL, 6, 2);
181 190 dc_link_event(dc, DC_EVT_NEW_DATA, 7, 1);
182 191 /* Init template microcode */
183   - dc_write_tmpl(dc, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5);
184   - dc_write_tmpl(dc, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5);
185   - dc_write_tmpl(dc, 7, WROD(0), 0, map, SYNC_WAVE, 0, 5);
  192 + dc_write_tmpl(dc, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
  193 + dc_write_tmpl(dc, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 1);
  194 + dc_write_tmpl(dc, 7, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
186 195 }
187 196 }
188 197 dc_link_event(dc, DC_EVT_NF, 0, 0);