Commit 86239ceb33b0d8480b0f0ca0eec08e7f7a807374
1 parent
ca58710f3a
Exists in
smarc-l5.0.0_1.0.0-ga
and in
5 other branches
intel_idle: initial C8, C9, C10 support
Allow intel_idle and cpuidle to utilize C8, C9, C10 when they are present on... "Fourth Generation Intel(R) Core(TM) Processors", which are based on Intel(R) microarchitecture code name Haswell. Signed-off-by: Len Brown <len.brown@intel.com>
Showing 2 changed files with 22 additions and 1 deletions Side-by-side Diff
drivers/idle/intel_idle.c
| ... | ... | @@ -274,6 +274,27 @@ |
| 274 | 274 | .target_residency = 500, |
| 275 | 275 | .enter = &intel_idle }, |
| 276 | 276 | { |
| 277 | + .name = "C8-HSW", | |
| 278 | + .desc = "MWAIT 0x40", | |
| 279 | + .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | |
| 280 | + .exit_latency = 300, | |
| 281 | + .target_residency = 900, | |
| 282 | + .enter = &intel_idle }, | |
| 283 | + { | |
| 284 | + .name = "C9-HSW", | |
| 285 | + .desc = "MWAIT 0x50", | |
| 286 | + .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | |
| 287 | + .exit_latency = 600, | |
| 288 | + .target_residency = 1800, | |
| 289 | + .enter = &intel_idle }, | |
| 290 | + { | |
| 291 | + .name = "C10-HSW", | |
| 292 | + .desc = "MWAIT 0x60", | |
| 293 | + .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | |
| 294 | + .exit_latency = 2600, | |
| 295 | + .target_residency = 7700, | |
| 296 | + .enter = &intel_idle }, | |
| 297 | + { | |
| 277 | 298 | .enter = NULL } |
| 278 | 299 | }; |
| 279 | 300 |