Commit 877d66856e9de4a6d1ffbf61bec6f830bde4d3bf
Exists in
smarc-l5.0.0_1.0.0-ga
and in
5 other branches
Merge remote-tracking branch 'kumar/next' into next
<< Mostly misc code cleanups in various board ports and adding support for a new MPC85xx board - ppa8548. >>
Showing 38 changed files Side-by-side Diff
- Documentation/devicetree/bindings/crypto/fsl-sec4.txt
- Documentation/devicetree/bindings/powerpc/fsl/guts.txt
- Documentation/devicetree/bindings/powerpc/fsl/pamu.txt
- arch/powerpc/boot/dts/bsc9131rdb.dtsi
- arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
- arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
- arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
- arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
- arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
- arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
- arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
- arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
- arch/powerpc/boot/dts/ppa8548.dts
- arch/powerpc/boot/dts/sbc8548-altflash.dts
- arch/powerpc/boot/dts/sbc8548-post.dtsi
- arch/powerpc/boot/dts/sbc8548-pre.dtsi
- arch/powerpc/boot/dts/sbc8548.dts
- arch/powerpc/configs/83xx/kmeter1_defconfig
- arch/powerpc/configs/85xx/ppa8548_defconfig
- arch/powerpc/configs/85xx/sbc8548_defconfig
- arch/powerpc/platforms/512x/mpc512x_shared.c
- arch/powerpc/platforms/82xx/km82xx.c
- arch/powerpc/platforms/83xx/km83xx.c
- arch/powerpc/platforms/85xx/Kconfig
- arch/powerpc/platforms/85xx/Makefile
- arch/powerpc/platforms/85xx/mpc85xx_mds.c
- arch/powerpc/platforms/85xx/p1022_ds.c
- arch/powerpc/platforms/85xx/p1022_rdk.c
- arch/powerpc/platforms/85xx/ppa8548.c
- arch/powerpc/platforms/85xx/qemu_e500.c
- arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
- arch/powerpc/sysdev/fsl_ifc.c
- arch/powerpc/sysdev/fsl_lbc.c
- arch/powerpc/sysdev/fsl_msi.c
- arch/powerpc/sysdev/fsl_pci.c
- arch/powerpc/sysdev/fsl_pci.h
- arch/powerpc/sysdev/fsl_soc.c
- arch/powerpc/sysdev/mpic.c
Documentation/devicetree/bindings/crypto/fsl-sec4.txt
... | ... | @@ -54,9 +54,14 @@ |
54 | 54 | - compatible |
55 | 55 | Usage: required |
56 | 56 | Value type: <string> |
57 | - Definition: Must include "fsl,sec-v4.0". Also includes SEC | |
58 | - ERA versions (optional) with which the device is compatible. | |
57 | + Definition: Must include "fsl,sec-v4.0" | |
59 | 58 | |
59 | + - fsl,sec-era | |
60 | + Usage: optional | |
61 | + Value type: <u32> | |
62 | + Definition: A standard property. Define the 'ERA' of the SEC | |
63 | + device. | |
64 | + | |
60 | 65 | - #address-cells |
61 | 66 | Usage: required |
62 | 67 | Value type: <u32> |
... | ... | @@ -107,7 +112,8 @@ |
107 | 112 | |
108 | 113 | EXAMPLE |
109 | 114 | crypto@300000 { |
110 | - compatible = "fsl,sec-v4.0", "fsl,sec-era-v2.0"; | |
115 | + compatible = "fsl,sec-v4.0"; | |
116 | + fsl,sec-era = <0x2>; | |
111 | 117 | #address-cells = <1>; |
112 | 118 | #size-cells = <1>; |
113 | 119 | reg = <0x300000 0x10000>; |
Documentation/devicetree/bindings/powerpc/fsl/guts.txt
... | ... | @@ -17,10 +17,21 @@ |
17 | 17 | contains a functioning "reset control register" (i.e. the board |
18 | 18 | is wired to reset upon setting the HRESET_REQ bit in this register). |
19 | 19 | |
20 | -Example: | |
20 | + - fsl,liodn-bits : Indicates the number of defined bits in the LIODN | |
21 | + registers, for those SOCs that have a PAMU device. | |
22 | + | |
23 | +Examples: | |
21 | 24 | global-utilities@e0000 { /* global utilities block */ |
22 | 25 | compatible = "fsl,mpc8548-guts"; |
23 | 26 | reg = <e0000 1000>; |
24 | 27 | fsl,has-rstcr; |
28 | + }; | |
29 | + | |
30 | + guts: global-utilities@e0000 { | |
31 | + compatible = "fsl,qoriq-device-config-1.0"; | |
32 | + reg = <0xe0000 0xe00>; | |
33 | + fsl,has-rstcr; | |
34 | + #sleep-cells = <1>; | |
35 | + fsl,liodn-bits = <12>; | |
25 | 36 | }; |
Documentation/devicetree/bindings/powerpc/fsl/pamu.txt
1 | +Freescale Peripheral Management Access Unit (PAMU) Device Tree Binding | |
2 | + | |
3 | +DESCRIPTION | |
4 | + | |
5 | +The PAMU is an I/O MMU that provides device-to-memory access control and | |
6 | +address translation capabilities. | |
7 | + | |
8 | +Required properties: | |
9 | + | |
10 | +- compatible : <string> | |
11 | + First entry is a version-specific string, such as | |
12 | + "fsl,pamu-v1.0". The second is "fsl,pamu". | |
13 | +- ranges : <prop-encoded-array> | |
14 | + A standard property. Utilized to describe the memory mapped | |
15 | + I/O space utilized by the controller. The size should | |
16 | + be set to the total size of the register space of all | |
17 | + physically present PAMU controllers. For example, for | |
18 | + PAMU v1.0, on an SOC that has five PAMU devices, the size | |
19 | + is 0x5000. | |
20 | +- interrupts : <prop-encoded-array> | |
21 | + Interrupt mappings. The first tuple is the normal PAMU | |
22 | + interrupt, used for reporting access violations. The second | |
23 | + is for PAMU hardware errors, such as PAMU operation errors | |
24 | + and ECC errors. | |
25 | +- #address-cells: <u32> | |
26 | + A standard property. | |
27 | +- #size-cells : <u32> | |
28 | + A standard property. | |
29 | + | |
30 | +Optional properties: | |
31 | +- reg : <prop-encoded-array> | |
32 | + A standard property. It represents the CCSR registers of | |
33 | + all child PAMUs combined. Include it to provide support | |
34 | + for legacy drivers. | |
35 | +- interrupt-parent : <phandle> | |
36 | + Phandle to interrupt controller | |
37 | + | |
38 | +Child nodes: | |
39 | + | |
40 | +Each child node represents one PAMU controller. Each SOC device that is | |
41 | +connected to a specific PAMU device should have a "fsl,pamu-phandle" property | |
42 | +that links to the corresponding specific child PAMU controller. | |
43 | + | |
44 | +- reg : <prop-encoded-array> | |
45 | + A standard property. Specifies the physical address and | |
46 | + length (relative to the parent 'ranges' property) of this | |
47 | + PAMU controller's configuration registers. The size should | |
48 | + be set to the size of this PAMU controllers's register space. | |
49 | + For PAMU v1.0, this size is 0x1000. | |
50 | +- fsl,primary-cache-geometry | |
51 | + : <prop-encoded-array> | |
52 | + Two cells that specify the geometry of the primary PAMU | |
53 | + cache. The first is the number of cache lines, and the | |
54 | + second is the number of "ways". For direct-mapped caches, | |
55 | + specify a value of 1. | |
56 | +- fsl,secondary-cache-geometry | |
57 | + : <prop-encoded-array> | |
58 | + Two cells that specify the geometry of the secondary PAMU | |
59 | + cache. The first is the number of cache lines, and the | |
60 | + second is the number of "ways". For direct-mapped caches, | |
61 | + specify a value of 1. | |
62 | + | |
63 | +Device nodes: | |
64 | + | |
65 | +Devices that have LIODNs need to specify links to the parent PAMU controller | |
66 | +(the actual PAMU controller that this device is connected to) and a pointer to | |
67 | +the LIODN register, if applicable. | |
68 | + | |
69 | +- fsl,iommu-parent | |
70 | + : <phandle> | |
71 | + Phandle to the single, specific PAMU controller node to which | |
72 | + this device is connect. The PAMU topology is represented in | |
73 | + the device tree to assist code that dynamically determines the | |
74 | + best LIODN values to minimize PAMU cache thrashing. | |
75 | + | |
76 | +- fsl,liodn-reg : <prop-encoded-array> | |
77 | + Two cells that specify the location of the LIODN register | |
78 | + for this device. Required for devices that have a single | |
79 | + LIODN. The first cell is a phandle to a node that contains | |
80 | + the registers where the LIODN is to be set. The second is | |
81 | + the offset from the first "reg" resource of the node where | |
82 | + the specific LIODN register is located. | |
83 | + | |
84 | + | |
85 | +Example: | |
86 | + | |
87 | + iommu@20000 { | |
88 | + compatible = "fsl,pamu-v1.0", "fsl,pamu"; | |
89 | + reg = <0x20000 0x5000>; | |
90 | + ranges = <0 0x20000 0x5000>; | |
91 | + #address-cells = <1>; | |
92 | + #size-cells = <1>; | |
93 | + interrupts = < | |
94 | + 24 2 0 0 | |
95 | + 16 2 1 30>; | |
96 | + | |
97 | + pamu0: pamu@0 { | |
98 | + reg = <0 0x1000>; | |
99 | + fsl,primary-cache-geometry = <32 1>; | |
100 | + fsl,secondary-cache-geometry = <128 2>; | |
101 | + }; | |
102 | + | |
103 | + pamu1: pamu@1000 { | |
104 | + reg = <0x1000 0x1000>; | |
105 | + fsl,primary-cache-geometry = <32 1>; | |
106 | + fsl,secondary-cache-geometry = <128 2>; | |
107 | + }; | |
108 | + | |
109 | + pamu2: pamu@2000 { | |
110 | + reg = <0x2000 0x1000>; | |
111 | + fsl,primary-cache-geometry = <32 1>; | |
112 | + fsl,secondary-cache-geometry = <128 2>; | |
113 | + }; | |
114 | + | |
115 | + pamu3: pamu@3000 { | |
116 | + reg = <0x3000 0x1000>; | |
117 | + fsl,primary-cache-geometry = <32 1>; | |
118 | + fsl,secondary-cache-geometry = <128 2>; | |
119 | + }; | |
120 | + | |
121 | + pamu4: pamu@4000 { | |
122 | + reg = <0x4000 0x1000>; | |
123 | + fsl,primary-cache-geometry = <32 1>; | |
124 | + fsl,secondary-cache-geometry = <128 2>; | |
125 | + }; | |
126 | + }; | |
127 | + | |
128 | + guts: global-utilities@e0000 { | |
129 | + compatible = "fsl,qoriq-device-config-1.0"; | |
130 | + reg = <0xe0000 0xe00>; | |
131 | + fsl,has-rstcr; | |
132 | + #sleep-cells = <1>; | |
133 | + fsl,liodn-bits = <12>; | |
134 | + }; | |
135 | + | |
136 | +/include/ "qoriq-dma-0.dtsi" | |
137 | + dma@100300 { | |
138 | + fsl,iommu-parent = <&pamu0>; | |
139 | + fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ | |
140 | + }; |
arch/powerpc/boot/dts/bsc9131rdb.dtsi
arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
... | ... | @@ -41,7 +41,7 @@ |
41 | 41 | |
42 | 42 | /* controller at 0x9000 */ |
43 | 43 | &pci0 { |
44 | - compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2"; | |
44 | + compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3"; | |
45 | 45 | device_type = "pci"; |
46 | 46 | #size-cells = <2>; |
47 | 47 | #address-cells = <3>; |
... | ... | @@ -69,7 +69,7 @@ |
69 | 69 | |
70 | 70 | /* controller at 0xa000 */ |
71 | 71 | &pci1 { |
72 | - compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2"; | |
72 | + compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3"; | |
73 | 73 | device_type = "pci"; |
74 | 74 | #size-cells = <2>; |
75 | 75 | #address-cells = <3>; |
arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
... | ... | @@ -45,7 +45,7 @@ |
45 | 45 | |
46 | 46 | /* controller at 0x9000 */ |
47 | 47 | &pci0 { |
48 | - compatible = "fsl,p1022-pcie"; | |
48 | + compatible = "fsl,mpc8548-pcie"; | |
49 | 49 | device_type = "pci"; |
50 | 50 | #size-cells = <2>; |
51 | 51 | #address-cells = <3>; |
... | ... | @@ -73,7 +73,7 @@ |
73 | 73 | |
74 | 74 | /* controller at 0xa000 */ |
75 | 75 | &pci1 { |
76 | - compatible = "fsl,p1022-pcie"; | |
76 | + compatible = "fsl,mpc8548-pcie"; | |
77 | 77 | device_type = "pci"; |
78 | 78 | #size-cells = <2>; |
79 | 79 | #address-cells = <3>; |
... | ... | @@ -102,7 +102,7 @@ |
102 | 102 | |
103 | 103 | /* controller at 0xb000 */ |
104 | 104 | &pci2 { |
105 | - compatible = "fsl,p1022-pcie"; | |
105 | + compatible = "fsl,mpc8548-pcie"; | |
106 | 106 | device_type = "pci"; |
107 | 107 | #size-cells = <2>; |
108 | 108 | #address-cells = <3>; |
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
... | ... | @@ -48,6 +48,8 @@ |
48 | 48 | bus-range = <0x0 0xff>; |
49 | 49 | clock-frequency = <33333333>; |
50 | 50 | interrupts = <16 2 1 15>; |
51 | + fsl,iommu-parent = <&pamu0>; | |
52 | + fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */ | |
51 | 53 | pcie@0 { |
52 | 54 | reg = <0 0 0 0 0>; |
53 | 55 | #interrupt-cells = <1>; |
... | ... | @@ -75,6 +77,8 @@ |
75 | 77 | bus-range = <0 0xff>; |
76 | 78 | clock-frequency = <33333333>; |
77 | 79 | interrupts = <16 2 1 14>; |
80 | + fsl,iommu-parent = <&pamu0>; | |
81 | + fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */ | |
78 | 82 | pcie@0 { |
79 | 83 | reg = <0 0 0 0 0>; |
80 | 84 | #interrupt-cells = <1>; |
... | ... | @@ -102,6 +106,8 @@ |
102 | 106 | bus-range = <0x0 0xff>; |
103 | 107 | clock-frequency = <33333333>; |
104 | 108 | interrupts = <16 2 1 13>; |
109 | + fsl,iommu-parent = <&pamu0>; | |
110 | + fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */ | |
105 | 111 | pcie@0 { |
106 | 112 | reg = <0 0 0 0 0>; |
107 | 113 | #interrupt-cells = <1>; |
108 | 114 | |
109 | 115 | |
... | ... | @@ -125,18 +131,21 @@ |
125 | 131 | interrupts = <16 2 1 11>; |
126 | 132 | #address-cells = <2>; |
127 | 133 | #size-cells = <2>; |
134 | + fsl,iommu-parent = <&pamu0>; | |
128 | 135 | ranges; |
129 | 136 | |
130 | 137 | port1 { |
131 | 138 | #address-cells = <2>; |
132 | 139 | #size-cells = <2>; |
133 | 140 | cell-index = <1>; |
141 | + fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */ | |
134 | 142 | }; |
135 | 143 | |
136 | 144 | port2 { |
137 | 145 | #address-cells = <2>; |
138 | 146 | #size-cells = <2>; |
139 | 147 | cell-index = <2>; |
148 | + fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */ | |
140 | 149 | }; |
141 | 150 | }; |
142 | 151 | |
143 | 152 | |
... | ... | @@ -246,10 +255,37 @@ |
246 | 255 | |
247 | 256 | iommu@20000 { |
248 | 257 | compatible = "fsl,pamu-v1.0", "fsl,pamu"; |
249 | - reg = <0x20000 0x4000>; | |
258 | + reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */ | |
259 | + ranges = <0 0x20000 0x4000>; | |
260 | + #address-cells = <1>; | |
261 | + #size-cells = <1>; | |
250 | 262 | interrupts = < |
251 | 263 | 24 2 0 0 |
252 | 264 | 16 2 1 30>; |
265 | + | |
266 | + pamu0: pamu@0 { | |
267 | + reg = <0 0x1000>; | |
268 | + fsl,primary-cache-geometry = <32 1>; | |
269 | + fsl,secondary-cache-geometry = <128 2>; | |
270 | + }; | |
271 | + | |
272 | + pamu1: pamu@1000 { | |
273 | + reg = <0x1000 0x1000>; | |
274 | + fsl,primary-cache-geometry = <32 1>; | |
275 | + fsl,secondary-cache-geometry = <128 2>; | |
276 | + }; | |
277 | + | |
278 | + pamu2: pamu@2000 { | |
279 | + reg = <0x2000 0x1000>; | |
280 | + fsl,primary-cache-geometry = <32 1>; | |
281 | + fsl,secondary-cache-geometry = <128 2>; | |
282 | + }; | |
283 | + | |
284 | + pamu3: pamu@3000 { | |
285 | + reg = <0x3000 0x1000>; | |
286 | + fsl,primary-cache-geometry = <32 1>; | |
287 | + fsl,secondary-cache-geometry = <128 2>; | |
288 | + }; | |
253 | 289 | }; |
254 | 290 | |
255 | 291 | /include/ "qoriq-mpic.dtsi" |
256 | 292 | |
... | ... | @@ -291,7 +327,17 @@ |
291 | 327 | }; |
292 | 328 | |
293 | 329 | /include/ "qoriq-dma-0.dtsi" |
330 | + dma@100300 { | |
331 | + fsl,iommu-parent = <&pamu0>; | |
332 | + fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ | |
333 | + }; | |
334 | + | |
294 | 335 | /include/ "qoriq-dma-1.dtsi" |
336 | + dma@101300 { | |
337 | + fsl,iommu-parent = <&pamu0>; | |
338 | + fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ | |
339 | + }; | |
340 | + | |
295 | 341 | /include/ "qoriq-espi-0.dtsi" |
296 | 342 | spi@110000 { |
297 | 343 | fsl,espi-num-chipselects = <4>; |
... | ... | @@ -299,6 +345,8 @@ |
299 | 345 | |
300 | 346 | /include/ "qoriq-esdhc-0.dtsi" |
301 | 347 | sdhc@114000 { |
348 | + fsl,iommu-parent = <&pamu1>; | |
349 | + fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ | |
302 | 350 | sdhci,auto-cmd12; |
303 | 351 | }; |
304 | 352 | |
305 | 353 | |
306 | 354 | |
307 | 355 | |
308 | 356 | |
... | ... | @@ -308,21 +356,38 @@ |
308 | 356 | /include/ "qoriq-duart-1.dtsi" |
309 | 357 | /include/ "qoriq-gpio-0.dtsi" |
310 | 358 | /include/ "qoriq-usb2-mph-0.dtsi" |
311 | - usb0: usb@210000 { | |
312 | - compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; | |
313 | - phy_type = "utmi"; | |
314 | - port0; | |
315 | - }; | |
359 | + usb0: usb@210000 { | |
360 | + compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; | |
361 | + phy_type = "utmi"; | |
362 | + fsl,iommu-parent = <&pamu1>; | |
363 | + fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ | |
364 | + port0; | |
365 | + }; | |
316 | 366 | |
317 | 367 | /include/ "qoriq-usb2-dr-0.dtsi" |
318 | - usb1: usb@211000 { | |
319 | - compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; | |
320 | - dr_mode = "host"; | |
321 | - phy_type = "utmi"; | |
322 | - }; | |
368 | + usb1: usb@211000 { | |
369 | + compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; | |
370 | + fsl,iommu-parent = <&pamu1>; | |
371 | + fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */ | |
372 | + dr_mode = "host"; | |
373 | + phy_type = "utmi"; | |
374 | + }; | |
323 | 375 | |
324 | 376 | /include/ "qoriq-sata2-0.dtsi" |
377 | + sata@220000 { | |
378 | + fsl,iommu-parent = <&pamu1>; | |
379 | + fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */ | |
380 | + }; | |
381 | + | |
325 | 382 | /include/ "qoriq-sata2-1.dtsi" |
383 | + sata@221000 { | |
384 | + fsl,iommu-parent = <&pamu1>; | |
385 | + fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */ | |
386 | + }; | |
387 | + | |
326 | 388 | /include/ "qoriq-sec4.2-0.dtsi" |
389 | +crypto: crypto@300000 { | |
390 | + fsl,iommu-parent = <&pamu1>; | |
391 | + }; | |
327 | 392 | }; |
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
... | ... | @@ -48,6 +48,8 @@ |
48 | 48 | bus-range = <0x0 0xff>; |
49 | 49 | clock-frequency = <33333333>; |
50 | 50 | interrupts = <16 2 1 15>; |
51 | + fsl,iommu-parent = <&pamu0>; | |
52 | + fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */ | |
51 | 53 | pcie@0 { |
52 | 54 | reg = <0 0 0 0 0>; |
53 | 55 | #interrupt-cells = <1>; |
... | ... | @@ -75,6 +77,8 @@ |
75 | 77 | bus-range = <0 0xff>; |
76 | 78 | clock-frequency = <33333333>; |
77 | 79 | interrupts = <16 2 1 14>; |
80 | + fsl,iommu-parent = <&pamu0>; | |
81 | + fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */ | |
78 | 82 | pcie@0 { |
79 | 83 | reg = <0 0 0 0 0>; |
80 | 84 | #interrupt-cells = <1>; |
... | ... | @@ -102,6 +106,8 @@ |
102 | 106 | bus-range = <0x0 0xff>; |
103 | 107 | clock-frequency = <33333333>; |
104 | 108 | interrupts = <16 2 1 13>; |
109 | + fsl,iommu-parent = <&pamu0>; | |
110 | + fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */ | |
105 | 111 | pcie@0 { |
106 | 112 | reg = <0 0 0 0 0>; |
107 | 113 | #interrupt-cells = <1>; |
108 | 114 | |
109 | 115 | |
... | ... | @@ -152,18 +158,21 @@ |
152 | 158 | interrupts = <16 2 1 11>; |
153 | 159 | #address-cells = <2>; |
154 | 160 | #size-cells = <2>; |
161 | + fsl,iommu-parent = <&pamu0>; | |
155 | 162 | ranges; |
156 | 163 | |
157 | 164 | port1 { |
158 | 165 | #address-cells = <2>; |
159 | 166 | #size-cells = <2>; |
160 | 167 | cell-index = <1>; |
168 | + fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */ | |
161 | 169 | }; |
162 | 170 | |
163 | 171 | port2 { |
164 | 172 | #address-cells = <2>; |
165 | 173 | #size-cells = <2>; |
166 | 174 | cell-index = <2>; |
175 | + fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */ | |
167 | 176 | }; |
168 | 177 | }; |
169 | 178 | |
170 | 179 | |
... | ... | @@ -273,10 +282,37 @@ |
273 | 282 | |
274 | 283 | iommu@20000 { |
275 | 284 | compatible = "fsl,pamu-v1.0", "fsl,pamu"; |
276 | - reg = <0x20000 0x4000>; | |
285 | + reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */ | |
286 | + ranges = <0 0x20000 0x4000>; | |
287 | + #address-cells = <1>; | |
288 | + #size-cells = <1>; | |
277 | 289 | interrupts = < |
278 | 290 | 24 2 0 0 |
279 | 291 | 16 2 1 30>; |
292 | + | |
293 | + pamu0: pamu@0 { | |
294 | + reg = <0 0x1000>; | |
295 | + fsl,primary-cache-geometry = <32 1>; | |
296 | + fsl,secondary-cache-geometry = <128 2>; | |
297 | + }; | |
298 | + | |
299 | + pamu1: pamu@1000 { | |
300 | + reg = <0x1000 0x1000>; | |
301 | + fsl,primary-cache-geometry = <32 1>; | |
302 | + fsl,secondary-cache-geometry = <128 2>; | |
303 | + }; | |
304 | + | |
305 | + pamu2: pamu@2000 { | |
306 | + reg = <0x2000 0x1000>; | |
307 | + fsl,primary-cache-geometry = <32 1>; | |
308 | + fsl,secondary-cache-geometry = <128 2>; | |
309 | + }; | |
310 | + | |
311 | + pamu3: pamu@3000 { | |
312 | + reg = <0x3000 0x1000>; | |
313 | + fsl,primary-cache-geometry = <32 1>; | |
314 | + fsl,secondary-cache-geometry = <128 2>; | |
315 | + }; | |
280 | 316 | }; |
281 | 317 | |
282 | 318 | /include/ "qoriq-mpic.dtsi" |
283 | 319 | |
... | ... | @@ -318,7 +354,17 @@ |
318 | 354 | }; |
319 | 355 | |
320 | 356 | /include/ "qoriq-dma-0.dtsi" |
357 | + dma@100300 { | |
358 | + fsl,iommu-parent = <&pamu0>; | |
359 | + fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ | |
360 | + }; | |
361 | + | |
321 | 362 | /include/ "qoriq-dma-1.dtsi" |
363 | + dma@101300 { | |
364 | + fsl,iommu-parent = <&pamu0>; | |
365 | + fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ | |
366 | + }; | |
367 | + | |
322 | 368 | /include/ "qoriq-espi-0.dtsi" |
323 | 369 | spi@110000 { |
324 | 370 | fsl,espi-num-chipselects = <4>; |
... | ... | @@ -326,6 +372,8 @@ |
326 | 372 | |
327 | 373 | /include/ "qoriq-esdhc-0.dtsi" |
328 | 374 | sdhc@114000 { |
375 | + fsl,iommu-parent = <&pamu1>; | |
376 | + fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ | |
329 | 377 | sdhci,auto-cmd12; |
330 | 378 | }; |
331 | 379 | |
332 | 380 | |
333 | 381 | |
334 | 382 | |
335 | 383 | |
... | ... | @@ -335,21 +383,38 @@ |
335 | 383 | /include/ "qoriq-duart-1.dtsi" |
336 | 384 | /include/ "qoriq-gpio-0.dtsi" |
337 | 385 | /include/ "qoriq-usb2-mph-0.dtsi" |
338 | - usb0: usb@210000 { | |
339 | - compatible = "fsl-usb2-mph-v1.6", "fsl-usb2-mph"; | |
340 | - phy_type = "utmi"; | |
341 | - port0; | |
342 | - }; | |
386 | + usb0: usb@210000 { | |
387 | + compatible = "fsl-usb2-mph-v1.6", "fsl-usb2-mph"; | |
388 | + phy_type = "utmi"; | |
389 | + fsl,iommu-parent = <&pamu1>; | |
390 | + fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ | |
391 | + port0; | |
392 | + }; | |
343 | 393 | |
344 | 394 | /include/ "qoriq-usb2-dr-0.dtsi" |
345 | - usb1: usb@211000 { | |
346 | - compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; | |
347 | - dr_mode = "host"; | |
348 | - phy_type = "utmi"; | |
349 | - }; | |
395 | + usb1: usb@211000 { | |
396 | + compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; | |
397 | + fsl,iommu-parent = <&pamu1>; | |
398 | + fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */ | |
399 | + dr_mode = "host"; | |
400 | + phy_type = "utmi"; | |
401 | + }; | |
350 | 402 | |
351 | 403 | /include/ "qoriq-sata2-0.dtsi" |
404 | + sata@220000 { | |
405 | + fsl,iommu-parent = <&pamu1>; | |
406 | + fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */ | |
407 | + }; | |
408 | + | |
352 | 409 | /include/ "qoriq-sata2-1.dtsi" |
410 | + sata@221000 { | |
411 | + fsl,iommu-parent = <&pamu1>; | |
412 | + fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */ | |
413 | + }; | |
414 | + | |
353 | 415 | /include/ "qoriq-sec4.2-0.dtsi" |
416 | +crypto: crypto@300000 { | |
417 | + fsl,iommu-parent = <&pamu1>; | |
418 | + }; | |
354 | 419 | }; |
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
... | ... | @@ -41,13 +41,15 @@ |
41 | 41 | |
42 | 42 | /* controller at 0x200000 */ |
43 | 43 | &pci0 { |
44 | - compatible = "fsl,p4080-pcie"; | |
44 | + compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1"; | |
45 | 45 | device_type = "pci"; |
46 | 46 | #size-cells = <2>; |
47 | 47 | #address-cells = <3>; |
48 | 48 | bus-range = <0x0 0xff>; |
49 | 49 | clock-frequency = <33333333>; |
50 | 50 | interrupts = <16 2 1 15>; |
51 | + fsl,iommu-parent = <&pamu0>; | |
52 | + fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */ | |
51 | 53 | pcie@0 { |
52 | 54 | reg = <0 0 0 0 0>; |
53 | 55 | #interrupt-cells = <1>; |
54 | 56 | |
... | ... | @@ -68,13 +70,15 @@ |
68 | 70 | |
69 | 71 | /* controller at 0x201000 */ |
70 | 72 | &pci1 { |
71 | - compatible = "fsl,p4080-pcie"; | |
73 | + compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1"; | |
72 | 74 | device_type = "pci"; |
73 | 75 | #size-cells = <2>; |
74 | 76 | #address-cells = <3>; |
75 | 77 | bus-range = <0 0xff>; |
76 | 78 | clock-frequency = <33333333>; |
77 | 79 | interrupts = <16 2 1 14>; |
80 | + fsl,iommu-parent = <&pamu0>; | |
81 | + fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */ | |
78 | 82 | pcie@0 { |
79 | 83 | reg = <0 0 0 0 0>; |
80 | 84 | #interrupt-cells = <1>; |
81 | 85 | |
... | ... | @@ -95,13 +99,15 @@ |
95 | 99 | |
96 | 100 | /* controller at 0x202000 */ |
97 | 101 | &pci2 { |
98 | - compatible = "fsl,p4080-pcie"; | |
102 | + compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1"; | |
99 | 103 | device_type = "pci"; |
100 | 104 | #size-cells = <2>; |
101 | 105 | #address-cells = <3>; |
102 | 106 | bus-range = <0x0 0xff>; |
103 | 107 | clock-frequency = <33333333>; |
104 | 108 | interrupts = <16 2 1 13>; |
109 | + fsl,iommu-parent = <&pamu0>; | |
110 | + fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */ | |
105 | 111 | pcie@0 { |
106 | 112 | reg = <0 0 0 0 0>; |
107 | 113 | #interrupt-cells = <1>; |
108 | 114 | |
109 | 115 | |
... | ... | @@ -126,18 +132,21 @@ |
126 | 132 | #address-cells = <2>; |
127 | 133 | #size-cells = <2>; |
128 | 134 | fsl,srio-rmu-handle = <&rmu>; |
135 | + fsl,iommu-parent = <&pamu0>; | |
129 | 136 | ranges; |
130 | 137 | |
131 | 138 | port1 { |
132 | 139 | #address-cells = <2>; |
133 | 140 | #size-cells = <2>; |
134 | 141 | cell-index = <1>; |
142 | + fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */ | |
135 | 143 | }; |
136 | 144 | |
137 | 145 | port2 { |
138 | 146 | #address-cells = <2>; |
139 | 147 | #size-cells = <2>; |
140 | 148 | cell-index = <2>; |
149 | + fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */ | |
141 | 150 | }; |
142 | 151 | }; |
143 | 152 | |
144 | 153 | |
145 | 154 | |
... | ... | @@ -281,13 +290,51 @@ |
281 | 290 | |
282 | 291 | iommu@20000 { |
283 | 292 | compatible = "fsl,pamu-v1.0", "fsl,pamu"; |
284 | - reg = <0x20000 0x5000>; | |
293 | + reg = <0x20000 0x5000>; /* for compatibility with older PAMU drivers */ | |
294 | + ranges = <0 0x20000 0x5000>; | |
295 | + #address-cells = <1>; | |
296 | + #size-cells = <1>; | |
285 | 297 | interrupts = < |
286 | 298 | 24 2 0 0 |
287 | 299 | 16 2 1 30>; |
300 | + | |
301 | + pamu0: pamu@0 { | |
302 | + reg = <0 0x1000>; | |
303 | + fsl,primary-cache-geometry = <32 1>; | |
304 | + fsl,secondary-cache-geometry = <128 2>; | |
305 | + }; | |
306 | + | |
307 | + pamu1: pamu@1000 { | |
308 | + reg = <0x1000 0x1000>; | |
309 | + fsl,primary-cache-geometry = <32 1>; | |
310 | + fsl,secondary-cache-geometry = <128 2>; | |
311 | + }; | |
312 | + | |
313 | + pamu2: pamu@2000 { | |
314 | + reg = <0x2000 0x1000>; | |
315 | + fsl,primary-cache-geometry = <32 1>; | |
316 | + fsl,secondary-cache-geometry = <128 2>; | |
317 | + }; | |
318 | + | |
319 | + pamu3: pamu@3000 { | |
320 | + reg = <0x3000 0x1000>; | |
321 | + fsl,primary-cache-geometry = <32 1>; | |
322 | + fsl,secondary-cache-geometry = <128 2>; | |
323 | + }; | |
324 | + | |
325 | + pamu4: pamu@4000 { | |
326 | + reg = <0x4000 0x1000>; | |
327 | + fsl,primary-cache-geometry = <32 1>; | |
328 | + fsl,secondary-cache-geometry = <128 2>; | |
329 | + }; | |
288 | 330 | }; |
289 | 331 | |
290 | 332 | /include/ "qoriq-rmu-0.dtsi" |
333 | + rmu@d3000 { | |
334 | + fsl,iommu-parent = <&pamu0>; | |
335 | + fsl,liodn-reg = <&guts 0x540>; /* RMULIODNR */ | |
336 | + }; | |
337 | + | |
291 | 338 | /include/ "qoriq-mpic.dtsi" |
292 | 339 | |
293 | 340 | guts: global-utilities@e0000 { |
294 | 341 | |
... | ... | @@ -327,7 +374,17 @@ |
327 | 374 | }; |
328 | 375 | |
329 | 376 | /include/ "qoriq-dma-0.dtsi" |
377 | + dma@100300 { | |
378 | + fsl,iommu-parent = <&pamu0>; | |
379 | + fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ | |
380 | + }; | |
381 | + | |
330 | 382 | /include/ "qoriq-dma-1.dtsi" |
383 | + dma@101300 { | |
384 | + fsl,iommu-parent = <&pamu0>; | |
385 | + fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ | |
386 | + }; | |
387 | + | |
331 | 388 | /include/ "qoriq-espi-0.dtsi" |
332 | 389 | spi@110000 { |
333 | 390 | fsl,espi-num-chipselects = <4>; |
... | ... | @@ -335,6 +392,8 @@ |
335 | 392 | |
336 | 393 | /include/ "qoriq-esdhc-0.dtsi" |
337 | 394 | sdhc@114000 { |
395 | + fsl,iommu-parent = <&pamu1>; | |
396 | + fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ | |
338 | 397 | voltage-ranges = <3300 3300>; |
339 | 398 | sdhci,auto-cmd12; |
340 | 399 | }; |
341 | 400 | |
342 | 401 | |
... | ... | @@ -347,12 +406,19 @@ |
347 | 406 | /include/ "qoriq-usb2-mph-0.dtsi" |
348 | 407 | usb@210000 { |
349 | 408 | compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; |
409 | + fsl,iommu-parent = <&pamu1>; | |
410 | + fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ | |
350 | 411 | port0; |
351 | 412 | }; |
352 | 413 | /include/ "qoriq-usb2-dr-0.dtsi" |
353 | 414 | usb@211000 { |
354 | 415 | compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; |
416 | + fsl,iommu-parent = <&pamu1>; | |
417 | + fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */ | |
355 | 418 | }; |
356 | 419 | /include/ "qoriq-sec4.0-0.dtsi" |
420 | +crypto: crypto@300000 { | |
421 | + fsl,iommu-parent = <&pamu1>; | |
422 | + }; | |
357 | 423 | }; |
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
... | ... | @@ -48,6 +48,8 @@ |
48 | 48 | bus-range = <0x0 0xff>; |
49 | 49 | clock-frequency = <33333333>; |
50 | 50 | interrupts = <16 2 1 15>; |
51 | + fsl,iommu-parent = <&pamu0>; | |
52 | + fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */ | |
51 | 53 | pcie@0 { |
52 | 54 | reg = <0 0 0 0 0>; |
53 | 55 | #interrupt-cells = <1>; |
... | ... | @@ -75,6 +77,8 @@ |
75 | 77 | bus-range = <0 0xff>; |
76 | 78 | clock-frequency = <33333333>; |
77 | 79 | interrupts = <16 2 1 14>; |
80 | + fsl,iommu-parent = <&pamu0>; | |
81 | + fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */ | |
78 | 82 | pcie@0 { |
79 | 83 | reg = <0 0 0 0 0>; |
80 | 84 | #interrupt-cells = <1>; |
... | ... | @@ -102,6 +106,8 @@ |
102 | 106 | bus-range = <0x0 0xff>; |
103 | 107 | clock-frequency = <33333333>; |
104 | 108 | interrupts = <16 2 1 13>; |
109 | + fsl,iommu-parent = <&pamu0>; | |
110 | + fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */ | |
105 | 111 | pcie@0 { |
106 | 112 | reg = <0 0 0 0 0>; |
107 | 113 | #interrupt-cells = <1>; |
... | ... | @@ -129,6 +135,8 @@ |
129 | 135 | bus-range = <0x0 0xff>; |
130 | 136 | clock-frequency = <33333333>; |
131 | 137 | interrupts = <16 2 1 12>; |
138 | + fsl,iommu-parent = <&pamu0>; | |
139 | + fsl,liodn-reg = <&guts 0x50c>; /* PEX4LIODNR */ | |
132 | 140 | pcie@0 { |
133 | 141 | reg = <0 0 0 0 0>; |
134 | 142 | #interrupt-cells = <1>; |
135 | 143 | |
136 | 144 | |
... | ... | @@ -152,18 +160,21 @@ |
152 | 160 | interrupts = <16 2 1 11>; |
153 | 161 | #address-cells = <2>; |
154 | 162 | #size-cells = <2>; |
163 | + fsl,iommu-parent = <&pamu0>; | |
155 | 164 | ranges; |
156 | 165 | |
157 | 166 | port1 { |
158 | 167 | #address-cells = <2>; |
159 | 168 | #size-cells = <2>; |
160 | 169 | cell-index = <1>; |
170 | + fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */ | |
161 | 171 | }; |
162 | 172 | |
163 | 173 | port2 { |
164 | 174 | #address-cells = <2>; |
165 | 175 | #size-cells = <2>; |
166 | 176 | cell-index = <2>; |
177 | + fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */ | |
167 | 178 | }; |
168 | 179 | }; |
169 | 180 | |
170 | 181 | |
... | ... | @@ -276,10 +287,37 @@ |
276 | 287 | |
277 | 288 | iommu@20000 { |
278 | 289 | compatible = "fsl,pamu-v1.0", "fsl,pamu"; |
279 | - reg = <0x20000 0x4000>; | |
290 | + reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */ | |
291 | + ranges = <0 0x20000 0x4000>; | |
292 | + #address-cells = <1>; | |
293 | + #size-cells = <1>; | |
280 | 294 | interrupts = < |
281 | 295 | 24 2 0 0 |
282 | 296 | 16 2 1 30>; |
297 | + | |
298 | + pamu0: pamu@0 { | |
299 | + reg = <0 0x1000>; | |
300 | + fsl,primary-cache-geometry = <32 1>; | |
301 | + fsl,secondary-cache-geometry = <128 2>; | |
302 | + }; | |
303 | + | |
304 | + pamu1: pamu@1000 { | |
305 | + reg = <0x1000 0x1000>; | |
306 | + fsl,primary-cache-geometry = <32 1>; | |
307 | + fsl,secondary-cache-geometry = <128 2>; | |
308 | + }; | |
309 | + | |
310 | + pamu2: pamu@2000 { | |
311 | + reg = <0x2000 0x1000>; | |
312 | + fsl,primary-cache-geometry = <32 1>; | |
313 | + fsl,secondary-cache-geometry = <128 2>; | |
314 | + }; | |
315 | + | |
316 | + pamu3: pamu@3000 { | |
317 | + reg = <0x3000 0x1000>; | |
318 | + fsl,primary-cache-geometry = <32 1>; | |
319 | + fsl,secondary-cache-geometry = <128 2>; | |
320 | + }; | |
283 | 321 | }; |
284 | 322 | |
285 | 323 | /include/ "qoriq-mpic.dtsi" |
286 | 324 | |
... | ... | @@ -321,7 +359,17 @@ |
321 | 359 | }; |
322 | 360 | |
323 | 361 | /include/ "qoriq-dma-0.dtsi" |
362 | + dma@100300 { | |
363 | + fsl,iommu-parent = <&pamu0>; | |
364 | + fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ | |
365 | + }; | |
366 | + | |
324 | 367 | /include/ "qoriq-dma-1.dtsi" |
368 | + dma@101300 { | |
369 | + fsl,iommu-parent = <&pamu0>; | |
370 | + fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ | |
371 | + }; | |
372 | + | |
325 | 373 | /include/ "qoriq-espi-0.dtsi" |
326 | 374 | spi@110000 { |
327 | 375 | fsl,espi-num-chipselects = <4>; |
... | ... | @@ -329,6 +377,8 @@ |
329 | 377 | |
330 | 378 | /include/ "qoriq-esdhc-0.dtsi" |
331 | 379 | sdhc@114000 { |
380 | + fsl,iommu-parent = <&pamu1>; | |
381 | + fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ | |
332 | 382 | sdhci,auto-cmd12; |
333 | 383 | }; |
334 | 384 | |
335 | 385 | |
336 | 386 | |
337 | 387 | |
338 | 388 | |
339 | 389 | |
... | ... | @@ -338,22 +388,42 @@ |
338 | 388 | /include/ "qoriq-duart-1.dtsi" |
339 | 389 | /include/ "qoriq-gpio-0.dtsi" |
340 | 390 | /include/ "qoriq-usb2-mph-0.dtsi" |
341 | - usb0: usb@210000 { | |
342 | - compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; | |
343 | - phy_type = "utmi"; | |
344 | - port0; | |
345 | - }; | |
391 | + usb0: usb@210000 { | |
392 | + compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; | |
393 | + fsl,iommu-parent = <&pamu1>; | |
394 | + fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ | |
395 | + phy_type = "utmi"; | |
396 | + port0; | |
397 | + }; | |
346 | 398 | |
347 | 399 | /include/ "qoriq-usb2-dr-0.dtsi" |
348 | - usb1: usb@211000 { | |
349 | - compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; | |
350 | - dr_mode = "host"; | |
351 | - phy_type = "utmi"; | |
352 | - }; | |
400 | + usb1: usb@211000 { | |
401 | + compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; | |
402 | + fsl,iommu-parent = <&pamu1>; | |
403 | + fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */ | |
404 | + dr_mode = "host"; | |
405 | + phy_type = "utmi"; | |
406 | + }; | |
353 | 407 | |
354 | 408 | /include/ "qoriq-sata2-0.dtsi" |
409 | + sata@220000 { | |
410 | + fsl,iommu-parent = <&pamu1>; | |
411 | + fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */ | |
412 | + }; | |
413 | + | |
355 | 414 | /include/ "qoriq-sata2-1.dtsi" |
415 | + sata@221000 { | |
416 | + fsl,iommu-parent = <&pamu1>; | |
417 | + fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */ | |
418 | + }; | |
356 | 419 | /include/ "qoriq-sec4.2-0.dtsi" |
420 | + crypto@300000 { | |
421 | + fsl,iommu-parent = <&pamu1>; | |
422 | + }; | |
423 | + | |
357 | 424 | /include/ "qoriq-raid1.0-0.dtsi" |
425 | + raideng@320000 { | |
426 | + fsl,iommu-parent = <&pamu1>; | |
427 | + }; | |
358 | 428 | }; |
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
... | ... | @@ -48,6 +48,7 @@ |
48 | 48 | bus-range = <0x0 0xff>; |
49 | 49 | clock-frequency = <33333333>; |
50 | 50 | interrupts = <16 2 1 15>; |
51 | + fsl,iommu-parent = <&pamu0>; | |
51 | 52 | pcie@0 { |
52 | 53 | reg = <0 0 0 0 0>; |
53 | 54 | #interrupt-cells = <1>; |
... | ... | @@ -75,6 +76,7 @@ |
75 | 76 | bus-range = <0 0xff>; |
76 | 77 | clock-frequency = <33333333>; |
77 | 78 | interrupts = <16 2 1 14>; |
79 | + fsl,iommu-parent = <&pamu0>; | |
78 | 80 | pcie@0 { |
79 | 81 | reg = <0 0 0 0 0>; |
80 | 82 | #interrupt-cells = <1>; |
... | ... | @@ -102,6 +104,7 @@ |
102 | 104 | bus-range = <0x0 0xff>; |
103 | 105 | clock-frequency = <33333333>; |
104 | 106 | interrupts = <16 2 1 13>; |
107 | + fsl,iommu-parent = <&pamu0>; | |
105 | 108 | pcie@0 { |
106 | 109 | reg = <0 0 0 0 0>; |
107 | 110 | #interrupt-cells = <1>; |
... | ... | @@ -239,10 +242,42 @@ |
239 | 242 | |
240 | 243 | iommu@20000 { |
241 | 244 | compatible = "fsl,pamu-v1.0", "fsl,pamu"; |
242 | - reg = <0x20000 0x5000>; | |
243 | - interrupts = < | |
244 | - 24 2 0 0 | |
245 | - 16 2 1 30>; | |
245 | + reg = <0x20000 0x5000>; /* for compatibility with older PAMU drivers */ | |
246 | + ranges = <0 0x20000 0x5000>; | |
247 | + #address-cells = <1>; | |
248 | + #size-cells = <1>; | |
249 | + interrupts = <24 2 0 0 | |
250 | + 16 2 1 30>; | |
251 | + | |
252 | + pamu0: pamu@0 { | |
253 | + reg = <0 0x1000>; | |
254 | + fsl,primary-cache-geometry = <32 1>; | |
255 | + fsl,secondary-cache-geometry = <128 2>; | |
256 | + }; | |
257 | + | |
258 | + pamu1: pamu@1000 { | |
259 | + reg = <0x1000 0x1000>; | |
260 | + fsl,primary-cache-geometry = <32 1>; | |
261 | + fsl,secondary-cache-geometry = <128 2>; | |
262 | + }; | |
263 | + | |
264 | + pamu2: pamu@2000 { | |
265 | + reg = <0x2000 0x1000>; | |
266 | + fsl,primary-cache-geometry = <32 1>; | |
267 | + fsl,secondary-cache-geometry = <128 2>; | |
268 | + }; | |
269 | + | |
270 | + pamu3: pamu@3000 { | |
271 | + reg = <0x3000 0x1000>; | |
272 | + fsl,primary-cache-geometry = <32 1>; | |
273 | + fsl,secondary-cache-geometry = <128 2>; | |
274 | + }; | |
275 | + | |
276 | + pamu4: pamu@4000 { | |
277 | + reg = <0x4000 0x1000>; | |
278 | + fsl,primary-cache-geometry = <32 1>; | |
279 | + fsl,secondary-cache-geometry = <128 2>; | |
280 | + }; | |
246 | 281 | }; |
247 | 282 | |
248 | 283 | /include/ "qoriq-mpic.dtsi" |
249 | 284 | |
... | ... | @@ -284,7 +319,17 @@ |
284 | 319 | }; |
285 | 320 | |
286 | 321 | /include/ "qoriq-dma-0.dtsi" |
322 | + dma@100300 { | |
323 | + fsl,iommu-parent = <&pamu0>; | |
324 | + fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ | |
325 | + }; | |
326 | + | |
287 | 327 | /include/ "qoriq-dma-1.dtsi" |
328 | + dma@101300 { | |
329 | + fsl,iommu-parent = <&pamu0>; | |
330 | + fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ | |
331 | + }; | |
332 | + | |
288 | 333 | /include/ "qoriq-espi-0.dtsi" |
289 | 334 | spi@110000 { |
290 | 335 | fsl,espi-num-chipselects = <4>; |
... | ... | @@ -292,6 +337,8 @@ |
292 | 337 | |
293 | 338 | /include/ "qoriq-esdhc-0.dtsi" |
294 | 339 | sdhc@114000 { |
340 | + fsl,iommu-parent = <&pamu2>; | |
341 | + fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ | |
295 | 342 | sdhci,auto-cmd12; |
296 | 343 | }; |
297 | 344 | |
298 | 345 | |
299 | 346 | |
300 | 347 | |
301 | 348 | |
... | ... | @@ -301,21 +348,38 @@ |
301 | 348 | /include/ "qoriq-duart-1.dtsi" |
302 | 349 | /include/ "qoriq-gpio-0.dtsi" |
303 | 350 | /include/ "qoriq-usb2-mph-0.dtsi" |
304 | - usb0: usb@210000 { | |
305 | - compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; | |
306 | - phy_type = "utmi"; | |
307 | - port0; | |
308 | - }; | |
351 | + usb0: usb@210000 { | |
352 | + compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; | |
353 | + fsl,iommu-parent = <&pamu4>; | |
354 | + fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ | |
355 | + phy_type = "utmi"; | |
356 | + port0; | |
357 | + }; | |
309 | 358 | |
310 | 359 | /include/ "qoriq-usb2-dr-0.dtsi" |
311 | - usb1: usb@211000 { | |
312 | - compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; | |
313 | - dr_mode = "host"; | |
314 | - phy_type = "utmi"; | |
315 | - }; | |
360 | + usb1: usb@211000 { | |
361 | + compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; | |
362 | + fsl,iommu-parent = <&pamu4>; | |
363 | + fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */ | |
364 | + dr_mode = "host"; | |
365 | + phy_type = "utmi"; | |
366 | + }; | |
316 | 367 | |
317 | 368 | /include/ "qoriq-sata2-0.dtsi" |
369 | + sata@220000 { | |
370 | + fsl,iommu-parent = <&pamu4>; | |
371 | + fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */ | |
372 | + }; | |
373 | + | |
318 | 374 | /include/ "qoriq-sata2-1.dtsi" |
375 | + sata@221000 { | |
376 | + fsl,iommu-parent = <&pamu4>; | |
377 | + fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */ | |
378 | + }; | |
379 | + | |
319 | 380 | /include/ "qoriq-sec5.2-0.dtsi" |
381 | + crypto@300000 { | |
382 | + fsl,iommu-parent = <&pamu4>; | |
383 | + }; | |
320 | 384 | }; |
arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
arch/powerpc/boot/dts/ppa8548.dts
1 | +/* | |
2 | + * PPA8548 Device Tree Source (36-bit address map) | |
3 | + * Copyright 2013 Prodrive B.V. | |
4 | + * | |
5 | + * Based on: | |
6 | + * MPC8548 CDS Device Tree Source (36-bit address map) | |
7 | + * Copyright 2012 Freescale Semiconductor Inc. | |
8 | + * | |
9 | + * This program is free software; you can redistribute it and/or modify it | |
10 | + * under the terms of the GNU General Public License as published by the | |
11 | + * Free Software Foundation; either version 2 of the License, or (at your | |
12 | + * option) any later version. | |
13 | + */ | |
14 | + | |
15 | +/include/ "fsl/mpc8548si-pre.dtsi" | |
16 | + | |
17 | +/ { | |
18 | + model = "ppa8548"; | |
19 | + compatible = "ppa8548"; | |
20 | + #address-cells = <2>; | |
21 | + #size-cells = <2>; | |
22 | + interrupt-parent = <&mpic>; | |
23 | + | |
24 | + memory { | |
25 | + device_type = "memory"; | |
26 | + reg = <0 0 0x0 0x40000000>; | |
27 | + }; | |
28 | + | |
29 | + lbc: localbus@fe0005000 { | |
30 | + reg = <0xf 0xe0005000 0 0x1000>; | |
31 | + ranges = <0x0 0x0 0xf 0xff800000 0x00800000>; | |
32 | + }; | |
33 | + | |
34 | + soc: soc8548@fe0000000 { | |
35 | + ranges = <0 0xf 0xe0000000 0x100000>; | |
36 | + }; | |
37 | + | |
38 | + pci0: pci@fe0008000 { | |
39 | + /* ppa8548 board doesn't support PCI */ | |
40 | + status = "disabled"; | |
41 | + }; | |
42 | + | |
43 | + pci1: pci@fe0009000 { | |
44 | + /* ppa8548 board doesn't support PCI */ | |
45 | + status = "disabled"; | |
46 | + }; | |
47 | + | |
48 | + pci2: pcie@fe000a000 { | |
49 | + /* ppa8548 board doesn't support PCI */ | |
50 | + status = "disabled"; | |
51 | + }; | |
52 | + | |
53 | + rio: rapidio@fe00c0000 { | |
54 | + reg = <0xf 0xe00c0000 0x0 0x11000>; | |
55 | + port1 { | |
56 | + ranges = <0x0 0x0 0x0 0x80000000 0x0 0x40000000>; | |
57 | + }; | |
58 | + }; | |
59 | +}; | |
60 | + | |
61 | +&lbc { | |
62 | + nor@0 { | |
63 | + #address-cells = <1>; | |
64 | + #size-cells = <1>; | |
65 | + compatible = "cfi-flash"; | |
66 | + reg = <0x0 0x0 0x00800000>; | |
67 | + bank-width = <2>; | |
68 | + device-width = <2>; | |
69 | + | |
70 | + partition@0 { | |
71 | + reg = <0x0 0x7A0000>; | |
72 | + label = "user"; | |
73 | + }; | |
74 | + | |
75 | + partition@7A0000 { | |
76 | + reg = <0x7A0000 0x20000>; | |
77 | + label = "env"; | |
78 | + read-only; | |
79 | + }; | |
80 | + | |
81 | + partition@7C0000 { | |
82 | + reg = <0x7C0000 0x40000>; | |
83 | + label = "u-boot"; | |
84 | + read-only; | |
85 | + }; | |
86 | + }; | |
87 | +}; | |
88 | + | |
89 | +&soc { | |
90 | + i2c@3000 { | |
91 | + rtc@6f { | |
92 | + compatible = "intersil,isl1208"; | |
93 | + reg = <0x6f>; | |
94 | + }; | |
95 | + }; | |
96 | + | |
97 | + i2c@3100 { | |
98 | + }; | |
99 | + | |
100 | + /* | |
101 | + * Only ethernet controller @25000 and @26000 are used. | |
102 | + * Use alias enet2 and enet3 for the remainig controllers, | |
103 | + * to stay compatible with mpc8548si-pre.dtsi. | |
104 | + */ | |
105 | + enet2: ethernet@24000 { | |
106 | + status = "disabled"; | |
107 | + }; | |
108 | + | |
109 | + mdio@24520 { | |
110 | + phy0: ethernet-phy@0 { | |
111 | + interrupts = <7 1 0 0>; | |
112 | + reg = <0x0>; | |
113 | + device_type = "ethernet-phy"; | |
114 | + }; | |
115 | + phy1: ethernet-phy@1 { | |
116 | + interrupts = <8 1 0 0>; | |
117 | + reg = <0x1>; | |
118 | + device_type = "ethernet-phy"; | |
119 | + }; | |
120 | + tbi0: tbi-phy@11 { | |
121 | + reg = <0x11>; | |
122 | + device_type = "tbi-phy"; | |
123 | + }; | |
124 | + }; | |
125 | + | |
126 | + enet0: ethernet@25000 { | |
127 | + tbi-handle = <&tbi1>; | |
128 | + phy-handle = <&phy0>; | |
129 | + }; | |
130 | + | |
131 | + mdio@25520 { | |
132 | + tbi1: tbi-phy@11 { | |
133 | + reg = <0x11>; | |
134 | + device_type = "tbi-phy"; | |
135 | + }; | |
136 | + }; | |
137 | + | |
138 | + enet1: ethernet@26000 { | |
139 | + tbi-handle = <&tbi2>; | |
140 | + phy-handle = <&phy1>; | |
141 | + }; | |
142 | + | |
143 | + mdio@26520 { | |
144 | + tbi2: tbi-phy@11 { | |
145 | + reg = <0x11>; | |
146 | + device_type = "tbi-phy"; | |
147 | + }; | |
148 | + }; | |
149 | + | |
150 | + enet3: ethernet@27000 { | |
151 | + status = "disabled"; | |
152 | + }; | |
153 | + | |
154 | + mdio@27520 { | |
155 | + tbi3: tbi-phy@11 { | |
156 | + reg = <0x11>; | |
157 | + device_type = "tbi-phy"; | |
158 | + }; | |
159 | + }; | |
160 | + | |
161 | + crypto@30000 { | |
162 | + status = "disabled"; | |
163 | + }; | |
164 | +}; | |
165 | + | |
166 | +/include/ "fsl/mpc8548si-post.dtsi" |
arch/powerpc/boot/dts/sbc8548-altflash.dts
1 | +/* | |
2 | + * SBC8548 Device Tree Source | |
3 | + * | |
4 | + * Configured for booting off the alternate (64MB SODIMM) flash. | |
5 | + * Requires switching JP12 jumpers and changing SW2.8 setting. | |
6 | + * | |
7 | + * Copyright 2013 Wind River Systems Inc. | |
8 | + * | |
9 | + * Paul Gortmaker (see MAINTAINERS for contact information) | |
10 | + * | |
11 | + * This program is free software; you can redistribute it and/or modify it | |
12 | + * under the terms of the GNU General Public License as published by the | |
13 | + * Free Software Foundation; either version 2 of the License, or (at your | |
14 | + * option) any later version. | |
15 | + */ | |
16 | + | |
17 | + | |
18 | +/dts-v1/; | |
19 | + | |
20 | +/include/ "sbc8548-pre.dtsi" | |
21 | + | |
22 | +/{ | |
23 | + localbus@e0000000 { | |
24 | + #address-cells = <2>; | |
25 | + #size-cells = <1>; | |
26 | + compatible = "simple-bus"; | |
27 | + reg = <0xe0000000 0x5000>; | |
28 | + interrupt-parent = <&mpic>; | |
29 | + | |
30 | + ranges = <0x0 0x0 0xfc000000 0x04000000 /*64MB Flash*/ | |
31 | + 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/ | |
32 | + 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/ | |
33 | + 0x5 0x0 0xf8000000 0x00b10000 /* EPLD */ | |
34 | + 0x6 0x0 0xef800000 0x00800000>; /*8MB Flash*/ | |
35 | + | |
36 | + flash@0,0 { | |
37 | + #address-cells = <1>; | |
38 | + #size-cells = <1>; | |
39 | + reg = <0x0 0x0 0x04000000>; | |
40 | + compatible = "intel,JS28F128", "cfi-flash"; | |
41 | + bank-width = <4>; | |
42 | + device-width = <1>; | |
43 | + partition@0x0 { | |
44 | + label = "space"; | |
45 | + /* FC000000 -> FFEFFFFF */ | |
46 | + reg = <0x00000000 0x03f00000>; | |
47 | + }; | |
48 | + partition@0x03f00000 { | |
49 | + label = "bootloader"; | |
50 | + /* FFF00000 -> FFFFFFFF */ | |
51 | + reg = <0x03f00000 0x00100000>; | |
52 | + read-only; | |
53 | + }; | |
54 | + }; | |
55 | + | |
56 | + | |
57 | + epld@5,0 { | |
58 | + compatible = "wrs,epld-localbus"; | |
59 | + #address-cells = <2>; | |
60 | + #size-cells = <1>; | |
61 | + reg = <0x5 0x0 0x00b10000>; | |
62 | + ranges = < | |
63 | + 0x0 0x0 0x5 0x000000 0x1fff /* LED */ | |
64 | + 0x1 0x0 0x5 0x100000 0x1fff /* Switches */ | |
65 | + 0x3 0x0 0x5 0x300000 0x1fff /* HW Rev. */ | |
66 | + 0xb 0x0 0x5 0xb00000 0x1fff /* EEPROM */ | |
67 | + >; | |
68 | + | |
69 | + led@0,0 { | |
70 | + compatible = "led"; | |
71 | + reg = <0x0 0x0 0x1fff>; | |
72 | + }; | |
73 | + | |
74 | + switches@1,0 { | |
75 | + compatible = "switches"; | |
76 | + reg = <0x1 0x0 0x1fff>; | |
77 | + }; | |
78 | + | |
79 | + hw-rev@3,0 { | |
80 | + compatible = "hw-rev"; | |
81 | + reg = <0x3 0x0 0x1fff>; | |
82 | + }; | |
83 | + | |
84 | + eeprom@b,0 { | |
85 | + compatible = "eeprom"; | |
86 | + reg = <0xb 0 0x1fff>; | |
87 | + }; | |
88 | + | |
89 | + }; | |
90 | + | |
91 | + alt-flash@6,0 { | |
92 | + #address-cells = <1>; | |
93 | + #size-cells = <1>; | |
94 | + compatible = "intel,JS28F640", "cfi-flash"; | |
95 | + reg = <0x6 0x0 0x800000>; | |
96 | + bank-width = <1>; | |
97 | + device-width = <1>; | |
98 | + partition@0x0 { | |
99 | + label = "space"; | |
100 | + /* EF800000 -> EFF9FFFF */ | |
101 | + reg = <0x00000000 0x007a0000>; | |
102 | + }; | |
103 | + partition@0x7a0000 { | |
104 | + label = "bootloader"; | |
105 | + /* EFFA0000 -> EFFFFFFF */ | |
106 | + reg = <0x007a0000 0x00060000>; | |
107 | + read-only; | |
108 | + }; | |
109 | + }; | |
110 | + | |
111 | + | |
112 | + }; | |
113 | +}; | |
114 | + | |
115 | +/include/ "sbc8548-post.dtsi" |
arch/powerpc/boot/dts/sbc8548-post.dtsi
1 | +/* | |
2 | + * SBC8548 Device Tree Source | |
3 | + * | |
4 | + * Copyright 2007 Wind River Systems Inc. | |
5 | + * | |
6 | + * Paul Gortmaker (see MAINTAINERS for contact information) | |
7 | + * | |
8 | + * This program is free software; you can redistribute it and/or modify it | |
9 | + * under the terms of the GNU General Public License as published by the | |
10 | + * Free Software Foundation; either version 2 of the License, or (at your | |
11 | + * option) any later version. | |
12 | + */ | |
13 | + | |
14 | +/{ | |
15 | + soc8548@e0000000 { | |
16 | + #address-cells = <1>; | |
17 | + #size-cells = <1>; | |
18 | + device_type = "soc"; | |
19 | + ranges = <0x00000000 0xe0000000 0x00100000>; | |
20 | + bus-frequency = <0>; | |
21 | + compatible = "simple-bus"; | |
22 | + | |
23 | + ecm-law@0 { | |
24 | + compatible = "fsl,ecm-law"; | |
25 | + reg = <0x0 0x1000>; | |
26 | + fsl,num-laws = <10>; | |
27 | + }; | |
28 | + | |
29 | + ecm@1000 { | |
30 | + compatible = "fsl,mpc8548-ecm", "fsl,ecm"; | |
31 | + reg = <0x1000 0x1000>; | |
32 | + interrupts = <17 2>; | |
33 | + interrupt-parent = <&mpic>; | |
34 | + }; | |
35 | + | |
36 | + memory-controller@2000 { | |
37 | + compatible = "fsl,mpc8548-memory-controller"; | |
38 | + reg = <0x2000 0x1000>; | |
39 | + interrupt-parent = <&mpic>; | |
40 | + interrupts = <0x12 0x2>; | |
41 | + }; | |
42 | + | |
43 | + L2: l2-cache-controller@20000 { | |
44 | + compatible = "fsl,mpc8548-l2-cache-controller"; | |
45 | + reg = <0x20000 0x1000>; | |
46 | + cache-line-size = <0x20>; // 32 bytes | |
47 | + cache-size = <0x80000>; // L2, 512K | |
48 | + interrupt-parent = <&mpic>; | |
49 | + interrupts = <0x10 0x2>; | |
50 | + }; | |
51 | + | |
52 | + i2c@3000 { | |
53 | + #address-cells = <1>; | |
54 | + #size-cells = <0>; | |
55 | + cell-index = <0>; | |
56 | + compatible = "fsl-i2c"; | |
57 | + reg = <0x3000 0x100>; | |
58 | + interrupts = <0x2b 0x2>; | |
59 | + interrupt-parent = <&mpic>; | |
60 | + dfsrr; | |
61 | + }; | |
62 | + | |
63 | + i2c@3100 { | |
64 | + #address-cells = <1>; | |
65 | + #size-cells = <0>; | |
66 | + cell-index = <1>; | |
67 | + compatible = "fsl-i2c"; | |
68 | + reg = <0x3100 0x100>; | |
69 | + interrupts = <0x2b 0x2>; | |
70 | + interrupt-parent = <&mpic>; | |
71 | + dfsrr; | |
72 | + }; | |
73 | + | |
74 | + dma@21300 { | |
75 | + #address-cells = <1>; | |
76 | + #size-cells = <1>; | |
77 | + compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; | |
78 | + reg = <0x21300 0x4>; | |
79 | + ranges = <0x0 0x21100 0x200>; | |
80 | + cell-index = <0>; | |
81 | + dma-channel@0 { | |
82 | + compatible = "fsl,mpc8548-dma-channel", | |
83 | + "fsl,eloplus-dma-channel"; | |
84 | + reg = <0x0 0x80>; | |
85 | + cell-index = <0>; | |
86 | + interrupt-parent = <&mpic>; | |
87 | + interrupts = <20 2>; | |
88 | + }; | |
89 | + dma-channel@80 { | |
90 | + compatible = "fsl,mpc8548-dma-channel", | |
91 | + "fsl,eloplus-dma-channel"; | |
92 | + reg = <0x80 0x80>; | |
93 | + cell-index = <1>; | |
94 | + interrupt-parent = <&mpic>; | |
95 | + interrupts = <21 2>; | |
96 | + }; | |
97 | + dma-channel@100 { | |
98 | + compatible = "fsl,mpc8548-dma-channel", | |
99 | + "fsl,eloplus-dma-channel"; | |
100 | + reg = <0x100 0x80>; | |
101 | + cell-index = <2>; | |
102 | + interrupt-parent = <&mpic>; | |
103 | + interrupts = <22 2>; | |
104 | + }; | |
105 | + dma-channel@180 { | |
106 | + compatible = "fsl,mpc8548-dma-channel", | |
107 | + "fsl,eloplus-dma-channel"; | |
108 | + reg = <0x180 0x80>; | |
109 | + cell-index = <3>; | |
110 | + interrupt-parent = <&mpic>; | |
111 | + interrupts = <23 2>; | |
112 | + }; | |
113 | + }; | |
114 | + | |
115 | + enet0: ethernet@24000 { | |
116 | + #address-cells = <1>; | |
117 | + #size-cells = <1>; | |
118 | + cell-index = <0>; | |
119 | + device_type = "network"; | |
120 | + model = "eTSEC"; | |
121 | + compatible = "gianfar"; | |
122 | + reg = <0x24000 0x1000>; | |
123 | + ranges = <0x0 0x24000 0x1000>; | |
124 | + local-mac-address = [ 00 00 00 00 00 00 ]; | |
125 | + interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>; | |
126 | + interrupt-parent = <&mpic>; | |
127 | + tbi-handle = <&tbi0>; | |
128 | + phy-handle = <&phy0>; | |
129 | + | |
130 | + mdio@520 { | |
131 | + #address-cells = <1>; | |
132 | + #size-cells = <0>; | |
133 | + compatible = "fsl,gianfar-mdio"; | |
134 | + reg = <0x520 0x20>; | |
135 | + | |
136 | + phy0: ethernet-phy@19 { | |
137 | + interrupt-parent = <&mpic>; | |
138 | + interrupts = <0x6 0x1>; | |
139 | + reg = <0x19>; | |
140 | + device_type = "ethernet-phy"; | |
141 | + }; | |
142 | + phy1: ethernet-phy@1a { | |
143 | + interrupt-parent = <&mpic>; | |
144 | + interrupts = <0x7 0x1>; | |
145 | + reg = <0x1a>; | |
146 | + device_type = "ethernet-phy"; | |
147 | + }; | |
148 | + tbi0: tbi-phy@11 { | |
149 | + reg = <0x11>; | |
150 | + device_type = "tbi-phy"; | |
151 | + }; | |
152 | + }; | |
153 | + }; | |
154 | + | |
155 | + enet1: ethernet@25000 { | |
156 | + #address-cells = <1>; | |
157 | + #size-cells = <1>; | |
158 | + cell-index = <1>; | |
159 | + device_type = "network"; | |
160 | + model = "eTSEC"; | |
161 | + compatible = "gianfar"; | |
162 | + reg = <0x25000 0x1000>; | |
163 | + ranges = <0x0 0x25000 0x1000>; | |
164 | + local-mac-address = [ 00 00 00 00 00 00 ]; | |
165 | + interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>; | |
166 | + interrupt-parent = <&mpic>; | |
167 | + tbi-handle = <&tbi1>; | |
168 | + phy-handle = <&phy1>; | |
169 | + | |
170 | + mdio@520 { | |
171 | + #address-cells = <1>; | |
172 | + #size-cells = <0>; | |
173 | + compatible = "fsl,gianfar-tbi"; | |
174 | + reg = <0x520 0x20>; | |
175 | + | |
176 | + tbi1: tbi-phy@11 { | |
177 | + reg = <0x11>; | |
178 | + device_type = "tbi-phy"; | |
179 | + }; | |
180 | + }; | |
181 | + }; | |
182 | + | |
183 | + serial0: serial@4500 { | |
184 | + cell-index = <0>; | |
185 | + device_type = "serial"; | |
186 | + compatible = "fsl,ns16550", "ns16550"; | |
187 | + reg = <0x4500 0x100>; // reg base, size | |
188 | + clock-frequency = <0>; // should we fill in in uboot? | |
189 | + interrupts = <0x2a 0x2>; | |
190 | + interrupt-parent = <&mpic>; | |
191 | + }; | |
192 | + | |
193 | + serial1: serial@4600 { | |
194 | + cell-index = <1>; | |
195 | + device_type = "serial"; | |
196 | + compatible = "fsl,ns16550", "ns16550"; | |
197 | + reg = <0x4600 0x100>; // reg base, size | |
198 | + clock-frequency = <0>; // should we fill in in uboot? | |
199 | + interrupts = <0x2a 0x2>; | |
200 | + interrupt-parent = <&mpic>; | |
201 | + }; | |
202 | + | |
203 | + global-utilities@e0000 { //global utilities reg | |
204 | + compatible = "fsl,mpc8548-guts"; | |
205 | + reg = <0xe0000 0x1000>; | |
206 | + fsl,has-rstcr; | |
207 | + }; | |
208 | + | |
209 | + crypto@30000 { | |
210 | + compatible = "fsl,sec2.1", "fsl,sec2.0"; | |
211 | + reg = <0x30000 0x10000>; | |
212 | + interrupts = <45 2>; | |
213 | + interrupt-parent = <&mpic>; | |
214 | + fsl,num-channels = <4>; | |
215 | + fsl,channel-fifo-len = <24>; | |
216 | + fsl,exec-units-mask = <0xfe>; | |
217 | + fsl,descriptor-types-mask = <0x12b0ebf>; | |
218 | + }; | |
219 | + | |
220 | + mpic: pic@40000 { | |
221 | + interrupt-controller; | |
222 | + #address-cells = <0>; | |
223 | + #interrupt-cells = <2>; | |
224 | + reg = <0x40000 0x40000>; | |
225 | + compatible = "chrp,open-pic"; | |
226 | + device_type = "open-pic"; | |
227 | + }; | |
228 | + }; | |
229 | + | |
230 | + pci0: pci@e0008000 { | |
231 | + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | |
232 | + interrupt-map = < | |
233 | + /* IDSEL 0x01 (PCI-X slot) @66MHz */ | |
234 | + 0x0800 0x0 0x0 0x1 &mpic 0x2 0x1 | |
235 | + 0x0800 0x0 0x0 0x2 &mpic 0x3 0x1 | |
236 | + 0x0800 0x0 0x0 0x3 &mpic 0x4 0x1 | |
237 | + 0x0800 0x0 0x0 0x4 &mpic 0x1 0x1 | |
238 | + | |
239 | + /* IDSEL 0x11 (PCI, 3.3V 32bit) @33MHz */ | |
240 | + 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 | |
241 | + 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 | |
242 | + 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 | |
243 | + 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1>; | |
244 | + | |
245 | + interrupt-parent = <&mpic>; | |
246 | + interrupts = <0x18 0x2>; | |
247 | + bus-range = <0 0>; | |
248 | + ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000 | |
249 | + 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>; | |
250 | + clock-frequency = <66000000>; | |
251 | + #interrupt-cells = <1>; | |
252 | + #size-cells = <2>; | |
253 | + #address-cells = <3>; | |
254 | + reg = <0xe0008000 0x1000>; | |
255 | + compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; | |
256 | + device_type = "pci"; | |
257 | + }; | |
258 | + | |
259 | + pci1: pcie@e000a000 { | |
260 | + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | |
261 | + interrupt-map = < | |
262 | + | |
263 | + /* IDSEL 0x0 (PEX) */ | |
264 | + 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1 | |
265 | + 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1 | |
266 | + 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1 | |
267 | + 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>; | |
268 | + | |
269 | + interrupt-parent = <&mpic>; | |
270 | + interrupts = <0x1a 0x2>; | |
271 | + bus-range = <0x0 0xff>; | |
272 | + ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 | |
273 | + 0x01000000 0x0 0x00000000 0xe2800000 0x0 0x08000000>; | |
274 | + clock-frequency = <33000000>; | |
275 | + #interrupt-cells = <1>; | |
276 | + #size-cells = <2>; | |
277 | + #address-cells = <3>; | |
278 | + reg = <0xe000a000 0x1000>; | |
279 | + compatible = "fsl,mpc8548-pcie"; | |
280 | + device_type = "pci"; | |
281 | + pcie@0 { | |
282 | + reg = <0x0 0x0 0x0 0x0 0x0>; | |
283 | + #size-cells = <2>; | |
284 | + #address-cells = <3>; | |
285 | + device_type = "pci"; | |
286 | + ranges = <0x02000000 0x0 0xa0000000 | |
287 | + 0x02000000 0x0 0xa0000000 | |
288 | + 0x0 0x10000000 | |
289 | + | |
290 | + 0x01000000 0x0 0x00000000 | |
291 | + 0x01000000 0x0 0x00000000 | |
292 | + 0x0 0x00800000>; | |
293 | + }; | |
294 | + }; | |
295 | +}; |
arch/powerpc/boot/dts/sbc8548-pre.dtsi
1 | +/* | |
2 | + * SBC8548 Device Tree Source | |
3 | + * | |
4 | + * Copyright 2007 Wind River Systems Inc. | |
5 | + * | |
6 | + * Paul Gortmaker (see MAINTAINERS for contact information) | |
7 | + * | |
8 | + * This program is free software; you can redistribute it and/or modify it | |
9 | + * under the terms of the GNU General Public License as published by the | |
10 | + * Free Software Foundation; either version 2 of the License, or (at your | |
11 | + * option) any later version. | |
12 | + */ | |
13 | + | |
14 | +/{ | |
15 | + model = "SBC8548"; | |
16 | + compatible = "SBC8548"; | |
17 | + #address-cells = <1>; | |
18 | + #size-cells = <1>; | |
19 | + | |
20 | + aliases { | |
21 | + ethernet0 = &enet0; | |
22 | + ethernet1 = &enet1; | |
23 | + serial0 = &serial0; | |
24 | + serial1 = &serial1; | |
25 | + pci0 = &pci0; | |
26 | + pci1 = &pci1; | |
27 | + }; | |
28 | + | |
29 | + cpus { | |
30 | + #address-cells = <1>; | |
31 | + #size-cells = <0>; | |
32 | + | |
33 | + PowerPC,8548@0 { | |
34 | + device_type = "cpu"; | |
35 | + reg = <0>; | |
36 | + d-cache-line-size = <0x20>; // 32 bytes | |
37 | + i-cache-line-size = <0x20>; // 32 bytes | |
38 | + d-cache-size = <0x8000>; // L1, 32K | |
39 | + i-cache-size = <0x8000>; // L1, 32K | |
40 | + timebase-frequency = <0>; // From uboot | |
41 | + bus-frequency = <0>; | |
42 | + clock-frequency = <0>; | |
43 | + next-level-cache = <&L2>; | |
44 | + }; | |
45 | + }; | |
46 | + | |
47 | + memory { | |
48 | + device_type = "memory"; | |
49 | + reg = <0x00000000 0x10000000>; | |
50 | + }; | |
51 | + | |
52 | +}; |
arch/powerpc/boot/dts/sbc8548.dts
... | ... | @@ -14,44 +14,9 @@ |
14 | 14 | |
15 | 15 | /dts-v1/; |
16 | 16 | |
17 | -/ { | |
18 | - model = "SBC8548"; | |
19 | - compatible = "SBC8548"; | |
20 | - #address-cells = <1>; | |
21 | - #size-cells = <1>; | |
17 | +/include/ "sbc8548-pre.dtsi" | |
22 | 18 | |
23 | - aliases { | |
24 | - ethernet0 = &enet0; | |
25 | - ethernet1 = &enet1; | |
26 | - serial0 = &serial0; | |
27 | - serial1 = &serial1; | |
28 | - pci0 = &pci0; | |
29 | - pci1 = &pci1; | |
30 | - }; | |
31 | - | |
32 | - cpus { | |
33 | - #address-cells = <1>; | |
34 | - #size-cells = <0>; | |
35 | - | |
36 | - PowerPC,8548@0 { | |
37 | - device_type = "cpu"; | |
38 | - reg = <0>; | |
39 | - d-cache-line-size = <0x20>; // 32 bytes | |
40 | - i-cache-line-size = <0x20>; // 32 bytes | |
41 | - d-cache-size = <0x8000>; // L1, 32K | |
42 | - i-cache-size = <0x8000>; // L1, 32K | |
43 | - timebase-frequency = <0>; // From uboot | |
44 | - bus-frequency = <0>; | |
45 | - clock-frequency = <0>; | |
46 | - next-level-cache = <&L2>; | |
47 | - }; | |
48 | - }; | |
49 | - | |
50 | - memory { | |
51 | - device_type = "memory"; | |
52 | - reg = <0x00000000 0x10000000>; | |
53 | - }; | |
54 | - | |
19 | +/{ | |
55 | 20 | localbus@e0000000 { |
56 | 21 | #address-cells = <2>; |
57 | 22 | #size-cells = <1>; |
58 | 23 | |
59 | 24 | |
60 | 25 | |
61 | 26 | |
... | ... | @@ -63,23 +28,25 @@ |
63 | 28 | 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/ |
64 | 29 | 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/ |
65 | 30 | 0x5 0x0 0xf8000000 0x00b10000 /* EPLD */ |
66 | - 0x6 0x0 0xfb800000 0x04000000>; /*64MB Flash*/ | |
31 | + 0x6 0x0 0xec000000 0x04000000>; /*64MB Flash*/ | |
67 | 32 | |
68 | 33 | |
69 | 34 | flash@0,0 { |
70 | 35 | #address-cells = <1>; |
71 | 36 | #size-cells = <1>; |
72 | - compatible = "cfi-flash"; | |
37 | + compatible = "intel,JS28F640", "cfi-flash"; | |
73 | 38 | reg = <0x0 0x0 0x800000>; |
74 | 39 | bank-width = <1>; |
75 | 40 | device-width = <1>; |
76 | 41 | partition@0x0 { |
77 | 42 | label = "space"; |
78 | - reg = <0x00000000 0x00100000>; | |
43 | + /* FF800000 -> FFF9FFFF */ | |
44 | + reg = <0x00000000 0x007a0000>; | |
79 | 45 | }; |
80 | - partition@0x100000 { | |
46 | + partition@0x7a0000 { | |
81 | 47 | label = "bootloader"; |
82 | - reg = <0x00100000 0x00700000>; | |
48 | + /* FFFA0000 -> FFFFFFFF */ | |
49 | + reg = <0x007a0000 0x00060000>; | |
83 | 50 | read-only; |
84 | 51 | }; |
85 | 52 | }; |
86 | 53 | |
87 | 54 | |
88 | 55 | |
89 | 56 | |
90 | 57 | |
... | ... | @@ -122,308 +89,23 @@ |
122 | 89 | #address-cells = <1>; |
123 | 90 | #size-cells = <1>; |
124 | 91 | reg = <0x6 0x0 0x04000000>; |
125 | - compatible = "cfi-flash"; | |
92 | + compatible = "intel,JS28F128", "cfi-flash"; | |
126 | 93 | bank-width = <4>; |
127 | 94 | device-width = <1>; |
128 | 95 | partition@0x0 { |
96 | + label = "space"; | |
97 | + /* EC000000 -> EFEFFFFF */ | |
98 | + reg = <0x00000000 0x03f00000>; | |
99 | + }; | |
100 | + partition@0x03f00000 { | |
129 | 101 | label = "bootloader"; |
130 | - reg = <0x00000000 0x00100000>; | |
102 | + /* EFF00000 -> EFFFFFFF */ | |
103 | + reg = <0x03f00000 0x00100000>; | |
131 | 104 | read-only; |
132 | 105 | }; |
133 | - partition@0x00100000 { | |
134 | - label = "file-system"; | |
135 | - reg = <0x00100000 0x01f00000>; | |
136 | - }; | |
137 | - partition@0x02000000 { | |
138 | - label = "boot-config"; | |
139 | - reg = <0x02000000 0x00100000>; | |
140 | - }; | |
141 | - partition@0x02100000 { | |
142 | - label = "space"; | |
143 | - reg = <0x02100000 0x01f00000>; | |
144 | - }; | |
145 | 106 | }; |
146 | 107 | }; |
147 | - | |
148 | - soc8548@e0000000 { | |
149 | - #address-cells = <1>; | |
150 | - #size-cells = <1>; | |
151 | - device_type = "soc"; | |
152 | - ranges = <0x00000000 0xe0000000 0x00100000>; | |
153 | - bus-frequency = <0>; | |
154 | - compatible = "simple-bus"; | |
155 | - | |
156 | - ecm-law@0 { | |
157 | - compatible = "fsl,ecm-law"; | |
158 | - reg = <0x0 0x1000>; | |
159 | - fsl,num-laws = <10>; | |
160 | - }; | |
161 | - | |
162 | - ecm@1000 { | |
163 | - compatible = "fsl,mpc8548-ecm", "fsl,ecm"; | |
164 | - reg = <0x1000 0x1000>; | |
165 | - interrupts = <17 2>; | |
166 | - interrupt-parent = <&mpic>; | |
167 | - }; | |
168 | - | |
169 | - memory-controller@2000 { | |
170 | - compatible = "fsl,mpc8548-memory-controller"; | |
171 | - reg = <0x2000 0x1000>; | |
172 | - interrupt-parent = <&mpic>; | |
173 | - interrupts = <0x12 0x2>; | |
174 | - }; | |
175 | - | |
176 | - L2: l2-cache-controller@20000 { | |
177 | - compatible = "fsl,mpc8548-l2-cache-controller"; | |
178 | - reg = <0x20000 0x1000>; | |
179 | - cache-line-size = <0x20>; // 32 bytes | |
180 | - cache-size = <0x80000>; // L2, 512K | |
181 | - interrupt-parent = <&mpic>; | |
182 | - interrupts = <0x10 0x2>; | |
183 | - }; | |
184 | - | |
185 | - i2c@3000 { | |
186 | - #address-cells = <1>; | |
187 | - #size-cells = <0>; | |
188 | - cell-index = <0>; | |
189 | - compatible = "fsl-i2c"; | |
190 | - reg = <0x3000 0x100>; | |
191 | - interrupts = <0x2b 0x2>; | |
192 | - interrupt-parent = <&mpic>; | |
193 | - dfsrr; | |
194 | - }; | |
195 | - | |
196 | - i2c@3100 { | |
197 | - #address-cells = <1>; | |
198 | - #size-cells = <0>; | |
199 | - cell-index = <1>; | |
200 | - compatible = "fsl-i2c"; | |
201 | - reg = <0x3100 0x100>; | |
202 | - interrupts = <0x2b 0x2>; | |
203 | - interrupt-parent = <&mpic>; | |
204 | - dfsrr; | |
205 | - }; | |
206 | - | |
207 | - dma@21300 { | |
208 | - #address-cells = <1>; | |
209 | - #size-cells = <1>; | |
210 | - compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; | |
211 | - reg = <0x21300 0x4>; | |
212 | - ranges = <0x0 0x21100 0x200>; | |
213 | - cell-index = <0>; | |
214 | - dma-channel@0 { | |
215 | - compatible = "fsl,mpc8548-dma-channel", | |
216 | - "fsl,eloplus-dma-channel"; | |
217 | - reg = <0x0 0x80>; | |
218 | - cell-index = <0>; | |
219 | - interrupt-parent = <&mpic>; | |
220 | - interrupts = <20 2>; | |
221 | - }; | |
222 | - dma-channel@80 { | |
223 | - compatible = "fsl,mpc8548-dma-channel", | |
224 | - "fsl,eloplus-dma-channel"; | |
225 | - reg = <0x80 0x80>; | |
226 | - cell-index = <1>; | |
227 | - interrupt-parent = <&mpic>; | |
228 | - interrupts = <21 2>; | |
229 | - }; | |
230 | - dma-channel@100 { | |
231 | - compatible = "fsl,mpc8548-dma-channel", | |
232 | - "fsl,eloplus-dma-channel"; | |
233 | - reg = <0x100 0x80>; | |
234 | - cell-index = <2>; | |
235 | - interrupt-parent = <&mpic>; | |
236 | - interrupts = <22 2>; | |
237 | - }; | |
238 | - dma-channel@180 { | |
239 | - compatible = "fsl,mpc8548-dma-channel", | |
240 | - "fsl,eloplus-dma-channel"; | |
241 | - reg = <0x180 0x80>; | |
242 | - cell-index = <3>; | |
243 | - interrupt-parent = <&mpic>; | |
244 | - interrupts = <23 2>; | |
245 | - }; | |
246 | - }; | |
247 | - | |
248 | - enet0: ethernet@24000 { | |
249 | - #address-cells = <1>; | |
250 | - #size-cells = <1>; | |
251 | - cell-index = <0>; | |
252 | - device_type = "network"; | |
253 | - model = "eTSEC"; | |
254 | - compatible = "gianfar"; | |
255 | - reg = <0x24000 0x1000>; | |
256 | - ranges = <0x0 0x24000 0x1000>; | |
257 | - local-mac-address = [ 00 00 00 00 00 00 ]; | |
258 | - interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>; | |
259 | - interrupt-parent = <&mpic>; | |
260 | - tbi-handle = <&tbi0>; | |
261 | - phy-handle = <&phy0>; | |
262 | - | |
263 | - mdio@520 { | |
264 | - #address-cells = <1>; | |
265 | - #size-cells = <0>; | |
266 | - compatible = "fsl,gianfar-mdio"; | |
267 | - reg = <0x520 0x20>; | |
268 | - | |
269 | - phy0: ethernet-phy@19 { | |
270 | - interrupt-parent = <&mpic>; | |
271 | - interrupts = <0x6 0x1>; | |
272 | - reg = <0x19>; | |
273 | - device_type = "ethernet-phy"; | |
274 | - }; | |
275 | - phy1: ethernet-phy@1a { | |
276 | - interrupt-parent = <&mpic>; | |
277 | - interrupts = <0x7 0x1>; | |
278 | - reg = <0x1a>; | |
279 | - device_type = "ethernet-phy"; | |
280 | - }; | |
281 | - tbi0: tbi-phy@11 { | |
282 | - reg = <0x11>; | |
283 | - device_type = "tbi-phy"; | |
284 | - }; | |
285 | - }; | |
286 | - }; | |
287 | - | |
288 | - enet1: ethernet@25000 { | |
289 | - #address-cells = <1>; | |
290 | - #size-cells = <1>; | |
291 | - cell-index = <1>; | |
292 | - device_type = "network"; | |
293 | - model = "eTSEC"; | |
294 | - compatible = "gianfar"; | |
295 | - reg = <0x25000 0x1000>; | |
296 | - ranges = <0x0 0x25000 0x1000>; | |
297 | - local-mac-address = [ 00 00 00 00 00 00 ]; | |
298 | - interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>; | |
299 | - interrupt-parent = <&mpic>; | |
300 | - tbi-handle = <&tbi1>; | |
301 | - phy-handle = <&phy1>; | |
302 | - | |
303 | - mdio@520 { | |
304 | - #address-cells = <1>; | |
305 | - #size-cells = <0>; | |
306 | - compatible = "fsl,gianfar-tbi"; | |
307 | - reg = <0x520 0x20>; | |
308 | - | |
309 | - tbi1: tbi-phy@11 { | |
310 | - reg = <0x11>; | |
311 | - device_type = "tbi-phy"; | |
312 | - }; | |
313 | - }; | |
314 | - }; | |
315 | - | |
316 | - serial0: serial@4500 { | |
317 | - cell-index = <0>; | |
318 | - device_type = "serial"; | |
319 | - compatible = "fsl,ns16550", "ns16550"; | |
320 | - reg = <0x4500 0x100>; // reg base, size | |
321 | - clock-frequency = <0>; // should we fill in in uboot? | |
322 | - interrupts = <0x2a 0x2>; | |
323 | - interrupt-parent = <&mpic>; | |
324 | - }; | |
325 | - | |
326 | - serial1: serial@4600 { | |
327 | - cell-index = <1>; | |
328 | - device_type = "serial"; | |
329 | - compatible = "fsl,ns16550", "ns16550"; | |
330 | - reg = <0x4600 0x100>; // reg base, size | |
331 | - clock-frequency = <0>; // should we fill in in uboot? | |
332 | - interrupts = <0x2a 0x2>; | |
333 | - interrupt-parent = <&mpic>; | |
334 | - }; | |
335 | - | |
336 | - global-utilities@e0000 { //global utilities reg | |
337 | - compatible = "fsl,mpc8548-guts"; | |
338 | - reg = <0xe0000 0x1000>; | |
339 | - fsl,has-rstcr; | |
340 | - }; | |
341 | - | |
342 | - crypto@30000 { | |
343 | - compatible = "fsl,sec2.1", "fsl,sec2.0"; | |
344 | - reg = <0x30000 0x10000>; | |
345 | - interrupts = <45 2>; | |
346 | - interrupt-parent = <&mpic>; | |
347 | - fsl,num-channels = <4>; | |
348 | - fsl,channel-fifo-len = <24>; | |
349 | - fsl,exec-units-mask = <0xfe>; | |
350 | - fsl,descriptor-types-mask = <0x12b0ebf>; | |
351 | - }; | |
352 | - | |
353 | - mpic: pic@40000 { | |
354 | - interrupt-controller; | |
355 | - #address-cells = <0>; | |
356 | - #interrupt-cells = <2>; | |
357 | - reg = <0x40000 0x40000>; | |
358 | - compatible = "chrp,open-pic"; | |
359 | - device_type = "open-pic"; | |
360 | - }; | |
361 | - }; | |
362 | - | |
363 | - pci0: pci@e0008000 { | |
364 | - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | |
365 | - interrupt-map = < | |
366 | - /* IDSEL 0x01 (PCI-X slot) @66MHz */ | |
367 | - 0x0800 0x0 0x0 0x1 &mpic 0x2 0x1 | |
368 | - 0x0800 0x0 0x0 0x2 &mpic 0x3 0x1 | |
369 | - 0x0800 0x0 0x0 0x3 &mpic 0x4 0x1 | |
370 | - 0x0800 0x0 0x0 0x4 &mpic 0x1 0x1 | |
371 | - | |
372 | - /* IDSEL 0x11 (PCI, 3.3V 32bit) @33MHz */ | |
373 | - 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 | |
374 | - 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 | |
375 | - 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 | |
376 | - 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1>; | |
377 | - | |
378 | - interrupt-parent = <&mpic>; | |
379 | - interrupts = <0x18 0x2>; | |
380 | - bus-range = <0 0>; | |
381 | - ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000 | |
382 | - 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>; | |
383 | - clock-frequency = <66000000>; | |
384 | - #interrupt-cells = <1>; | |
385 | - #size-cells = <2>; | |
386 | - #address-cells = <3>; | |
387 | - reg = <0xe0008000 0x1000>; | |
388 | - compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; | |
389 | - device_type = "pci"; | |
390 | - }; | |
391 | - | |
392 | - pci1: pcie@e000a000 { | |
393 | - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | |
394 | - interrupt-map = < | |
395 | - | |
396 | - /* IDSEL 0x0 (PEX) */ | |
397 | - 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1 | |
398 | - 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1 | |
399 | - 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1 | |
400 | - 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>; | |
401 | - | |
402 | - interrupt-parent = <&mpic>; | |
403 | - interrupts = <0x1a 0x2>; | |
404 | - bus-range = <0x0 0xff>; | |
405 | - ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 | |
406 | - 0x01000000 0x0 0x00000000 0xe2800000 0x0 0x08000000>; | |
407 | - clock-frequency = <33000000>; | |
408 | - #interrupt-cells = <1>; | |
409 | - #size-cells = <2>; | |
410 | - #address-cells = <3>; | |
411 | - reg = <0xe000a000 0x1000>; | |
412 | - compatible = "fsl,mpc8548-pcie"; | |
413 | - device_type = "pci"; | |
414 | - pcie@0 { | |
415 | - reg = <0x0 0x0 0x0 0x0 0x0>; | |
416 | - #size-cells = <2>; | |
417 | - #address-cells = <3>; | |
418 | - device_type = "pci"; | |
419 | - ranges = <0x02000000 0x0 0xa0000000 | |
420 | - 0x02000000 0x0 0xa0000000 | |
421 | - 0x0 0x10000000 | |
422 | - | |
423 | - 0x01000000 0x0 0x00000000 | |
424 | - 0x01000000 0x0 0x00000000 | |
425 | - 0x0 0x00800000>; | |
426 | - }; | |
427 | - }; | |
428 | 108 | }; |
109 | + | |
110 | +/include/ "sbc8548-post.dtsi" |
arch/powerpc/configs/83xx/kmeter1_defconfig
... | ... | @@ -2,6 +2,8 @@ |
2 | 2 | # CONFIG_SWAP is not set |
3 | 3 | CONFIG_SYSVIPC=y |
4 | 4 | CONFIG_POSIX_MQUEUE=y |
5 | +CONFIG_NO_HZ=y | |
6 | +CONFIG_HIGH_RES_TIMERS=y | |
5 | 7 | CONFIG_LOG_BUF_SHIFT=14 |
6 | 8 | CONFIG_EXPERT=y |
7 | 9 | CONFIG_SLAB=y |
... | ... | @@ -16,8 +18,6 @@ |
16 | 18 | # CONFIG_PPC_PMAC is not set |
17 | 19 | CONFIG_PPC_83xx=y |
18 | 20 | CONFIG_KMETER1=y |
19 | -CONFIG_NO_HZ=y | |
20 | -CONFIG_HIGH_RES_TIMERS=y | |
21 | 21 | CONFIG_PREEMPT=y |
22 | 22 | # CONFIG_SECCOMP is not set |
23 | 23 | CONFIG_NET=y |
... | ... | @@ -45,7 +45,6 @@ |
45 | 45 | CONFIG_MTD_PHRAM=y |
46 | 46 | CONFIG_MTD_UBI=y |
47 | 47 | CONFIG_MTD_UBI_GLUEBI=y |
48 | -CONFIG_MTD_UBI_DEBUG=y | |
49 | 48 | CONFIG_PROC_DEVICETREE=y |
50 | 49 | CONFIG_NETDEVICES=y |
51 | 50 | CONFIG_DUMMY=y |
... | ... | @@ -76,6 +75,5 @@ |
76 | 75 | CONFIG_JFFS2_FS=y |
77 | 76 | CONFIG_UBIFS_FS=y |
78 | 77 | CONFIG_NFS_FS=y |
79 | -CONFIG_NFS_V3=y | |
80 | 78 | CONFIG_ROOT_NFS=y |
arch/powerpc/configs/85xx/ppa8548_defconfig
1 | +CONFIG_PPC_85xx=y | |
2 | +CONFIG_PPA8548=y | |
3 | +CONFIG_DTC=y | |
4 | +CONFIG_DEFAULT_UIMAGE=y | |
5 | +CONFIG_IKCONFIG=y | |
6 | +CONFIG_IKCONFIG_PROC=y | |
7 | +# CONFIG_PCI is not set | |
8 | +# CONFIG_USB_SUPPORT is not set | |
9 | +CONFIG_ADVANCED_OPTIONS=y | |
10 | +CONFIG_LOWMEM_SIZE_BOOL=y | |
11 | +CONFIG_LOWMEM_SIZE=0x40000000 | |
12 | +CONFIG_LOWMEM_CAM_NUM_BOOL=y | |
13 | +CONFIG_LOWMEM_CAM_NUM=4 | |
14 | +CONFIG_PAGE_OFFSET_BOOL=y | |
15 | +CONFIG_PAGE_OFFSET=0xb0000000 | |
16 | +CONFIG_KERNEL_START_BOOL=y | |
17 | +CONFIG_KERNEL_START=0xb0000000 | |
18 | +# CONFIG_PHYSICAL_START_BOOL is not set | |
19 | +CONFIG_PHYSICAL_START=0x00000000 | |
20 | +CONFIG_PHYSICAL_ALIGN=0x04000000 | |
21 | +CONFIG_TASK_SIZE_BOOL=y | |
22 | +CONFIG_TASK_SIZE=0xb0000000 | |
23 | + | |
24 | +CONFIG_FSL_LBC=y | |
25 | +CONFIG_FSL_DMA=y | |
26 | +CONFIG_FSL_RIO=y | |
27 | + | |
28 | +CONFIG_RAPIDIO=y | |
29 | +CONFIG_RAPIDIO_DMA_ENGINE=y | |
30 | +CONFIG_RAPIDIO_TSI57X=y | |
31 | +CONFIG_RAPIDIO_TSI568=y | |
32 | +CONFIG_RAPIDIO_CPS_XX=y | |
33 | +CONFIG_RAPIDIO_CPS_GEN2=y | |
34 | +CONFIG_SERIAL_8250=y | |
35 | +CONFIG_SERIAL_8250_CONSOLE=y | |
36 | +CONFIG_PROC_DEVICETREE=y | |
37 | + | |
38 | +CONFIG_MTD=y | |
39 | +CONFIG_MTD_BLKDEVS=y | |
40 | +CONFIG_MTD_BLOCK=y | |
41 | +CONFIG_MTD_CFI=y | |
42 | +CONFIG_MTD_CFI_AMDSTD=y | |
43 | +CONFIG_MTD_CFI_INTELEXT=y | |
44 | +CONFIG_MTD_CHAR=y | |
45 | +CONFIG_MTD_CMDLINE_PARTS=y | |
46 | +CONFIG_MTD_CONCAT=y | |
47 | +CONFIG_MTD_PARTITIONS=y | |
48 | +CONFIG_MTD_PHYSMAP_OF=y | |
49 | + | |
50 | +CONFIG_I2C=y | |
51 | +CONFIG_I2C_MPC=y | |
52 | +CONFIG_I2C_CHARDEV | |
53 | +CONFIG_RTC_CLASS=y | |
54 | +CONFIG_RTC_HCTOSYS=y | |
55 | +CONFIG_RTC_DRV_ISL1208=y | |
56 | + | |
57 | +CONFIG_NET=y | |
58 | +CONFIG_INET=y | |
59 | +CONFIG_IP_PNP=y | |
60 | +CONFIG_NETDEVICES=y | |
61 | +CONFIG_MII=y | |
62 | +CONFIG_GIANFAR=y | |
63 | +CONFIG_MARVELL_PHY=y | |
64 | +CONFIG_NFS_FS=y | |
65 | +CONFIG_ROOT_NFS=y |
arch/powerpc/configs/85xx/sbc8548_defconfig
... | ... | @@ -55,4 +55,23 @@ |
55 | 55 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set |
56 | 56 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
57 | 57 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
58 | +CONFIG_MTD=y | |
59 | +CONFIG_MTD_OF_PARTS=y | |
60 | +CONFIG_MTD_CHAR=y | |
61 | +CONFIG_MTD_BLKDEVS=y | |
62 | +CONFIG_MTD_BLOCK=y | |
63 | +CONFIG_MTD_CFI=y | |
64 | +CONFIG_MTD_GEN_PROBE=y | |
65 | +CONFIG_MTD_CFI_ADV_OPTIONS=y | |
66 | +CONFIG_MTD_CFI_NOSWAP=y | |
67 | +CONFIG_MTD_CFI_GEOMETRY=y | |
68 | +CONFIG_MTD_MAP_BANK_WIDTH_1=y | |
69 | +CONFIG_MTD_MAP_BANK_WIDTH_2=y | |
70 | +CONFIG_MTD_MAP_BANK_WIDTH_4=y | |
71 | +CONFIG_MTD_CFI_I1=y | |
72 | +CONFIG_MTD_CFI_I2=y | |
73 | +CONFIG_MTD_CFI_I4=y | |
74 | +CONFIG_MTD_CFI_INTELEXT=y | |
75 | +CONFIG_MTD_CFI_UTIL=y | |
76 | +CONFIG_MTD_PHYSMAP_OF=y |
arch/powerpc/platforms/512x/mpc512x_shared.c
... | ... | @@ -68,10 +68,6 @@ |
68 | 68 | bool in_use; |
69 | 69 | }; |
70 | 70 | |
71 | -void mpc512x_set_monitor_port(enum fsl_diu_monitor_port port) | |
72 | -{ | |
73 | -} | |
74 | - | |
75 | 71 | #define DIU_DIV_MASK 0x000000ff |
76 | 72 | void mpc512x_set_pixel_clock(unsigned int pixclock) |
77 | 73 | { |
... | ... | @@ -303,7 +299,6 @@ |
303 | 299 | } |
304 | 300 | } |
305 | 301 | |
306 | - diu_ops.set_monitor_port = mpc512x_set_monitor_port; | |
307 | 302 | diu_ops.set_pixel_clock = mpc512x_set_pixel_clock; |
308 | 303 | diu_ops.valid_monitor_port = mpc512x_valid_monitor_port; |
309 | 304 | diu_ops.release_bootmem = mpc512x_release_bootmem; |
arch/powerpc/platforms/82xx/km82xx.c
... | ... | @@ -18,11 +18,11 @@ |
18 | 18 | #include <linux/fsl_devices.h> |
19 | 19 | #include <linux/of_platform.h> |
20 | 20 | |
21 | -#include <asm/io.h> | |
21 | +#include <linux/io.h> | |
22 | 22 | #include <asm/cpm2.h> |
23 | 23 | #include <asm/udbg.h> |
24 | 24 | #include <asm/machdep.h> |
25 | -#include <asm/time.h> | |
25 | +#include <linux/time.h> | |
26 | 26 | #include <asm/mpc8260.h> |
27 | 27 | #include <asm/prom.h> |
28 | 28 | |
... | ... | @@ -36,7 +36,7 @@ |
36 | 36 | struct device_node *np = of_find_compatible_node(NULL, NULL, |
37 | 37 | "fsl,pq2-pic"); |
38 | 38 | if (!np) { |
39 | - printk(KERN_ERR "PIC init: can not find cpm-pic node\n"); | |
39 | + pr_err("PIC init: can not find cpm-pic node\n"); | |
40 | 40 | return; |
41 | 41 | } |
42 | 42 |
arch/powerpc/platforms/83xx/km83xx.c
... | ... | @@ -28,8 +28,8 @@ |
28 | 28 | #include <linux/of_device.h> |
29 | 29 | |
30 | 30 | #include <linux/atomic.h> |
31 | -#include <asm/time.h> | |
32 | -#include <asm/io.h> | |
31 | +#include <linux/time.h> | |
32 | +#include <linux/io.h> | |
33 | 33 | #include <asm/machdep.h> |
34 | 34 | #include <asm/ipic.h> |
35 | 35 | #include <asm/irq.h> |
... | ... | @@ -43,6 +43,82 @@ |
43 | 43 | #include "mpc83xx.h" |
44 | 44 | |
45 | 45 | #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ |
46 | + | |
47 | +static void quirk_mpc8360e_qe_enet10(void) | |
48 | +{ | |
49 | + /* | |
50 | + * handle mpc8360E Erratum QE_ENET10: | |
51 | + * RGMII AC values do not meet the specification | |
52 | + */ | |
53 | + uint svid = mfspr(SPRN_SVR); | |
54 | + struct device_node *np_par; | |
55 | + struct resource res; | |
56 | + void __iomem *base; | |
57 | + int ret; | |
58 | + | |
59 | + np_par = of_find_node_by_name(NULL, "par_io"); | |
60 | + if (np_par == NULL) { | |
61 | + pr_warn("%s couldn;t find par_io node\n", __func__); | |
62 | + return; | |
63 | + } | |
64 | + /* Map Parallel I/O ports registers */ | |
65 | + ret = of_address_to_resource(np_par, 0, &res); | |
66 | + if (ret) { | |
67 | + pr_warn("%s couldn;t map par_io registers\n", __func__); | |
68 | + return; | |
69 | + } | |
70 | + | |
71 | + base = ioremap(res.start, res.end - res.start + 1); | |
72 | + | |
73 | + /* | |
74 | + * set output delay adjustments to default values according | |
75 | + * table 5 in Errata Rev. 5, 9/2011: | |
76 | + * | |
77 | + * write 0b01 to UCC1 bits 18:19 | |
78 | + * write 0b01 to UCC2 option 1 bits 4:5 | |
79 | + * write 0b01 to UCC2 option 2 bits 16:17 | |
80 | + */ | |
81 | + clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000); | |
82 | + | |
83 | + /* | |
84 | + * set output delay adjustments to default values according | |
85 | + * table 3-13 in Reference Manual Rev.3 05/2010: | |
86 | + * | |
87 | + * write 0b01 to UCC2 option 2 bits 16:17 | |
88 | + * write 0b0101 to UCC1 bits 20:23 | |
89 | + * write 0b0101 to UCC2 option 1 bits 24:27 | |
90 | + */ | |
91 | + clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550); | |
92 | + | |
93 | + if (SVR_REV(svid) == 0x0021) { | |
94 | + /* | |
95 | + * UCC2 option 1: write 0b1010 to bits 24:27 | |
96 | + * at address IMMRBAR+0x14AC | |
97 | + */ | |
98 | + clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0); | |
99 | + } else if (SVR_REV(svid) == 0x0020) { | |
100 | + /* | |
101 | + * UCC1: write 0b11 to bits 18:19 | |
102 | + * at address IMMRBAR+0x14A8 | |
103 | + */ | |
104 | + setbits32((base + 0xa8), 0x00003000); | |
105 | + | |
106 | + /* | |
107 | + * UCC2 option 1: write 0b11 to bits 4:5 | |
108 | + * at address IMMRBAR+0x14A8 | |
109 | + */ | |
110 | + setbits32((base + 0xa8), 0x0c000000); | |
111 | + | |
112 | + /* | |
113 | + * UCC2 option 2: write 0b11 to bits 16:17 | |
114 | + * at address IMMRBAR+0x14AC | |
115 | + */ | |
116 | + setbits32((base + 0xac), 0x0000c000); | |
117 | + } | |
118 | + iounmap(base); | |
119 | + of_node_put(np_par); | |
120 | +} | |
121 | + | |
46 | 122 | /* ************************************************************************ |
47 | 123 | * |
48 | 124 | * Setup the architecture |
49 | 125 | |
50 | 126 | |
... | ... | @@ -72,84 +148,13 @@ |
72 | 148 | |
73 | 149 | for_each_node_by_name(np, "ucc") |
74 | 150 | par_io_of_config(np); |
75 | - } | |
76 | 151 | |
77 | - np = of_find_compatible_node(NULL, "network", "ucc_geth"); | |
78 | - if (np != NULL) { | |
79 | - /* | |
80 | - * handle mpc8360E Erratum QE_ENET10: | |
81 | - * RGMII AC values do not meet the specification | |
82 | - */ | |
83 | - uint svid = mfspr(SPRN_SVR); | |
84 | - struct device_node *np_par; | |
85 | - struct resource res; | |
86 | - void __iomem *base; | |
87 | - int ret; | |
88 | - | |
89 | - np_par = of_find_node_by_name(NULL, "par_io"); | |
90 | - if (np_par == NULL) { | |
91 | - printk(KERN_WARNING "%s couldn;t find par_io node\n", | |
92 | - __func__); | |
93 | - return; | |
152 | + /* Only apply this quirk when par_io is available */ | |
153 | + np = of_find_compatible_node(NULL, "network", "ucc_geth"); | |
154 | + if (np != NULL) { | |
155 | + quirk_mpc8360e_qe_enet10(); | |
156 | + of_node_put(np); | |
94 | 157 | } |
95 | - /* Map Parallel I/O ports registers */ | |
96 | - ret = of_address_to_resource(np_par, 0, &res); | |
97 | - if (ret) { | |
98 | - printk(KERN_WARNING "%s couldn;t map par_io registers\n", | |
99 | - __func__); | |
100 | - return; | |
101 | - } | |
102 | - | |
103 | - base = ioremap(res.start, res.end - res.start + 1); | |
104 | - | |
105 | - /* | |
106 | - * set output delay adjustments to default values according | |
107 | - * table 5 in Errata Rev. 5, 9/2011: | |
108 | - * | |
109 | - * write 0b01 to UCC1 bits 18:19 | |
110 | - * write 0b01 to UCC2 option 1 bits 4:5 | |
111 | - * write 0b01 to UCC2 option 2 bits 16:17 | |
112 | - */ | |
113 | - clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000); | |
114 | - | |
115 | - /* | |
116 | - * set output delay adjustments to default values according | |
117 | - * table 3-13 in Reference Manual Rev.3 05/2010: | |
118 | - * | |
119 | - * write 0b01 to UCC2 option 2 bits 16:17 | |
120 | - * write 0b0101 to UCC1 bits 20:23 | |
121 | - * write 0b0101 to UCC2 option 1 bits 24:27 | |
122 | - */ | |
123 | - clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550); | |
124 | - | |
125 | - if (SVR_REV(svid) == 0x0021) { | |
126 | - /* | |
127 | - * UCC2 option 1: write 0b1010 to bits 24:27 | |
128 | - * at address IMMRBAR+0x14AC | |
129 | - */ | |
130 | - clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0); | |
131 | - } else if (SVR_REV(svid) == 0x0020) { | |
132 | - /* | |
133 | - * UCC1: write 0b11 to bits 18:19 | |
134 | - * at address IMMRBAR+0x14A8 | |
135 | - */ | |
136 | - setbits32((base + 0xa8), 0x00003000); | |
137 | - | |
138 | - /* | |
139 | - * UCC2 option 1: write 0b11 to bits 4:5 | |
140 | - * at address IMMRBAR+0x14A8 | |
141 | - */ | |
142 | - setbits32((base + 0xa8), 0x0c000000); | |
143 | - | |
144 | - /* | |
145 | - * UCC2 option 2: write 0b11 to bits 16:17 | |
146 | - * at address IMMRBAR+0x14AC | |
147 | - */ | |
148 | - setbits32((base + 0xac), 0x0000c000); | |
149 | - } | |
150 | - iounmap(base); | |
151 | - of_node_put(np_par); | |
152 | - of_node_put(np); | |
153 | 158 | } |
154 | 159 | #endif /* CONFIG_QUICC_ENGINE */ |
155 | 160 | } |
arch/powerpc/platforms/85xx/Kconfig
... | ... | @@ -191,6 +191,13 @@ |
191 | 191 | help |
192 | 192 | This option enables support for the Wind River SBC8548 board |
193 | 193 | |
194 | +config PPA8548 | |
195 | + bool "Prodrive PPA8548" | |
196 | + help | |
197 | + This option enables support for the Prodrive PPA8548 board. | |
198 | + select DEFAULT_UIMAGE | |
199 | + select HAS_RAPIDIO | |
200 | + | |
194 | 201 | config GE_IMP3A |
195 | 202 | bool "GE Intelligent Platforms IMP3A" |
196 | 203 | select DEFAULT_UIMAGE |
arch/powerpc/platforms/85xx/Makefile
... | ... | @@ -25,6 +25,7 @@ |
25 | 25 | obj-$(CONFIG_STX_GP3) += stx_gp3.o |
26 | 26 | obj-$(CONFIG_TQM85xx) += tqm85xx.o |
27 | 27 | obj-$(CONFIG_SBC8548) += sbc8548.o |
28 | +obj-$(CONFIG_PPA8548) += ppa8548.o | |
28 | 29 | obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o |
29 | 30 | obj-$(CONFIG_KSI8560) += ksi8560.o |
30 | 31 | obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o |
arch/powerpc/platforms/85xx/mpc85xx_mds.c
... | ... | @@ -206,9 +206,7 @@ |
206 | 206 | setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST); |
207 | 207 | clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST); |
208 | 208 | |
209 | - for (np = NULL; (np = of_find_compatible_node(np, | |
210 | - "network", | |
211 | - "ucc_geth")) != NULL;) { | |
209 | + for_each_compatible_node(np, "network", "ucc_geth") { | |
212 | 210 | const unsigned int *prop; |
213 | 211 | int ucc_num; |
214 | 212 |
arch/powerpc/platforms/85xx/p1022_ds.c
... | ... | @@ -106,42 +106,6 @@ |
106 | 106 | (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \ |
107 | 107 | (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT)) |
108 | 108 | |
109 | -/** | |
110 | - * p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth | |
111 | - * | |
112 | - * The Area Descriptor is a 32-bit value that determine which bits in each | |
113 | - * pixel are to be used for each color. | |
114 | - */ | |
115 | -static u32 p1022ds_get_pixel_format(enum fsl_diu_monitor_port port, | |
116 | - unsigned int bits_per_pixel) | |
117 | -{ | |
118 | - switch (bits_per_pixel) { | |
119 | - case 32: | |
120 | - /* 0x88883316 */ | |
121 | - return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8); | |
122 | - case 24: | |
123 | - /* 0x88082219 */ | |
124 | - return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8); | |
125 | - case 16: | |
126 | - /* 0x65053118 */ | |
127 | - return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0); | |
128 | - default: | |
129 | - pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel); | |
130 | - return 0; | |
131 | - } | |
132 | -} | |
133 | - | |
134 | -/** | |
135 | - * p1022ds_set_gamma_table: update the gamma table, if necessary | |
136 | - * | |
137 | - * On some boards, the gamma table for some ports may need to be modified. | |
138 | - * This is not the case on the P1022DS, so we do nothing. | |
139 | -*/ | |
140 | -static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port, | |
141 | - char *gamma_table_base) | |
142 | -{ | |
143 | -} | |
144 | - | |
145 | 109 | struct fsl_law { |
146 | 110 | u32 lawbar; |
147 | 111 | u32 reserved1; |
... | ... | @@ -302,7 +266,7 @@ |
302 | 266 | goto exit; |
303 | 267 | } |
304 | 268 | cs1_addr = lbc_br_to_phys(ecm, num_laws, br1); |
305 | - if (!cs0_addr) { | |
269 | + if (!cs1_addr) { | |
306 | 270 | pr_err("p1022ds: could not determine physical address for CS1" |
307 | 271 | " (BR1=%08x)\n", br1); |
308 | 272 | goto exit; |
... | ... | @@ -510,8 +474,6 @@ |
510 | 474 | ppc_md.progress("p1022_ds_setup_arch()", 0); |
511 | 475 | |
512 | 476 | #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) |
513 | - diu_ops.get_pixel_format = p1022ds_get_pixel_format; | |
514 | - diu_ops.set_gamma_table = p1022ds_set_gamma_table; | |
515 | 477 | diu_ops.set_monitor_port = p1022ds_set_monitor_port; |
516 | 478 | diu_ops.set_pixel_clock = p1022ds_set_pixel_clock; |
517 | 479 | diu_ops.valid_monitor_port = p1022ds_valid_monitor_port; |
arch/powerpc/platforms/85xx/p1022_rdk.c
... | ... | @@ -35,17 +35,6 @@ |
35 | 35 | #define CLKDVDR_PXCLK_MASK 0x00FF0000 |
36 | 36 | |
37 | 37 | /** |
38 | - * p1022rdk_set_monitor_port: switch the output to a different monitor port | |
39 | - */ | |
40 | -static void p1022rdk_set_monitor_port(enum fsl_diu_monitor_port port) | |
41 | -{ | |
42 | - if (port != FSL_DIU_PORT_DVI) { | |
43 | - pr_err("p1022rdk: unsupported monitor port %i\n", port); | |
44 | - return; | |
45 | - } | |
46 | -} | |
47 | - | |
48 | -/** | |
49 | 38 | * p1022rdk_set_pixel_clock: program the DIU's clock |
50 | 39 | * |
51 | 40 | * @pixclock: the wavelength, in picoseconds, of the clock |
... | ... | @@ -124,7 +113,6 @@ |
124 | 113 | ppc_md.progress("p1022_rdk_setup_arch()", 0); |
125 | 114 | |
126 | 115 | #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) |
127 | - diu_ops.set_monitor_port = p1022rdk_set_monitor_port; | |
128 | 116 | diu_ops.set_pixel_clock = p1022rdk_set_pixel_clock; |
129 | 117 | diu_ops.valid_monitor_port = p1022rdk_valid_monitor_port; |
130 | 118 | #endif |
arch/powerpc/platforms/85xx/ppa8548.c
1 | +/* | |
2 | + * ppa8548 setup and early boot code. | |
3 | + * | |
4 | + * Copyright 2009 Prodrive B.V.. | |
5 | + * | |
6 | + * By Stef van Os (see MAINTAINERS for contact information) | |
7 | + * | |
8 | + * Based on the SBC8548 support - Copyright 2007 Wind River Systems Inc. | |
9 | + * Based on the MPC8548CDS support - Copyright 2005 Freescale Inc. | |
10 | + * | |
11 | + * This program is free software; you can redistribute it and/or modify it | |
12 | + * under the terms of the GNU General Public License as published by the | |
13 | + * Free Software Foundation; either version 2 of the License, or (at your | |
14 | + * option) any later version. | |
15 | + */ | |
16 | + | |
17 | +#include <linux/stddef.h> | |
18 | +#include <linux/kernel.h> | |
19 | +#include <linux/init.h> | |
20 | +#include <linux/reboot.h> | |
21 | +#include <linux/seq_file.h> | |
22 | +#include <linux/of_platform.h> | |
23 | + | |
24 | +#include <asm/machdep.h> | |
25 | +#include <asm/udbg.h> | |
26 | +#include <asm/mpic.h> | |
27 | + | |
28 | +#include <sysdev/fsl_soc.h> | |
29 | + | |
30 | +static void __init ppa8548_pic_init(void) | |
31 | +{ | |
32 | + struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN, | |
33 | + 0, 256, " OpenPIC "); | |
34 | + BUG_ON(mpic == NULL); | |
35 | + mpic_init(mpic); | |
36 | +} | |
37 | + | |
38 | +/* | |
39 | + * Setup the architecture | |
40 | + */ | |
41 | +static void __init ppa8548_setup_arch(void) | |
42 | +{ | |
43 | + if (ppc_md.progress) | |
44 | + ppc_md.progress("ppa8548_setup_arch()", 0); | |
45 | +} | |
46 | + | |
47 | +static void ppa8548_show_cpuinfo(struct seq_file *m) | |
48 | +{ | |
49 | + uint32_t svid, phid1; | |
50 | + | |
51 | + svid = mfspr(SPRN_SVR); | |
52 | + | |
53 | + seq_printf(m, "Vendor\t\t: Prodrive B.V.\n"); | |
54 | + seq_printf(m, "SVR\t\t: 0x%x\n", svid); | |
55 | + | |
56 | + /* Display cpu Pll setting */ | |
57 | + phid1 = mfspr(SPRN_HID1); | |
58 | + seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); | |
59 | +} | |
60 | + | |
61 | +static struct of_device_id __initdata of_bus_ids[] = { | |
62 | + { .name = "soc", }, | |
63 | + { .type = "soc", }, | |
64 | + { .compatible = "simple-bus", }, | |
65 | + { .compatible = "gianfar", }, | |
66 | + { .compatible = "fsl,srio", }, | |
67 | + {}, | |
68 | +}; | |
69 | + | |
70 | +static int __init declare_of_platform_devices(void) | |
71 | +{ | |
72 | + of_platform_bus_probe(NULL, of_bus_ids, NULL); | |
73 | + | |
74 | + return 0; | |
75 | +} | |
76 | +machine_device_initcall(ppa8548, declare_of_platform_devices); | |
77 | + | |
78 | +/* | |
79 | + * Called very early, device-tree isn't unflattened | |
80 | + */ | |
81 | +static int __init ppa8548_probe(void) | |
82 | +{ | |
83 | + unsigned long root = of_get_flat_dt_root(); | |
84 | + | |
85 | + return of_flat_dt_is_compatible(root, "ppa8548"); | |
86 | +} | |
87 | + | |
88 | +define_machine(ppa8548) { | |
89 | + .name = "ppa8548", | |
90 | + .probe = ppa8548_probe, | |
91 | + .setup_arch = ppa8548_setup_arch, | |
92 | + .init_IRQ = ppa8548_pic_init, | |
93 | + .show_cpuinfo = ppa8548_show_cpuinfo, | |
94 | + .get_irq = mpic_get_irq, | |
95 | + .restart = fsl_rstcr_restart, | |
96 | + .calibrate_decr = generic_calibrate_decr, | |
97 | + .progress = udbg_progress, | |
98 | +}; |
arch/powerpc/platforms/85xx/qemu_e500.c
... | ... | @@ -29,9 +29,10 @@ |
29 | 29 | void __init qemu_e500_pic_init(void) |
30 | 30 | { |
31 | 31 | struct mpic *mpic; |
32 | + unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU | | |
33 | + MPIC_ENABLE_COREINT; | |
32 | 34 | |
33 | - mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU, | |
34 | - 0, 256, " OpenPIC "); | |
35 | + mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC "); | |
35 | 36 | |
36 | 37 | BUG_ON(mpic == NULL); |
37 | 38 | mpic_init(mpic); |
... | ... | @@ -66,7 +67,7 @@ |
66 | 67 | #ifdef CONFIG_PCI |
67 | 68 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
68 | 69 | #endif |
69 | - .get_irq = mpic_get_irq, | |
70 | + .get_irq = mpic_get_coreint_irq, | |
70 | 71 | .restart = fsl_rstcr_restart, |
71 | 72 | .calibrate_decr = generic_calibrate_decr, |
72 | 73 | .progress = udbg_progress, |
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
arch/powerpc/sysdev/fsl_ifc.c
... | ... | @@ -63,7 +63,7 @@ |
63 | 63 | return -ENODEV; |
64 | 64 | |
65 | 65 | for (i = 0; i < ARRAY_SIZE(fsl_ifc_ctrl_dev->regs->cspr_cs); i++) { |
66 | - __be32 cspr = in_be32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr); | |
66 | + u32 cspr = in_be32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr); | |
67 | 67 | if (cspr & CSPR_V && (cspr & CSPR_BA) == |
68 | 68 | convert_ifc_address(addr_base)) |
69 | 69 | return i; |
arch/powerpc/sysdev/fsl_lbc.c
... | ... | @@ -74,8 +74,8 @@ |
74 | 74 | |
75 | 75 | lbc = fsl_lbc_ctrl_dev->regs; |
76 | 76 | for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) { |
77 | - __be32 br = in_be32(&lbc->bank[i].br); | |
78 | - __be32 or = in_be32(&lbc->bank[i].or); | |
77 | + u32 br = in_be32(&lbc->bank[i].br); | |
78 | + u32 or = in_be32(&lbc->bank[i].or); | |
79 | 79 | |
80 | 80 | if (br & BR_V && (br & or & BR_BA) == fsl_lbc_addr(addr_base)) |
81 | 81 | return i; |
... | ... | @@ -97,7 +97,7 @@ |
97 | 97 | int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm) |
98 | 98 | { |
99 | 99 | int bank; |
100 | - __be32 br; | |
100 | + u32 br; | |
101 | 101 | struct fsl_lbc_regs __iomem *lbc; |
102 | 102 | |
103 | 103 | bank = fsl_lbc_find(addr_base); |
arch/powerpc/sysdev/fsl_msi.c
... | ... | @@ -28,7 +28,7 @@ |
28 | 28 | #include "fsl_msi.h" |
29 | 29 | #include "fsl_pci.h" |
30 | 30 | |
31 | -LIST_HEAD(msi_head); | |
31 | +static LIST_HEAD(msi_head); | |
32 | 32 | |
33 | 33 | struct fsl_msi_feature { |
34 | 34 | u32 fsl_pic_ip; |
... | ... | @@ -130,7 +130,7 @@ |
130 | 130 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
131 | 131 | u64 address; /* Physical address of the MSIIR */ |
132 | 132 | int len; |
133 | - const u64 *reg; | |
133 | + const __be64 *reg; | |
134 | 134 | |
135 | 135 | /* If the msi-address-64 property exists, then use it */ |
136 | 136 | reg = of_get_property(hose->dn, "msi-address-64", &len); |
arch/powerpc/sysdev/fsl_pci.c
... | ... | @@ -421,14 +421,17 @@ |
421 | 421 | } |
422 | 422 | } |
423 | 423 | |
424 | -int __init fsl_add_bridge(struct device_node *dev, int is_primary) | |
424 | +int __init fsl_add_bridge(struct platform_device *pdev, int is_primary) | |
425 | 425 | { |
426 | 426 | int len; |
427 | 427 | struct pci_controller *hose; |
428 | 428 | struct resource rsrc; |
429 | 429 | const int *bus_range; |
430 | 430 | u8 hdr_type, progif; |
431 | + struct device_node *dev; | |
431 | 432 | |
433 | + dev = pdev->dev.of_node; | |
434 | + | |
432 | 435 | if (!of_device_is_available(dev)) { |
433 | 436 | pr_warning("%s: disabled\n", dev->full_name); |
434 | 437 | return -ENODEV; |
... | ... | @@ -453,6 +456,8 @@ |
453 | 456 | if (!hose) |
454 | 457 | return -ENOMEM; |
455 | 458 | |
459 | + /* set platform device as the parent */ | |
460 | + hose->parent = &pdev->dev; | |
456 | 461 | hose->first_busno = bus_range ? bus_range[0] : 0x0; |
457 | 462 | hose->last_busno = bus_range ? bus_range[1] : 0xff; |
458 | 463 | |
459 | 464 | |
460 | 465 | |
... | ... | @@ -827,13 +832,18 @@ |
827 | 832 | { .compatible = "fsl,mpc8548-pcie", }, |
828 | 833 | { .compatible = "fsl,mpc8610-pci", }, |
829 | 834 | { .compatible = "fsl,mpc8641-pcie", }, |
835 | + { .compatible = "fsl,qoriq-pcie-v2.1", }, | |
836 | + { .compatible = "fsl,qoriq-pcie-v2.2", }, | |
837 | + { .compatible = "fsl,qoriq-pcie-v2.3", }, | |
838 | + { .compatible = "fsl,qoriq-pcie-v2.4", }, | |
839 | + | |
840 | + /* | |
841 | + * The following entries are for compatibility with older device | |
842 | + * trees. | |
843 | + */ | |
830 | 844 | { .compatible = "fsl,p1022-pcie", }, |
831 | - { .compatible = "fsl,p1010-pcie", }, | |
832 | - { .compatible = "fsl,p1023-pcie", }, | |
833 | 845 | { .compatible = "fsl,p4080-pcie", }, |
834 | - { .compatible = "fsl,qoriq-pcie-v2.4", }, | |
835 | - { .compatible = "fsl,qoriq-pcie-v2.3", }, | |
836 | - { .compatible = "fsl,qoriq-pcie-v2.2", }, | |
846 | + | |
837 | 847 | {}, |
838 | 848 | }; |
839 | 849 | |
... | ... | @@ -880,7 +890,7 @@ |
880 | 890 | #endif |
881 | 891 | |
882 | 892 | node = pdev->dev.of_node; |
883 | - ret = fsl_add_bridge(node, fsl_pci_primary == node); | |
893 | + ret = fsl_add_bridge(pdev, fsl_pci_primary == node); | |
884 | 894 | |
885 | 895 | #ifdef CONFIG_SWIOTLB |
886 | 896 | if (ret == 0) { |
arch/powerpc/sysdev/fsl_pci.h
... | ... | @@ -91,7 +91,7 @@ |
91 | 91 | __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */ |
92 | 92 | }; |
93 | 93 | |
94 | -extern int fsl_add_bridge(struct device_node *dev, int is_primary); | |
94 | +extern int fsl_add_bridge(struct platform_device *pdev, int is_primary); | |
95 | 95 | extern void fsl_pcibios_fixup_bus(struct pci_bus *bus); |
96 | 96 | extern int mpc83xx_add_bridge(struct device_node *dev); |
97 | 97 | u64 fsl_pci_immrbar_base(struct pci_controller *hose); |
arch/powerpc/sysdev/fsl_soc.c
... | ... | @@ -58,10 +58,10 @@ |
58 | 58 | if (soc) { |
59 | 59 | int size; |
60 | 60 | u32 naddr; |
61 | - const u32 *prop = of_get_property(soc, "#address-cells", &size); | |
61 | + const __be32 *prop = of_get_property(soc, "#address-cells", &size); | |
62 | 62 | |
63 | 63 | if (prop && size == 4) |
64 | - naddr = *prop; | |
64 | + naddr = be32_to_cpup(prop); | |
65 | 65 | else |
66 | 66 | naddr = 2; |
67 | 67 |
arch/powerpc/sysdev/mpic.c
... | ... | @@ -1182,6 +1182,7 @@ |
1182 | 1182 | const char *vers; |
1183 | 1183 | const u32 *psrc; |
1184 | 1184 | u32 last_irq; |
1185 | + u32 fsl_version = 0; | |
1185 | 1186 | |
1186 | 1187 | /* Default MPIC search parameters */ |
1187 | 1188 | static const struct of_device_id __initconst mpic_device_id[] = { |
... | ... | @@ -1314,7 +1315,7 @@ |
1314 | 1315 | mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); |
1315 | 1316 | |
1316 | 1317 | if (mpic->flags & MPIC_FSL) { |
1317 | - u32 brr1, version; | |
1318 | + u32 brr1; | |
1318 | 1319 | int ret; |
1319 | 1320 | |
1320 | 1321 | /* |
... | ... | @@ -1327,7 +1328,7 @@ |
1327 | 1328 | |
1328 | 1329 | brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs, |
1329 | 1330 | MPIC_FSL_BRR1); |
1330 | - version = brr1 & MPIC_FSL_BRR1_VER; | |
1331 | + fsl_version = brr1 & MPIC_FSL_BRR1_VER; | |
1331 | 1332 | |
1332 | 1333 | /* Error interrupt mask register (EIMR) is required for |
1333 | 1334 | * handling individual device error interrupts. EIMR |
1334 | 1335 | |
... | ... | @@ -1342,11 +1343,30 @@ |
1342 | 1343 | * is the number of vectors which have been consumed by |
1343 | 1344 | * ipis and timer interrupts. |
1344 | 1345 | */ |
1345 | - if (version >= 0x401) { | |
1346 | + if (fsl_version >= 0x401) { | |
1346 | 1347 | ret = mpic_setup_error_int(mpic, intvec_top - 12); |
1347 | 1348 | if (ret) |
1348 | 1349 | return NULL; |
1349 | 1350 | } |
1351 | + | |
1352 | + } | |
1353 | + | |
1354 | + /* | |
1355 | + * EPR is only available starting with v4.0. To support | |
1356 | + * platforms that don't know the MPIC version at compile-time, | |
1357 | + * such as qemu-e500, turn off coreint if this MPIC doesn't | |
1358 | + * support it. Note that we never enable it if it wasn't | |
1359 | + * requested in the first place. | |
1360 | + * | |
1361 | + * This is done outside the MPIC_FSL check, so that we | |
1362 | + * also disable coreint if the MPIC node doesn't have | |
1363 | + * an "fsl,mpic" compatible at all. This will be the case | |
1364 | + * with device trees generated by older versions of QEMU. | |
1365 | + * fsl_version will be zero if MPIC_FSL is not set. | |
1366 | + */ | |
1367 | + if (fsl_version < 0x400 && (flags & MPIC_ENABLE_COREINT)) { | |
1368 | + WARN_ON(ppc_md.get_irq != mpic_get_coreint_irq); | |
1369 | + ppc_md.get_irq = mpic_get_irq; | |
1350 | 1370 | } |
1351 | 1371 | |
1352 | 1372 | /* Reset */ |