Commit 881e23e56764808e7ab1ed73b5d8a6700042ea38
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x86, microcode: Correct microcode revision format
506ed6b53e00 ("x86, intel: Output microcode revision in /proc/cpuinfo") added microcode revision format to /proc/cpuinfo and the MCE handler in decimal format but both AMD and Intel patch levels are handled as hex numbers. Fix it. Acked-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Showing 2 changed files with 2 additions and 2 deletions Side-by-side Diff
arch/x86/kernel/cpu/mcheck/mce.c
... | ... | @@ -221,7 +221,7 @@ |
221 | 221 | * Note this output is parsed by external tools and old fields |
222 | 222 | * should not be changed. |
223 | 223 | */ |
224 | - pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %u\n", | |
224 | + pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", | |
225 | 225 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, |
226 | 226 | cpu_data(m->extcpu).microcode); |
227 | 227 |
arch/x86/kernel/cpu/proc.c
... | ... | @@ -86,7 +86,7 @@ |
86 | 86 | else |
87 | 87 | seq_printf(m, "stepping\t: unknown\n"); |
88 | 88 | if (c->microcode) |
89 | - seq_printf(m, "microcode\t: %u\n", c->microcode); | |
89 | + seq_printf(m, "microcode\t: 0x%x\n", c->microcode); | |
90 | 90 | |
91 | 91 | if (cpu_has(c, X86_FEATURE_TSC)) { |
92 | 92 | unsigned int freq = cpufreq_quick_get(cpu); |