Commit 896508705561bea24656680cdaf3b4095c4d7473
1 parent
598c5abad7
Exists in
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MIPS: i8259: Convert IRQ controller lock to raw spinlock.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Showing 3 changed files with 16 additions and 16 deletions Side-by-side Diff
arch/mips/include/asm/i8259.h
... | ... | @@ -35,7 +35,7 @@ |
35 | 35 | #define SLAVE_ICW4_DEFAULT 0x01 |
36 | 36 | #define PIC_ICW4_AEOI 2 |
37 | 37 | |
38 | -extern spinlock_t i8259A_lock; | |
38 | +extern raw_spinlock_t i8259A_lock; | |
39 | 39 | |
40 | 40 | extern int i8259A_irq_pending(unsigned int irq); |
41 | 41 | extern void make_8259A_irq(unsigned int irq); |
... | ... | @@ -51,7 +51,7 @@ |
51 | 51 | { |
52 | 52 | int irq; |
53 | 53 | |
54 | - spin_lock(&i8259A_lock); | |
54 | + raw_spin_lock(&i8259A_lock); | |
55 | 55 | |
56 | 56 | /* Perform an interrupt acknowledge cycle on controller 1. */ |
57 | 57 | outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */ |
... | ... | @@ -78,7 +78,7 @@ |
78 | 78 | irq = -1; |
79 | 79 | } |
80 | 80 | |
81 | - spin_unlock(&i8259A_lock); | |
81 | + raw_spin_unlock(&i8259A_lock); | |
82 | 82 | |
83 | 83 | return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq; |
84 | 84 | } |
arch/mips/kernel/i8259.c
... | ... | @@ -29,7 +29,7 @@ |
29 | 29 | */ |
30 | 30 | |
31 | 31 | static int i8259A_auto_eoi = -1; |
32 | -DEFINE_SPINLOCK(i8259A_lock); | |
32 | +DEFINE_RAW_SPINLOCK(i8259A_lock); | |
33 | 33 | static void disable_8259A_irq(unsigned int irq); |
34 | 34 | static void enable_8259A_irq(unsigned int irq); |
35 | 35 | static void mask_and_ack_8259A(unsigned int irq); |
36 | 36 | |
... | ... | @@ -65,13 +65,13 @@ |
65 | 65 | |
66 | 66 | irq -= I8259A_IRQ_BASE; |
67 | 67 | mask = 1 << irq; |
68 | - spin_lock_irqsave(&i8259A_lock, flags); | |
68 | + raw_spin_lock_irqsave(&i8259A_lock, flags); | |
69 | 69 | cached_irq_mask |= mask; |
70 | 70 | if (irq & 8) |
71 | 71 | outb(cached_slave_mask, PIC_SLAVE_IMR); |
72 | 72 | else |
73 | 73 | outb(cached_master_mask, PIC_MASTER_IMR); |
74 | - spin_unlock_irqrestore(&i8259A_lock, flags); | |
74 | + raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
75 | 75 | } |
76 | 76 | |
77 | 77 | static void enable_8259A_irq(unsigned int irq) |
78 | 78 | |
... | ... | @@ -81,13 +81,13 @@ |
81 | 81 | |
82 | 82 | irq -= I8259A_IRQ_BASE; |
83 | 83 | mask = ~(1 << irq); |
84 | - spin_lock_irqsave(&i8259A_lock, flags); | |
84 | + raw_spin_lock_irqsave(&i8259A_lock, flags); | |
85 | 85 | cached_irq_mask &= mask; |
86 | 86 | if (irq & 8) |
87 | 87 | outb(cached_slave_mask, PIC_SLAVE_IMR); |
88 | 88 | else |
89 | 89 | outb(cached_master_mask, PIC_MASTER_IMR); |
90 | - spin_unlock_irqrestore(&i8259A_lock, flags); | |
90 | + raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
91 | 91 | } |
92 | 92 | |
93 | 93 | int i8259A_irq_pending(unsigned int irq) |
94 | 94 | |
... | ... | @@ -98,12 +98,12 @@ |
98 | 98 | |
99 | 99 | irq -= I8259A_IRQ_BASE; |
100 | 100 | mask = 1 << irq; |
101 | - spin_lock_irqsave(&i8259A_lock, flags); | |
101 | + raw_spin_lock_irqsave(&i8259A_lock, flags); | |
102 | 102 | if (irq < 8) |
103 | 103 | ret = inb(PIC_MASTER_CMD) & mask; |
104 | 104 | else |
105 | 105 | ret = inb(PIC_SLAVE_CMD) & (mask >> 8); |
106 | - spin_unlock_irqrestore(&i8259A_lock, flags); | |
106 | + raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
107 | 107 | |
108 | 108 | return ret; |
109 | 109 | } |
... | ... | @@ -151,7 +151,7 @@ |
151 | 151 | |
152 | 152 | irq -= I8259A_IRQ_BASE; |
153 | 153 | irqmask = 1 << irq; |
154 | - spin_lock_irqsave(&i8259A_lock, flags); | |
154 | + raw_spin_lock_irqsave(&i8259A_lock, flags); | |
155 | 155 | /* |
156 | 156 | * Lightweight spurious IRQ detection. We do not want |
157 | 157 | * to overdo spurious IRQ handling - it's usually a sign |
... | ... | @@ -183,7 +183,7 @@ |
183 | 183 | outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */ |
184 | 184 | } |
185 | 185 | smtc_im_ack_irq(irq); |
186 | - spin_unlock_irqrestore(&i8259A_lock, flags); | |
186 | + raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
187 | 187 | return; |
188 | 188 | |
189 | 189 | spurious_8259A_irq: |
... | ... | @@ -264,7 +264,7 @@ |
264 | 264 | |
265 | 265 | i8259A_auto_eoi = auto_eoi; |
266 | 266 | |
267 | - spin_lock_irqsave(&i8259A_lock, flags); | |
267 | + raw_spin_lock_irqsave(&i8259A_lock, flags); | |
268 | 268 | |
269 | 269 | outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ |
270 | 270 | outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ |
... | ... | @@ -298,7 +298,7 @@ |
298 | 298 | outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */ |
299 | 299 | outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */ |
300 | 300 | |
301 | - spin_unlock_irqrestore(&i8259A_lock, flags); | |
301 | + raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
302 | 302 | } |
303 | 303 | |
304 | 304 | /* |
arch/mips/loongson/lemote-2f/irq.c
... | ... | @@ -38,7 +38,7 @@ |
38 | 38 | irq = -1; |
39 | 39 | |
40 | 40 | if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) { |
41 | - spin_lock(&i8259A_lock); | |
41 | + raw_spin_lock(&i8259A_lock); | |
42 | 42 | isr = inb(PIC_MASTER_CMD) & |
43 | 43 | ~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR); |
44 | 44 | if (!isr) |
... | ... | @@ -56,7 +56,7 @@ |
56 | 56 | if (~inb(PIC_MASTER_ISR) & 0x80) |
57 | 57 | irq = -1; |
58 | 58 | } |
59 | - spin_unlock(&i8259A_lock); | |
59 | + raw_spin_unlock(&i8259A_lock); | |
60 | 60 | } |
61 | 61 | |
62 | 62 | return irq; |