Blackfin: bf537: demux port H mask A and emac rx ints

The BF537 SIC combines the gpio port H mask A interrupts with the emac rx interrupt, so we need to demux this in software. It also combines the gpio port H mask B and the emac tx interrupts, and the watchdog and port F mask B interrupts, but since we don't support mask B yet, just add the defines for now. Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Blackfin: bf537: demux port H mask A and emac rx ints
The BF537 SIC combines the gpio port H mask A interrupts with the emac rx interrupt, so we need to demux this in software. It also combines the gpio port H mask B and the emac tx interrupts, and the watchdog and port F mask B interrupts, but since we don't support mask B yet, just add the defines for now. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Mike Frysinger
1 parent e2a8092c3f
Showing 5 changed files with 77 additions and 20 deletions Side-by-side Diff
arch/blackfin/include/asm/irq_handler.h
arch/blackfin/kernel/bfin_gpio.c
arch/blackfin/mach-bf537/include/mach/irq.h
arch/blackfin/mach-bf537/ints-priority.c
arch/blackfin/mach-common/ints-priority.c
@@ -60,6 +60,7 @@
  
 struct irq_desc;
 extern void bfin_demux_mac_status_irq(unsigned int, struct irq_desc *);
+extern void bfin_demux_gpio_irq(unsigned int, struct irq_desc *);
  
 #endif
@@ -535,7 +535,7 @@
 #if defined(BF533_FAMILY)
 	IRQ_PROG_INTB
 #elif defined(BF537_FAMILY)
-	IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX
+	IRQ_PF_INTB_WATCH, IRQ_PORTG_INTB, IRQ_PH_INTB_MAC_TX
 #elif defined(BF538_FAMILY)
 	IRQ_PORTF_INTB
 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
@@ -28,8 +28,8 @@
 #define IRQ_UART1_TX		BFIN_IRQ(14)	/* DMA11 Interrupt (UART1 TX) */
 #define IRQ_CAN_RX		BFIN_IRQ(15)	/* CAN Receive Interrupt */
 #define IRQ_CAN_TX		BFIN_IRQ(16)	/* CAN Transmit Interrupt */
-#define IRQ_MAC_RX		BFIN_IRQ(17)	/* DMA1 (Ethernet RX) Interrupt */
-#define IRQ_MAC_TX		BFIN_IRQ(18)	/* DMA2 (Ethernet TX) Interrupt */
+#define IRQ_PH_INTA_MAC_RX	BFIN_IRQ(17)	/* Port H Interrupt A & DMA1 Interrupt (Ethernet RX) */
+#define IRQ_PH_INTB_MAC_TX	BFIN_IRQ(18)	/* Port H Interrupt B & DMA2 Interrupt (Ethernet TX) */
 #define IRQ_TIMER0		BFIN_IRQ(19)	/* Timer 0 */
 #define IRQ_TIMER1		BFIN_IRQ(20)	/* Timer 1 */
 #define IRQ_TIMER2		BFIN_IRQ(21)	/* Timer 2 */
  
@@ -38,12 +38,11 @@
 #define IRQ_TIMER5		BFIN_IRQ(24)	/* Timer 5 */
 #define IRQ_TIMER6		BFIN_IRQ(25)	/* Timer 6 */
 #define IRQ_TIMER7		BFIN_IRQ(26)	/* Timer 7 */
-#define IRQ_PROG_INTA		BFIN_IRQ(27)	/* PF Ports F&G (PF15:0) Interrupt A */
-#define IRQ_PORTG_INTB		BFIN_IRQ(28)	/* PF Port G (PF15:0) Interrupt B */
+#define IRQ_PF_INTA_PG_INTA	BFIN_IRQ(27)	/* Ports F&G Interrupt A */
+#define IRQ_PORTG_INTB		BFIN_IRQ(28)	/* Port G Interrupt B */
 #define IRQ_MEM_DMA0		BFIN_IRQ(29)	/* (Memory DMA Stream 0) */
 #define IRQ_MEM_DMA1		BFIN_IRQ(30)	/* (Memory DMA Stream 1) */
-#define IRQ_PROG_INTB		BFIN_IRQ(31)	/* PF Ports F (PF15:0) Interrupt B */
-#define IRQ_WATCH		BFIN_IRQ(32)	/* Watch Dog Timer */
+#define IRQ_PF_INTB_WATCH	BFIN_IRQ(31)	/* Watchdog & Port F Interrupt B */
  
 #define SYS_IRQS		39
  
@@ -118,7 +117,27 @@
 #define IRQ_MAC_TXDMAERR	104	/* TX DMA Direction Error Interrupt */
 #define IRQ_MAC_STMDONE		105	/* Station Mgt. Transfer Done Interrupt */
  
-#define NR_MACH_IRQS		(IRQ_MAC_STMDONE + 1)
+#define IRQ_MAC_RX		106	/* DMA1 Interrupt (Ethernet RX) */
+#define IRQ_PORTH_INTA		107	/* Port H Interrupt A */
+
+#if 0 /* No Interrupt B support (yet) */
+#define IRQ_MAC_TX		108	/* DMA2 Interrupt (Ethernet TX) */
+#define IRQ_PORTH_INTB		109	/* Port H Interrupt B */
+#else
+#define IRQ_MAC_TX		IRQ_PH_INTB_MAC_TX
+#endif
+
+#define IRQ_PORTF_INTA		110	/* Port F Interrupt A */
+#define IRQ_PORTG_INTA		111	/* Port G Interrupt A */
+
+#if 0 /* No Interrupt B support (yet) */
+#define IRQ_WATCH		112	/* Watchdog Timer */
+#define IRQ_PORTF_INTB		113	/* Port F Interrupt B */
+#else
+#define IRQ_WATCH		IRQ_PF_INTB_WATCH
+#endif
+
+#define NR_MACH_IRQS		(113 + 1)
  
 /* IAR0 BIT FIELDS */
 #define IRQ_PLL_WAKEUP_POS	0
@@ -14,6 +14,7 @@
 #include <asm/bfin5xx_spi.h>
 #include <asm/bfin_sport.h>
 #include <asm/bfin_can.h>
+#include <asm/bfin_dma.h>
 #include <asm/dpmc.h>
  
 void __init program_IAR(void)
@@ -157,6 +158,40 @@
  
 }
  
+#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+static int mac_rx_int_mask;
+
+static void bf537_mac_rx_mask_irq(struct irq_data *d)
+{
+	mac_rx_int_mask &= ~(1L << (d->irq - IRQ_MAC_RX));
+	if (!mac_rx_int_mask)
+		bfin_internal_mask_irq(IRQ_PH_INTA_MAC_RX);
+}
+
+static void bf537_mac_rx_unmask_irq(struct irq_data *d)
+{
+	bfin_internal_unmask_irq(IRQ_PH_INTA_MAC_RX);
+	mac_rx_int_mask |= 1L << (d->irq - IRQ_MAC_RX);
+}
+
+static struct irq_chip bf537_mac_rx_irqchip = {
+	.name = "ERROR",
+	.irq_ack = bfin_ack_noop,
+	.irq_mask_ack = bf537_mac_rx_mask_irq,
+	.irq_mask = bf537_mac_rx_mask_irq,
+	.irq_unmask = bf537_mac_rx_unmask_irq,
+};
+
+static void bf537_demux_mac_rx_irq(unsigned int int_irq,
+				   struct irq_desc *desc)
+{
+	if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR))
+		bfin_handle_irq(IRQ_MAC_RX);
+	else
+		bfin_demux_gpio_irq(int_irq, desc);
+}
+#endif
+
 void __init init_mach_irq(void)
 {
 	int irq;
@@ -172,6 +207,10 @@
 					 handle_level_irq);
  
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+	irq_set_chained_handler(IRQ_PH_INTA_MAC_RX, bf537_demux_mac_rx_irq);
+	irq_set_chip_and_handler(IRQ_MAC_RX, &bf537_mac_rx_irqchip, handle_level_irq);
+	irq_set_chip_and_handler(IRQ_PORTH_INTA, &bf537_mac_rx_irqchip, handle_level_irq);
+
 	irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
 #endif
 }
@@ -582,22 +582,20 @@
 	}
 }
  
-static void bfin_demux_gpio_irq(unsigned int inta_irq,
-				struct irq_desc *desc)
+void bfin_demux_gpio_irq(unsigned int inta_irq,
+			 struct irq_desc *desc)
 {
 	unsigned int irq;
  
 	switch (inta_irq) {
 #if defined(BF537_FAMILY)
-	case IRQ_PROG_INTA:
+	case IRQ_PF_INTA_PG_INTA:
 		bfin_demux_gpio_block(IRQ_PF0);
 		irq = IRQ_PG0;
 		break;
-# if !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
-	case IRQ_MAC_RX:
+	case IRQ_PH_INTA_MAC_RX:
 		irq = IRQ_PH0;
 		break;
-# endif
 #elif defined(BF533_FAMILY)
 	case IRQ_PROG_INTA:
 		irq = IRQ_PF0;
@@ -881,8 +879,8 @@
 # define bfin_gpio_set_wake NULL
 #endif
  
-static void bfin_demux_gpio_irq(unsigned int inta_irq,
-				struct irq_desc *desc)
+void bfin_demux_gpio_irq(unsigned int inta_irq,
+			 struct irq_desc *desc)
 {
 	u32 bank, pint_val;
 	u32 request, irq;
  
@@ -1001,11 +999,11 @@
 			irq_set_chip(irq, &bfin_internal_irqchip);
  
 		switch (irq) {
-#if defined(CONFIG_BF53x)
+#if defined(BF537_FAMILY)
+		case IRQ_PH_INTA_MAC_RX:
+		case IRQ_PF_INTA_PG_INTA:
+#elif defined(BF533_FAMILY)
 		case IRQ_PROG_INTA:
-# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
-		case IRQ_MAC_RX:
-# endif
 #elif defined(CONFIG_BF54x)
 		case IRQ_PINT0:
 		case IRQ_PINT1:
...	...	@@ -60,6 +60,7 @@
60	60
61	61	struct irq_desc;
62	62	extern void bfin_demux_mac_status_irq(unsigned int, struct irq_desc *);
	63	+extern void bfin_demux_gpio_irq(unsigned int, struct irq_desc *);
63	64
64	65	#endif
...	...	@@ -535,7 +535,7 @@
535	535	#if defined(BF533_FAMILY)
536	536	IRQ_PROG_INTB
537	537	#elif defined(BF537_FAMILY)
538		- IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX
	538	+ IRQ_PF_INTB_WATCH, IRQ_PORTG_INTB, IRQ_PH_INTB_MAC_TX
539	539	#elif defined(BF538_FAMILY)
540	540	IRQ_PORTF_INTB
541	541	#elif defined(CONFIG_BF52x) \|\| defined(CONFIG_BF51x)
...	...	@@ -28,8 +28,8 @@
28	28	#define IRQ_UART1_TX BFIN_IRQ(14) /* DMA11 Interrupt (UART1 TX) */
29	29	#define IRQ_CAN_RX BFIN_IRQ(15) /* CAN Receive Interrupt */
30	30	#define IRQ_CAN_TX BFIN_IRQ(16) /* CAN Transmit Interrupt */
31		-#define IRQ_MAC_RX BFIN_IRQ(17) /* DMA1 (Ethernet RX) Interrupt */
32		-#define IRQ_MAC_TX BFIN_IRQ(18) /* DMA2 (Ethernet TX) Interrupt */
	31	+#define IRQ_PH_INTA_MAC_RX BFIN_IRQ(17) /* Port H Interrupt A & DMA1 Interrupt (Ethernet RX) */
	32	+#define IRQ_PH_INTB_MAC_TX BFIN_IRQ(18) /* Port H Interrupt B & DMA2 Interrupt (Ethernet TX) */
33	33	#define IRQ_TIMER0 BFIN_IRQ(19) /* Timer 0 */
34	34	#define IRQ_TIMER1 BFIN_IRQ(20) /* Timer 1 */
35	35	#define IRQ_TIMER2 BFIN_IRQ(21) /* Timer 2 */
36	36
...	...	@@ -38,12 +38,11 @@
38	38	#define IRQ_TIMER5 BFIN_IRQ(24) /* Timer 5 */
39	39	#define IRQ_TIMER6 BFIN_IRQ(25) /* Timer 6 */
40	40	#define IRQ_TIMER7 BFIN_IRQ(26) /* Timer 7 */
41		-#define IRQ_PROG_INTA BFIN_IRQ(27) /* PF Ports F&G (PF15:0) Interrupt A */
42		-#define IRQ_PORTG_INTB BFIN_IRQ(28) /* PF Port G (PF15:0) Interrupt B */
	41	+#define IRQ_PF_INTA_PG_INTA BFIN_IRQ(27) /* Ports F&G Interrupt A */
	42	+#define IRQ_PORTG_INTB BFIN_IRQ(28) /* Port G Interrupt B */
43	43	#define IRQ_MEM_DMA0 BFIN_IRQ(29) /* (Memory DMA Stream 0) */
44	44	#define IRQ_MEM_DMA1 BFIN_IRQ(30) /* (Memory DMA Stream 1) */
45		-#define IRQ_PROG_INTB BFIN_IRQ(31) /* PF Ports F (PF15:0) Interrupt B */
46		-#define IRQ_WATCH BFIN_IRQ(32) /* Watch Dog Timer */
	45	+#define IRQ_PF_INTB_WATCH BFIN_IRQ(31) /* Watchdog & Port F Interrupt B */
47	46
48	47	#define SYS_IRQS 39
49	48
...	...	@@ -118,7 +117,27 @@
118	117	#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
119	118	#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
120	119
121		-#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
	120	+#define IRQ_MAC_RX 106 /* DMA1 Interrupt (Ethernet RX) */
	121	+#define IRQ_PORTH_INTA 107 /* Port H Interrupt A */
	122	+
	123	+#if 0 /* No Interrupt B support (yet) */
	124	+#define IRQ_MAC_TX 108 /* DMA2 Interrupt (Ethernet TX) */
	125	+#define IRQ_PORTH_INTB 109 /* Port H Interrupt B */
	126	+#else
	127	+#define IRQ_MAC_TX IRQ_PH_INTB_MAC_TX
	128	+#endif
	129	+
	130	+#define IRQ_PORTF_INTA 110 /* Port F Interrupt A */
	131	+#define IRQ_PORTG_INTA 111 /* Port G Interrupt A */
	132	+
	133	+#if 0 /* No Interrupt B support (yet) */
	134	+#define IRQ_WATCH 112 /* Watchdog Timer */
	135	+#define IRQ_PORTF_INTB 113 /* Port F Interrupt B */
	136	+#else
	137	+#define IRQ_WATCH IRQ_PF_INTB_WATCH
	138	+#endif
	139	+
	140	+#define NR_MACH_IRQS (113 + 1)
122	141
123	142	/* IAR0 BIT FIELDS */
124	143	#define IRQ_PLL_WAKEUP_POS 0
...	...	@@ -14,6 +14,7 @@
14	14	#include <asm/bfin5xx_spi.h>
15	15	#include <asm/bfin_sport.h>
16	16	#include <asm/bfin_can.h>
	17	+#include <asm/bfin_dma.h>
17	18	#include <asm/dpmc.h>
18	19
19	20	void __init program_IAR(void)
...	...	@@ -157,6 +158,40 @@
157	158
158	159	}
159	160
	161	+#if defined(CONFIG_BFIN_MAC) \|\| defined(CONFIG_BFIN_MAC_MODULE)
	162	+static int mac_rx_int_mask;
	163	+
	164	+static void bf537_mac_rx_mask_irq(struct irq_data *d)
	165	+{
	166	+ mac_rx_int_mask &= ~(1L << (d->irq - IRQ_MAC_RX));
	167	+ if (!mac_rx_int_mask)
	168	+ bfin_internal_mask_irq(IRQ_PH_INTA_MAC_RX);
	169	+}
	170	+
	171	+static void bf537_mac_rx_unmask_irq(struct irq_data *d)
	172	+{
	173	+ bfin_internal_unmask_irq(IRQ_PH_INTA_MAC_RX);
	174	+ mac_rx_int_mask \|= 1L << (d->irq - IRQ_MAC_RX);
	175	+}
	176	+
	177	+static struct irq_chip bf537_mac_rx_irqchip = {
	178	+ .name = "ERROR",
	179	+ .irq_ack = bfin_ack_noop,
	180	+ .irq_mask_ack = bf537_mac_rx_mask_irq,
	181	+ .irq_mask = bf537_mac_rx_mask_irq,
	182	+ .irq_unmask = bf537_mac_rx_unmask_irq,
	183	+};
	184	+
	185	+static void bf537_demux_mac_rx_irq(unsigned int int_irq,
	186	+ struct irq_desc *desc)
	187	+{
	188	+ if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE \| DMA_ERR))
	189	+ bfin_handle_irq(IRQ_MAC_RX);
	190	+ else
	191	+ bfin_demux_gpio_irq(int_irq, desc);
	192	+}
	193	+#endif
	194	+
160	195	void __init init_mach_irq(void)
161	196	{
162	197	int irq;
...	...	@@ -172,6 +207,10 @@
172	207	handle_level_irq);
173	208
174	209	#if defined(CONFIG_BFIN_MAC) \|\| defined(CONFIG_BFIN_MAC_MODULE)
	210	+ irq_set_chained_handler(IRQ_PH_INTA_MAC_RX, bf537_demux_mac_rx_irq);
	211	+ irq_set_chip_and_handler(IRQ_MAC_RX, &bf537_mac_rx_irqchip, handle_level_irq);
	212	+ irq_set_chip_and_handler(IRQ_PORTH_INTA, &bf537_mac_rx_irqchip, handle_level_irq);
	213	+
175	214	irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
176	215	#endif
177	216	}
...	...	@@ -582,22 +582,20 @@
582	582	}
583	583	}
584	584
585		-static void bfin_demux_gpio_irq(unsigned int inta_irq,
586		- struct irq_desc *desc)
	585	+void bfin_demux_gpio_irq(unsigned int inta_irq,
	586	+ struct irq_desc *desc)
587	587	{
588	588	unsigned int irq;
589	589
590	590	switch (inta_irq) {
591	591	#if defined(BF537_FAMILY)
592		- case IRQ_PROG_INTA:
	592	+ case IRQ_PF_INTA_PG_INTA:
593	593	bfin_demux_gpio_block(IRQ_PF0);
594	594	irq = IRQ_PG0;
595	595	break;
596		-# if !(defined(CONFIG_BFIN_MAC) \|\| defined(CONFIG_BFIN_MAC_MODULE))
597		- case IRQ_MAC_RX:
	596	+ case IRQ_PH_INTA_MAC_RX:
598	597	irq = IRQ_PH0;
599	598	break;
600		-# endif
601	599	#elif defined(BF533_FAMILY)
602	600	case IRQ_PROG_INTA:
603	601	irq = IRQ_PF0;
...	...	@@ -881,8 +879,8 @@
881	879	# define bfin_gpio_set_wake NULL
882	880	#endif
883	881
884		-static void bfin_demux_gpio_irq(unsigned int inta_irq,
885		- struct irq_desc *desc)
	882	+void bfin_demux_gpio_irq(unsigned int inta_irq,
	883	+ struct irq_desc *desc)
886	884	{
887	885	u32 bank, pint_val;
888	886	u32 request, irq;
889	887
...	...	@@ -1001,11 +999,11 @@
1001	999	irq_set_chip(irq, &bfin_internal_irqchip);
1002	1000
1003	1001	switch (irq) {
1004		-#if defined(CONFIG_BF53x)
	1002	+#if defined(BF537_FAMILY)
	1003	+ case IRQ_PH_INTA_MAC_RX:
	1004	+ case IRQ_PF_INTA_PG_INTA:
	1005	+#elif defined(BF533_FAMILY)
1005	1006	case IRQ_PROG_INTA:
1006		-# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) \|\| defined(CONFIG_BFIN_MAC_MODULE))
1007		- case IRQ_MAC_RX:
1008		-# endif
1009	1007	#elif defined(CONFIG_BF54x)
1010	1008	case IRQ_PINT0:
1011	1009	case IRQ_PINT1: