Commit 8d9e53b93de7383d5bb4b3507f146bfcd83c6e5d
1 parent
eafa5c8a10
Exists in
smarc-imx_3.14.28_1.0.0_ga
and in
1 other branch
tile PCI RC: use proper accessor function
Using the low-level hv_dev_pread() API makes assumptions about the layout of datastructures in the Tilera hypervisor API; it's better to use the gxio_XXX accessor and the pcie_trio_ports_property struct. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Showing 1 changed file with 11 additions and 13 deletions Side-by-side Diff
arch/tile/kernel/pci_gx.c
| ... | ... | @@ -91,7 +91,7 @@ |
| 91 | 91 | TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1 |
| 92 | 92 | |
| 93 | 93 | /* Array of the PCIe ports configuration info obtained from the BIB. */ |
| 94 | -struct pcie_port_property pcie_ports[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES]; | |
| 94 | +struct pcie_trio_ports_property pcie_ports[TILEGX_NUM_TRIO]; | |
| 95 | 95 | |
| 96 | 96 | /* Number of configured TRIO instances. */ |
| 97 | 97 | int num_trio_shims; |
| ... | ... | @@ -195,10 +195,7 @@ |
| 195 | 195 | #endif |
| 196 | 196 | |
| 197 | 197 | /* Get the properties of the PCIe ports on this TRIO instance. */ |
| 198 | - ret = hv_dev_pread(context->fd, 0, | |
| 199 | - (HV_VirtAddr)&pcie_ports[trio_index][0], | |
| 200 | - sizeof(struct pcie_port_property) * TILEGX_TRIO_PCIES, | |
| 201 | - GXIO_TRIO_OP_GET_PORT_PROPERTY); | |
| 198 | + ret = gxio_trio_get_port_property(context, &pcie_ports[trio_index]); | |
| 202 | 199 | if (ret < 0) { |
| 203 | 200 | pr_err("PCI: PCIE_GET_PORT_PROPERTY failure, error %d," |
| 204 | 201 | " on TRIO %d\n", ret, trio_index); |
| ... | ... | @@ -221,8 +218,8 @@ |
| 221 | 218 | unsigned int reg_offset; |
| 222 | 219 | |
| 223 | 220 | /* Ignore ports that are not specified in the BIB. */ |
| 224 | - if (!pcie_ports[trio_index][mac].allow_rc && | |
| 225 | - !pcie_ports[trio_index][mac].allow_ep) | |
| 221 | + if (!pcie_ports[trio_index].ports[mac].allow_rc && | |
| 222 | + !pcie_ports[trio_index].ports[mac].allow_ep) | |
| 226 | 223 | continue; |
| 227 | 224 | |
| 228 | 225 | reg_offset = |
| ... | ... | @@ -243,7 +240,7 @@ |
| 243 | 240 | */ |
| 244 | 241 | if (port_config.strap_state == AUTO_CONFIG_EP || |
| 245 | 242 | port_config.strap_state == AUTO_CONFIG_EP_G1) |
| 246 | - pcie_ports[trio_index][mac].allow_ep = 1; | |
| 243 | + pcie_ports[trio_index].ports[mac].allow_ep = 1; | |
| 247 | 244 | } |
| 248 | 245 | } |
| 249 | 246 | |
| ... | ... | @@ -438,9 +435,10 @@ |
| 438 | 435 | return 0; |
| 439 | 436 | |
| 440 | 437 | /* |
| 441 | - * Now determine which PCIe ports are configured to operate in RC mode. | |
| 442 | - * We look at the Board Information Block first and then see if there | |
| 443 | - * are any overriding configuration by the HW strapping pin. | |
| 438 | + * Now determine which PCIe ports are configured to operate in RC | |
| 439 | + * mode. To use a port, it must be allowed to be in RC mode by the | |
| 440 | + * Board Information Block, and the hardware strapping pins must be | |
| 441 | + * set to RC mode. | |
| 444 | 442 | */ |
| 445 | 443 | for (i = 0; i < TILEGX_NUM_TRIO; i++) { |
| 446 | 444 | gxio_trio_context_t *context = &trio_contexts[i]; |
| ... | ... | @@ -449,7 +447,7 @@ |
| 449 | 447 | continue; |
| 450 | 448 | |
| 451 | 449 | for (j = 0; j < TILEGX_TRIO_PCIES; j++) { |
| 452 | - if (pcie_ports[i][j].allow_rc && | |
| 450 | + if (pcie_ports[i].ports[j].allow_rc && | |
| 453 | 451 | strapped_for_rc(context, j)) { |
| 454 | 452 | pcie_rc[i][j] = 1; |
| 455 | 453 | num_rc_controllers++; |
| ... | ... | @@ -736,7 +734,7 @@ |
| 736 | 734 | __gxio_mmio_read(trio_context->mmio_base_mac + |
| 737 | 735 | reg_offset); |
| 738 | 736 | if (!port_status.dl_up) { |
| 739 | - if (pcie_ports[trio_index][mac].removable) { | |
| 737 | + if (pcie_ports[trio_index].ports[mac].removable) { | |
| 740 | 738 | pr_info("PCI: link is down, MAC %d on TRIO %d\n", |
| 741 | 739 | mac, trio_index); |
| 742 | 740 | pr_info("This is expected if no PCIe card" |