Commit 8f4c344696b9f9f8471d7f342076ef10ed7f66a5
Committed by
Linus Torvalds
1 parent
dcb30e6592
Exists in
smarc-imx_3.14.28_1.0.0_ga
and in
1 other branch
lockref: use cmpxchg64 explicitly for lockless updates
The cmpxchg() function tends not to support 64-bit arguments on 32-bit architectures. This could be either due to use of unsigned long arguments (like on ARM) or lack of instruction support (cmpxchgq on x86). However, these architectures may implement a specific cmpxchg64() function to provide 64-bit cmpxchg support instead. Since the lockref code requires a 64-bit cmpxchg and relies on the architecture selecting ARCH_USE_CMPXCHG_LOCKREF, move to using cmpxchg64 instead of cmpxchg and allow 32-bit architectures to make use of the lockless lockref implementation. Cc: Waiman Long <Waiman.Long@hp.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Showing 1 changed file with 2 additions and 2 deletions Side-by-side Diff
lib/lockref.c
... | ... | @@ -14,8 +14,8 @@ |
14 | 14 | while (likely(arch_spin_value_unlocked(old.lock.rlock.raw_lock))) { \ |
15 | 15 | struct lockref new = old, prev = old; \ |
16 | 16 | CODE \ |
17 | - old.lock_count = cmpxchg(&lockref->lock_count, \ | |
18 | - old.lock_count, new.lock_count); \ | |
17 | + old.lock_count = cmpxchg64(&lockref->lock_count, \ | |
18 | + old.lock_count, new.lock_count); \ | |
19 | 19 | if (likely(old.lock_count == prev.lock_count)) { \ |
20 | 20 | SUCCESS; \ |
21 | 21 | } \ |