Commit 91e80aecff77349312f032cf8792885871fa6477
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0a6f98c958
Exists in
smarc-l5.0.0_1.0.0-ga
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ARM: OMAP2+: Make ctrl_module_core_44xx.h local
This can be local to mach-omap2. Signed-off-by: Tony Lindgren <tony@atomide.com>
Showing 3 changed files with 393 additions and 393 deletions Inline Diff
arch/arm/mach-omap2/control.h
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-omap2/control.h | 2 | * arch/arm/mach-omap2/control.h |
| 3 | * | 3 | * |
| 4 | * OMAP2/3/4 System Control Module definitions | 4 | * OMAP2/3/4 System Control Module definitions |
| 5 | * | 5 | * |
| 6 | * Copyright (C) 2007-2010 Texas Instruments, Inc. | 6 | * Copyright (C) 2007-2010 Texas Instruments, Inc. |
| 7 | * Copyright (C) 2007-2008, 2010 Nokia Corporation | 7 | * Copyright (C) 2007-2008, 2010 Nokia Corporation |
| 8 | * | 8 | * |
| 9 | * Written by Paul Walmsley | 9 | * Written by Paul Walmsley |
| 10 | * | 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify | 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by | 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation. | 13 | * the Free Software Foundation. |
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H | 16 | #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H |
| 17 | #define __ARCH_ARM_MACH_OMAP2_CONTROL_H | 17 | #define __ARCH_ARM_MACH_OMAP2_CONTROL_H |
| 18 | 18 | ||
| 19 | #include <mach/ctrl_module_core_44xx.h> | 19 | #include "ctrl_module_core_44xx.h" |
| 20 | #include <mach/ctrl_module_wkup_44xx.h> | 20 | #include <mach/ctrl_module_wkup_44xx.h> |
| 21 | #include <mach/ctrl_module_pad_core_44xx.h> | 21 | #include <mach/ctrl_module_pad_core_44xx.h> |
| 22 | #include <mach/ctrl_module_pad_wkup_44xx.h> | 22 | #include <mach/ctrl_module_pad_wkup_44xx.h> |
| 23 | 23 | ||
| 24 | #include "am33xx.h" | 24 | #include "am33xx.h" |
| 25 | 25 | ||
| 26 | #ifndef __ASSEMBLY__ | 26 | #ifndef __ASSEMBLY__ |
| 27 | #define OMAP242X_CTRL_REGADDR(reg) \ | 27 | #define OMAP242X_CTRL_REGADDR(reg) \ |
| 28 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) | 28 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) |
| 29 | #define OMAP243X_CTRL_REGADDR(reg) \ | 29 | #define OMAP243X_CTRL_REGADDR(reg) \ |
| 30 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) | 30 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) |
| 31 | #define OMAP343X_CTRL_REGADDR(reg) \ | 31 | #define OMAP343X_CTRL_REGADDR(reg) \ |
| 32 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) | 32 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) |
| 33 | #define AM33XX_CTRL_REGADDR(reg) \ | 33 | #define AM33XX_CTRL_REGADDR(reg) \ |
| 34 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) | 34 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) |
| 35 | #else | 35 | #else |
| 36 | #define OMAP242X_CTRL_REGADDR(reg) \ | 36 | #define OMAP242X_CTRL_REGADDR(reg) \ |
| 37 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) | 37 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) |
| 38 | #define OMAP243X_CTRL_REGADDR(reg) \ | 38 | #define OMAP243X_CTRL_REGADDR(reg) \ |
| 39 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) | 39 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) |
| 40 | #define OMAP343X_CTRL_REGADDR(reg) \ | 40 | #define OMAP343X_CTRL_REGADDR(reg) \ |
| 41 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) | 41 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) |
| 42 | #define AM33XX_CTRL_REGADDR(reg) \ | 42 | #define AM33XX_CTRL_REGADDR(reg) \ |
| 43 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) | 43 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) |
| 44 | #endif /* __ASSEMBLY__ */ | 44 | #endif /* __ASSEMBLY__ */ |
| 45 | 45 | ||
| 46 | /* | 46 | /* |
| 47 | * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for | 47 | * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for |
| 48 | * OMAP24XX and OMAP34XX. | 48 | * OMAP24XX and OMAP34XX. |
| 49 | */ | 49 | */ |
| 50 | 50 | ||
| 51 | /* Control submodule offsets */ | 51 | /* Control submodule offsets */ |
| 52 | 52 | ||
| 53 | #define OMAP2_CONTROL_INTERFACE 0x000 | 53 | #define OMAP2_CONTROL_INTERFACE 0x000 |
| 54 | #define OMAP2_CONTROL_PADCONFS 0x030 | 54 | #define OMAP2_CONTROL_PADCONFS 0x030 |
| 55 | #define OMAP2_CONTROL_GENERAL 0x270 | 55 | #define OMAP2_CONTROL_GENERAL 0x270 |
| 56 | #define OMAP343X_CONTROL_MEM_WKUP 0x600 | 56 | #define OMAP343X_CONTROL_MEM_WKUP 0x600 |
| 57 | #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 | 57 | #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 |
| 58 | #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 | 58 | #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 |
| 59 | 59 | ||
| 60 | /* TI81XX spefic control submodules */ | 60 | /* TI81XX spefic control submodules */ |
| 61 | #define TI81XX_CONTROL_DEVCONF 0x600 | 61 | #define TI81XX_CONTROL_DEVCONF 0x600 |
| 62 | 62 | ||
| 63 | /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ | 63 | /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ |
| 64 | 64 | ||
| 65 | #define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) | 65 | #define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) |
| 66 | 66 | ||
| 67 | /* CONTROL_GENERAL register offsets common to OMAP2 & 3 */ | 67 | /* CONTROL_GENERAL register offsets common to OMAP2 & 3 */ |
| 68 | #define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004) | 68 | #define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004) |
| 69 | #define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020) | 69 | #define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020) |
| 70 | #define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024) | 70 | #define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024) |
| 71 | #define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028) | 71 | #define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028) |
| 72 | #define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c) | 72 | #define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c) |
| 73 | #define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030) | 73 | #define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030) |
| 74 | #define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034) | 74 | #define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034) |
| 75 | #define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040) | 75 | #define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040) |
| 76 | #define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090) | 76 | #define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090) |
| 77 | #define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094) | 77 | #define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094) |
| 78 | #define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098) | 78 | #define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098) |
| 79 | #define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c) | 79 | #define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c) |
| 80 | 80 | ||
| 81 | /* 242x-only CONTROL_GENERAL register offsets */ | 81 | /* 242x-only CONTROL_GENERAL register offsets */ |
| 82 | #define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */ | 82 | #define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */ |
| 83 | #define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068) | 83 | #define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068) |
| 84 | 84 | ||
| 85 | /* 243x-only CONTROL_GENERAL register offsets */ | 85 | /* 243x-only CONTROL_GENERAL register offsets */ |
| 86 | /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */ | 86 | /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */ |
| 87 | #define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078) | 87 | #define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078) |
| 88 | #define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c) | 88 | #define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c) |
| 89 | #define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) | 89 | #define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) |
| 90 | #define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) | 90 | #define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) |
| 91 | #define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198) | 91 | #define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198) |
| 92 | #define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230) | 92 | #define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230) |
| 93 | 93 | ||
| 94 | /* 24xx-only CONTROL_GENERAL register offsets */ | 94 | /* 24xx-only CONTROL_GENERAL register offsets */ |
| 95 | #define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000) | 95 | #define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000) |
| 96 | #define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008) | 96 | #define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008) |
| 97 | #define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044) | 97 | #define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044) |
| 98 | #define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048) | 98 | #define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048) |
| 99 | #define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c) | 99 | #define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c) |
| 100 | #define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050) | 100 | #define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050) |
| 101 | #define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060) | 101 | #define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060) |
| 102 | #define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064) | 102 | #define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064) |
| 103 | #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c) | 103 | #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c) |
| 104 | #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070) | 104 | #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070) |
| 105 | #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074) | 105 | #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074) |
| 106 | #define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) | 106 | #define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) |
| 107 | #define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) | 107 | #define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) |
| 108 | #define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088) | 108 | #define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088) |
| 109 | #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c) | 109 | #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c) |
| 110 | #define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0) | 110 | #define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0) |
| 111 | #define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4) | 111 | #define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4) |
| 112 | #define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8) | 112 | #define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8) |
| 113 | #define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac) | 113 | #define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac) |
| 114 | #define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0) | 114 | #define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0) |
| 115 | #define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4) | 115 | #define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4) |
| 116 | #define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0) | 116 | #define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0) |
| 117 | #define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4) | 117 | #define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4) |
| 118 | #define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8) | 118 | #define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8) |
| 119 | #define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc) | 119 | #define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc) |
| 120 | #define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0) | 120 | #define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0) |
| 121 | #define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4) | 121 | #define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4) |
| 122 | #define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8) | 122 | #define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8) |
| 123 | #define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc) | 123 | #define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc) |
| 124 | #define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) | 124 | #define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) |
| 125 | #define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) | 125 | #define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) |
| 126 | 126 | ||
| 127 | #define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0) | 127 | #define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0) |
| 128 | 128 | ||
| 129 | /* 34xx-only CONTROL_GENERAL register offsets */ | 129 | /* 34xx-only CONTROL_GENERAL register offsets */ |
| 130 | #define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) | 130 | #define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) |
| 131 | #define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) | 131 | #define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) |
| 132 | #define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c) | 132 | #define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c) |
| 133 | #define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068) | 133 | #define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068) |
| 134 | #define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c) | 134 | #define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c) |
| 135 | #define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070) | 135 | #define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070) |
| 136 | #define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074) | 136 | #define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074) |
| 137 | #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078) | 137 | #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078) |
| 138 | #define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) | 138 | #define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) |
| 139 | #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) | 139 | #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) |
| 140 | #define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0) | 140 | #define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0) |
| 141 | #define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8) | 141 | #define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8) |
| 142 | #define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac) | 142 | #define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac) |
| 143 | #define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0) | 143 | #define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0) |
| 144 | #define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4) | 144 | #define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4) |
| 145 | #define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8) | 145 | #define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8) |
| 146 | #define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc) | 146 | #define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc) |
| 147 | #define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0) | 147 | #define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0) |
| 148 | #define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4) | 148 | #define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4) |
| 149 | #define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8) | 149 | #define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8) |
| 150 | #define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc) | 150 | #define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc) |
| 151 | #define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0) | 151 | #define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0) |
| 152 | #define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4) | 152 | #define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4) |
| 153 | #define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8) | 153 | #define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8) |
| 154 | #define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec) | 154 | #define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec) |
| 155 | #define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0) | 155 | #define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0) |
| 156 | #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) | 156 | #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) |
| 157 | #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) | 157 | #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) |
| 158 | #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) | 158 | #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) |
| 159 | #define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) | 159 | #define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) |
| 160 | #define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) | 160 | #define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) |
| 161 | #define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) | 161 | #define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) |
| 162 | #define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c) | 162 | #define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c) |
| 163 | #define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) | 163 | #define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) |
| 164 | #define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124) | 164 | #define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124) |
| 165 | #define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) | 165 | #define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) |
| 166 | #define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c) | 166 | #define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c) |
| 167 | #define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130) | 167 | #define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130) |
| 168 | #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) | 168 | #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) |
| 169 | #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) | 169 | #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) |
| 170 | #define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ | 170 | #define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ |
| 171 | + ((i) >> 1) * 4 + (!((i) & 1)) * 2) | 171 | + ((i) >> 1) * 4 + (!((i) & 1)) * 2) |
| 172 | #define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4) | 172 | #define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4) |
| 173 | #define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8) | 173 | #define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8) |
| 174 | #define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0) | 174 | #define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0) |
| 175 | #define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4) | 175 | #define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4) |
| 176 | #define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8) | 176 | #define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8) |
| 177 | #define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC) | 177 | #define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC) |
| 178 | #define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0) | 178 | #define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0) |
| 179 | #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4) | 179 | #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4) |
| 180 | #define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8) | 180 | #define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8) |
| 181 | #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) | 181 | #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) |
| 182 | #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) | 182 | #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) |
| 183 | 183 | ||
| 184 | /* OMAP3630 only CONTROL_GENERAL register offsets */ | 184 | /* OMAP3630 only CONTROL_GENERAL register offsets */ |
| 185 | #define OMAP3630_CONTROL_FUSE_OPP1G_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) | 185 | #define OMAP3630_CONTROL_FUSE_OPP1G_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) |
| 186 | #define OMAP3630_CONTROL_FUSE_OPP50_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) | 186 | #define OMAP3630_CONTROL_FUSE_OPP50_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) |
| 187 | #define OMAP3630_CONTROL_FUSE_OPP100_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) | 187 | #define OMAP3630_CONTROL_FUSE_OPP100_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) |
| 188 | #define OMAP3630_CONTROL_FUSE_OPP120_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) | 188 | #define OMAP3630_CONTROL_FUSE_OPP120_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) |
| 189 | #define OMAP3630_CONTROL_FUSE_OPP50_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) | 189 | #define OMAP3630_CONTROL_FUSE_OPP50_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) |
| 190 | #define OMAP3630_CONTROL_FUSE_OPP100_VDD2 (OMAP2_CONTROL_GENERAL + 0x012C) | 190 | #define OMAP3630_CONTROL_FUSE_OPP100_VDD2 (OMAP2_CONTROL_GENERAL + 0x012C) |
| 191 | #define OMAP3630_CONTROL_CAMERA_PHY_CTRL (OMAP2_CONTROL_GENERAL + 0x02f0) | 191 | #define OMAP3630_CONTROL_CAMERA_PHY_CTRL (OMAP2_CONTROL_GENERAL + 0x02f0) |
| 192 | 192 | ||
| 193 | /* OMAP44xx control efuse offsets */ | 193 | /* OMAP44xx control efuse offsets */ |
| 194 | #define OMAP44XX_CONTROL_FUSE_IVA_OPP50 0x22C | 194 | #define OMAP44XX_CONTROL_FUSE_IVA_OPP50 0x22C |
| 195 | #define OMAP44XX_CONTROL_FUSE_IVA_OPP100 0x22F | 195 | #define OMAP44XX_CONTROL_FUSE_IVA_OPP100 0x22F |
| 196 | #define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO 0x232 | 196 | #define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO 0x232 |
| 197 | #define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO 0x235 | 197 | #define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO 0x235 |
| 198 | #define OMAP44XX_CONTROL_FUSE_MPU_OPP50 0x240 | 198 | #define OMAP44XX_CONTROL_FUSE_MPU_OPP50 0x240 |
| 199 | #define OMAP44XX_CONTROL_FUSE_MPU_OPP100 0x243 | 199 | #define OMAP44XX_CONTROL_FUSE_MPU_OPP100 0x243 |
| 200 | #define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO 0x246 | 200 | #define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO 0x246 |
| 201 | #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249 | 201 | #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249 |
| 202 | #define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254 | 202 | #define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254 |
| 203 | #define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257 | 203 | #define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257 |
| 204 | 204 | ||
| 205 | /* AM35XX only CONTROL_GENERAL register offsets */ | 205 | /* AM35XX only CONTROL_GENERAL register offsets */ |
| 206 | #define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038) | 206 | #define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038) |
| 207 | #define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310) | 207 | #define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310) |
| 208 | #define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314) | 208 | #define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314) |
| 209 | #define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320) | 209 | #define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320) |
| 210 | #define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324) | 210 | #define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324) |
| 211 | #define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328) | 211 | #define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328) |
| 212 | #define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C) | 212 | #define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C) |
| 213 | 213 | ||
| 214 | /* 34xx PADCONF register offsets */ | 214 | /* 34xx PADCONF register offsets */ |
| 215 | #define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \ | 215 | #define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \ |
| 216 | (i)*2) | 216 | (i)*2) |
| 217 | #define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0) | 217 | #define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0) |
| 218 | #define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1) | 218 | #define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1) |
| 219 | #define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2) | 219 | #define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2) |
| 220 | #define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3) | 220 | #define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3) |
| 221 | #define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4) | 221 | #define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4) |
| 222 | #define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5) | 222 | #define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5) |
| 223 | #define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6) | 223 | #define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6) |
| 224 | #define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7) | 224 | #define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7) |
| 225 | #define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8) | 225 | #define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8) |
| 226 | #define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9) | 226 | #define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9) |
| 227 | #define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10) | 227 | #define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10) |
| 228 | #define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11) | 228 | #define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11) |
| 229 | #define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12) | 229 | #define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12) |
| 230 | #define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13) | 230 | #define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13) |
| 231 | #define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14) | 231 | #define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14) |
| 232 | #define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15) | 232 | #define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15) |
| 233 | #define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16) | 233 | #define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16) |
| 234 | #define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17) | 234 | #define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17) |
| 235 | 235 | ||
| 236 | /* 34xx GENERAL_WKUP regist offsets */ | 236 | /* 34xx GENERAL_WKUP regist offsets */ |
| 237 | #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \ | 237 | #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \ |
| 238 | 0x008 + (i)) | 238 | 0x008 + (i)) |
| 239 | #define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008) | 239 | #define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008) |
| 240 | #define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C) | 240 | #define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C) |
| 241 | #define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010) | 241 | #define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010) |
| 242 | #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) | 242 | #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) |
| 243 | #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) | 243 | #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) |
| 244 | 244 | ||
| 245 | /* 36xx-only RTA - Retention till Access control registers and bits */ | 245 | /* 36xx-only RTA - Retention till Access control registers and bits */ |
| 246 | #define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C | 246 | #define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C |
| 247 | #define OMAP36XX_RTA_DISABLE 0x0 | 247 | #define OMAP36XX_RTA_DISABLE 0x0 |
| 248 | 248 | ||
| 249 | /* 34xx D2D idle-related pins, handled by PM core */ | 249 | /* 34xx D2D idle-related pins, handled by PM core */ |
| 250 | #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 | 250 | #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 |
| 251 | #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 | 251 | #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 |
| 252 | 252 | ||
| 253 | /* TI81XX CONTROL_DEVCONF register offsets */ | 253 | /* TI81XX CONTROL_DEVCONF register offsets */ |
| 254 | #define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000) | 254 | #define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000) |
| 255 | 255 | ||
| 256 | /* OMAP54XX CONTROL STATUS register */ | 256 | /* OMAP54XX CONTROL STATUS register */ |
| 257 | #define OMAP5XXX_CONTROL_STATUS 0x134 | 257 | #define OMAP5XXX_CONTROL_STATUS 0x134 |
| 258 | #define OMAP5_DEVICETYPE_MASK (0x7 << 6) | 258 | #define OMAP5_DEVICETYPE_MASK (0x7 << 6) |
| 259 | 259 | ||
| 260 | /* | 260 | /* |
| 261 | * REVISIT: This list of registers is not comprehensive - there are more | 261 | * REVISIT: This list of registers is not comprehensive - there are more |
| 262 | * that should be added. | 262 | * that should be added. |
| 263 | */ | 263 | */ |
| 264 | 264 | ||
| 265 | /* | 265 | /* |
| 266 | * Control module register bit defines - these should eventually go into | 266 | * Control module register bit defines - these should eventually go into |
| 267 | * their own regbits file. Some of these will be complicated, depending | 267 | * their own regbits file. Some of these will be complicated, depending |
| 268 | * on the device type (general-purpose, emulator, test, secure, bad, other) | 268 | * on the device type (general-purpose, emulator, test, secure, bad, other) |
| 269 | * and the security mode (secure, non-secure, don't care) | 269 | * and the security mode (secure, non-secure, don't care) |
| 270 | */ | 270 | */ |
| 271 | /* CONTROL_DEVCONF0 bits */ | 271 | /* CONTROL_DEVCONF0 bits */ |
| 272 | #define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */ | 272 | #define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */ |
| 273 | #define OMAP24XX_USBSTANDBYCTRL (1 << 15) | 273 | #define OMAP24XX_USBSTANDBYCTRL (1 << 15) |
| 274 | #define OMAP2_MCBSP2_CLKS_MASK (1 << 6) | 274 | #define OMAP2_MCBSP2_CLKS_MASK (1 << 6) |
| 275 | #define OMAP2_MCBSP1_FSR_MASK (1 << 4) | 275 | #define OMAP2_MCBSP1_FSR_MASK (1 << 4) |
| 276 | #define OMAP2_MCBSP1_CLKR_MASK (1 << 3) | 276 | #define OMAP2_MCBSP1_CLKR_MASK (1 << 3) |
| 277 | #define OMAP2_MCBSP1_CLKS_MASK (1 << 2) | 277 | #define OMAP2_MCBSP1_CLKS_MASK (1 << 2) |
| 278 | 278 | ||
| 279 | /* CONTROL_DEVCONF1 bits */ | 279 | /* CONTROL_DEVCONF1 bits */ |
| 280 | #define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31) | 280 | #define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31) |
| 281 | #define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */ | 281 | #define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */ |
| 282 | #define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */ | 282 | #define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */ |
| 283 | #define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */ | 283 | #define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */ |
| 284 | #define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */ | 284 | #define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */ |
| 285 | 285 | ||
| 286 | /* CONTROL_STATUS bits */ | 286 | /* CONTROL_STATUS bits */ |
| 287 | #define OMAP2_DEVICETYPE_MASK (0x7 << 8) | 287 | #define OMAP2_DEVICETYPE_MASK (0x7 << 8) |
| 288 | #define OMAP2_SYSBOOT_5_MASK (1 << 5) | 288 | #define OMAP2_SYSBOOT_5_MASK (1 << 5) |
| 289 | #define OMAP2_SYSBOOT_4_MASK (1 << 4) | 289 | #define OMAP2_SYSBOOT_4_MASK (1 << 4) |
| 290 | #define OMAP2_SYSBOOT_3_MASK (1 << 3) | 290 | #define OMAP2_SYSBOOT_3_MASK (1 << 3) |
| 291 | #define OMAP2_SYSBOOT_2_MASK (1 << 2) | 291 | #define OMAP2_SYSBOOT_2_MASK (1 << 2) |
| 292 | #define OMAP2_SYSBOOT_1_MASK (1 << 1) | 292 | #define OMAP2_SYSBOOT_1_MASK (1 << 1) |
| 293 | #define OMAP2_SYSBOOT_0_MASK (1 << 0) | 293 | #define OMAP2_SYSBOOT_0_MASK (1 << 0) |
| 294 | 294 | ||
| 295 | /* CONTROL_PBIAS_LITE bits */ | 295 | /* CONTROL_PBIAS_LITE bits */ |
| 296 | #define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15) | 296 | #define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15) |
| 297 | #define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11) | 297 | #define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11) |
| 298 | #define OMAP343X_PBIASSPEEDCTRL1 (1 << 10) | 298 | #define OMAP343X_PBIASSPEEDCTRL1 (1 << 10) |
| 299 | #define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9) | 299 | #define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9) |
| 300 | #define OMAP343X_PBIASLITEVMODE1 (1 << 8) | 300 | #define OMAP343X_PBIASLITEVMODE1 (1 << 8) |
| 301 | #define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7) | 301 | #define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7) |
| 302 | #define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3) | 302 | #define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3) |
| 303 | #define OMAP2_PBIASSPEEDCTRL0 (1 << 2) | 303 | #define OMAP2_PBIASSPEEDCTRL0 (1 << 2) |
| 304 | #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) | 304 | #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) |
| 305 | #define OMAP2_PBIASLITEVMODE0 (1 << 0) | 305 | #define OMAP2_PBIASLITEVMODE0 (1 << 0) |
| 306 | 306 | ||
| 307 | /* CONTROL_PROG_IO1 bits */ | 307 | /* CONTROL_PROG_IO1 bits */ |
| 308 | #define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) | 308 | #define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) |
| 309 | 309 | ||
| 310 | /* CONTROL_IVA2_BOOTMOD bits */ | 310 | /* CONTROL_IVA2_BOOTMOD bits */ |
| 311 | #define OMAP3_IVA2_BOOTMOD_SHIFT 0 | 311 | #define OMAP3_IVA2_BOOTMOD_SHIFT 0 |
| 312 | #define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0) | 312 | #define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0) |
| 313 | #define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0) | 313 | #define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0) |
| 314 | 314 | ||
| 315 | /* CONTROL_PADCONF_X bits */ | 315 | /* CONTROL_PADCONF_X bits */ |
| 316 | #define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) | 316 | #define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) |
| 317 | #define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) | 317 | #define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) |
| 318 | 318 | ||
| 319 | #define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) | 319 | #define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) |
| 320 | #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) | 320 | #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) |
| 321 | #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C | 321 | #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C |
| 322 | #define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\ | 322 | #define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\ |
| 323 | OMAP343X_SCRATCHPAD + reg) | 323 | OMAP343X_SCRATCHPAD + reg) |
| 324 | 324 | ||
| 325 | /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ | 325 | /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ |
| 326 | #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 | 326 | #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 |
| 327 | #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 | 327 | #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 |
| 328 | #define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 | 328 | #define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 |
| 329 | #define AM35XX_HECC_VBUSP_CLK_SHIFT 3 | 329 | #define AM35XX_HECC_VBUSP_CLK_SHIFT 3 |
| 330 | #define AM35XX_USBOTG_FCLK_SHIFT 8 | 330 | #define AM35XX_USBOTG_FCLK_SHIFT 8 |
| 331 | #define AM35XX_CPGMAC_FCLK_SHIFT 9 | 331 | #define AM35XX_CPGMAC_FCLK_SHIFT 9 |
| 332 | #define AM35XX_VPFE_FCLK_SHIFT 10 | 332 | #define AM35XX_VPFE_FCLK_SHIFT 10 |
| 333 | 333 | ||
| 334 | /* AM35XX CONTROL_LVL_INTR_CLEAR bits */ | 334 | /* AM35XX CONTROL_LVL_INTR_CLEAR bits */ |
| 335 | #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) | 335 | #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) |
| 336 | #define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) | 336 | #define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) |
| 337 | #define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) | 337 | #define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) |
| 338 | #define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3) | 338 | #define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3) |
| 339 | #define AM35XX_USBOTGSS_INT_CLR BIT(4) | 339 | #define AM35XX_USBOTGSS_INT_CLR BIT(4) |
| 340 | #define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5) | 340 | #define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5) |
| 341 | #define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) | 341 | #define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) |
| 342 | #define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) | 342 | #define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) |
| 343 | 343 | ||
| 344 | /* AM35XX CONTROL_IP_SW_RESET bits */ | 344 | /* AM35XX CONTROL_IP_SW_RESET bits */ |
| 345 | #define AM35XX_USBOTGSS_SW_RST BIT(0) | 345 | #define AM35XX_USBOTGSS_SW_RST BIT(0) |
| 346 | #define AM35XX_CPGMACSS_SW_RST BIT(1) | 346 | #define AM35XX_CPGMACSS_SW_RST BIT(1) |
| 347 | #define AM35XX_VPFE_VBUSP_SW_RST BIT(2) | 347 | #define AM35XX_VPFE_VBUSP_SW_RST BIT(2) |
| 348 | #define AM35XX_HECC_SW_RST BIT(3) | 348 | #define AM35XX_HECC_SW_RST BIT(3) |
| 349 | #define AM35XX_VPFE_PCLK_SW_RST BIT(4) | 349 | #define AM35XX_VPFE_PCLK_SW_RST BIT(4) |
| 350 | 350 | ||
| 351 | /* AM33XX CONTROL_STATUS register */ | 351 | /* AM33XX CONTROL_STATUS register */ |
| 352 | #define AM33XX_CONTROL_STATUS 0x040 | 352 | #define AM33XX_CONTROL_STATUS 0x040 |
| 353 | #define AM33XX_CONTROL_SEC_CLK_CTRL 0x1bc | 353 | #define AM33XX_CONTROL_SEC_CLK_CTRL 0x1bc |
| 354 | 354 | ||
| 355 | /* AM33XX CONTROL_STATUS bitfields (partial) */ | 355 | /* AM33XX CONTROL_STATUS bitfields (partial) */ |
| 356 | #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22 | 356 | #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22 |
| 357 | #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) | 357 | #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) |
| 358 | 358 | ||
| 359 | /* CONTROL OMAP STATUS register to identify OMAP3 features */ | 359 | /* CONTROL OMAP STATUS register to identify OMAP3 features */ |
| 360 | #define OMAP3_CONTROL_OMAP_STATUS 0x044c | 360 | #define OMAP3_CONTROL_OMAP_STATUS 0x044c |
| 361 | 361 | ||
| 362 | #define OMAP3_SGX_SHIFT 13 | 362 | #define OMAP3_SGX_SHIFT 13 |
| 363 | #define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT) | 363 | #define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT) |
| 364 | #define FEAT_SGX_FULL 0 | 364 | #define FEAT_SGX_FULL 0 |
| 365 | #define FEAT_SGX_HALF 1 | 365 | #define FEAT_SGX_HALF 1 |
| 366 | #define FEAT_SGX_NONE 2 | 366 | #define FEAT_SGX_NONE 2 |
| 367 | 367 | ||
| 368 | #define OMAP3_IVA_SHIFT 12 | 368 | #define OMAP3_IVA_SHIFT 12 |
| 369 | #define OMAP3_IVA_MASK (1 << OMAP3_IVA_SHIFT) | 369 | #define OMAP3_IVA_MASK (1 << OMAP3_IVA_SHIFT) |
| 370 | #define FEAT_IVA 0 | 370 | #define FEAT_IVA 0 |
| 371 | #define FEAT_IVA_NONE 1 | 371 | #define FEAT_IVA_NONE 1 |
| 372 | 372 | ||
| 373 | #define OMAP3_L2CACHE_SHIFT 10 | 373 | #define OMAP3_L2CACHE_SHIFT 10 |
| 374 | #define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT) | 374 | #define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT) |
| 375 | #define FEAT_L2CACHE_NONE 0 | 375 | #define FEAT_L2CACHE_NONE 0 |
| 376 | #define FEAT_L2CACHE_64KB 1 | 376 | #define FEAT_L2CACHE_64KB 1 |
| 377 | #define FEAT_L2CACHE_128KB 2 | 377 | #define FEAT_L2CACHE_128KB 2 |
| 378 | #define FEAT_L2CACHE_256KB 3 | 378 | #define FEAT_L2CACHE_256KB 3 |
| 379 | 379 | ||
| 380 | #define OMAP3_ISP_SHIFT 5 | 380 | #define OMAP3_ISP_SHIFT 5 |
| 381 | #define OMAP3_ISP_MASK (1 << OMAP3_ISP_SHIFT) | 381 | #define OMAP3_ISP_MASK (1 << OMAP3_ISP_SHIFT) |
| 382 | #define FEAT_ISP 0 | 382 | #define FEAT_ISP 0 |
| 383 | #define FEAT_ISP_NONE 1 | 383 | #define FEAT_ISP_NONE 1 |
| 384 | 384 | ||
| 385 | #define OMAP3_NEON_SHIFT 4 | 385 | #define OMAP3_NEON_SHIFT 4 |
| 386 | #define OMAP3_NEON_MASK (1 << OMAP3_NEON_SHIFT) | 386 | #define OMAP3_NEON_MASK (1 << OMAP3_NEON_SHIFT) |
| 387 | #define FEAT_NEON 0 | 387 | #define FEAT_NEON 0 |
| 388 | #define FEAT_NEON_NONE 1 | 388 | #define FEAT_NEON_NONE 1 |
| 389 | 389 | ||
| 390 | 390 | ||
| 391 | #ifndef __ASSEMBLY__ | 391 | #ifndef __ASSEMBLY__ |
| 392 | #ifdef CONFIG_ARCH_OMAP2PLUS | 392 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 393 | extern void __iomem *omap_ctrl_base_get(void); | 393 | extern void __iomem *omap_ctrl_base_get(void); |
| 394 | extern u8 omap_ctrl_readb(u16 offset); | 394 | extern u8 omap_ctrl_readb(u16 offset); |
| 395 | extern u16 omap_ctrl_readw(u16 offset); | 395 | extern u16 omap_ctrl_readw(u16 offset); |
| 396 | extern u32 omap_ctrl_readl(u16 offset); | 396 | extern u32 omap_ctrl_readl(u16 offset); |
| 397 | extern u32 omap4_ctrl_pad_readl(u16 offset); | 397 | extern u32 omap4_ctrl_pad_readl(u16 offset); |
| 398 | extern void omap_ctrl_writeb(u8 val, u16 offset); | 398 | extern void omap_ctrl_writeb(u8 val, u16 offset); |
| 399 | extern void omap_ctrl_writew(u16 val, u16 offset); | 399 | extern void omap_ctrl_writew(u16 val, u16 offset); |
| 400 | extern void omap_ctrl_writel(u32 val, u16 offset); | 400 | extern void omap_ctrl_writel(u32 val, u16 offset); |
| 401 | extern void omap4_ctrl_pad_writel(u32 val, u16 offset); | 401 | extern void omap4_ctrl_pad_writel(u32 val, u16 offset); |
| 402 | 402 | ||
| 403 | extern void omap3_save_scratchpad_contents(void); | 403 | extern void omap3_save_scratchpad_contents(void); |
| 404 | extern void omap3_clear_scratchpad_contents(void); | 404 | extern void omap3_clear_scratchpad_contents(void); |
| 405 | extern void omap3_restore(void); | 405 | extern void omap3_restore(void); |
| 406 | extern void omap3_restore_es3(void); | 406 | extern void omap3_restore_es3(void); |
| 407 | extern void omap3_restore_3630(void); | 407 | extern void omap3_restore_3630(void); |
| 408 | extern u32 omap3_arm_context[128]; | 408 | extern u32 omap3_arm_context[128]; |
| 409 | extern void omap3_control_save_context(void); | 409 | extern void omap3_control_save_context(void); |
| 410 | extern void omap3_control_restore_context(void); | 410 | extern void omap3_control_restore_context(void); |
| 411 | extern void omap3_ctrl_write_boot_mode(u8 bootmode); | 411 | extern void omap3_ctrl_write_boot_mode(u8 bootmode); |
| 412 | extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr); | 412 | extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr); |
| 413 | extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); | 413 | extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); |
| 414 | extern void omap3630_ctrl_disable_rta(void); | 414 | extern void omap3630_ctrl_disable_rta(void); |
| 415 | extern int omap3_ctrl_save_padconf(void); | 415 | extern int omap3_ctrl_save_padconf(void); |
| 416 | #else | 416 | #else |
| 417 | #define omap_ctrl_base_get() 0 | 417 | #define omap_ctrl_base_get() 0 |
| 418 | #define omap_ctrl_readb(x) 0 | 418 | #define omap_ctrl_readb(x) 0 |
| 419 | #define omap_ctrl_readw(x) 0 | 419 | #define omap_ctrl_readw(x) 0 |
| 420 | #define omap_ctrl_readl(x) 0 | 420 | #define omap_ctrl_readl(x) 0 |
| 421 | #define omap4_ctrl_pad_readl(x) 0 | 421 | #define omap4_ctrl_pad_readl(x) 0 |
| 422 | #define omap_ctrl_writeb(x, y) WARN_ON(1) | 422 | #define omap_ctrl_writeb(x, y) WARN_ON(1) |
| 423 | #define omap_ctrl_writew(x, y) WARN_ON(1) | 423 | #define omap_ctrl_writew(x, y) WARN_ON(1) |
| 424 | #define omap_ctrl_writel(x, y) WARN_ON(1) | 424 | #define omap_ctrl_writel(x, y) WARN_ON(1) |
| 425 | #define omap4_ctrl_pad_writel(x, y) WARN_ON(1) | 425 | #define omap4_ctrl_pad_writel(x, y) WARN_ON(1) |
| 426 | #endif | 426 | #endif |
| 427 | #endif /* __ASSEMBLY__ */ | 427 | #endif /* __ASSEMBLY__ */ |
| 428 | 428 | ||
| 429 | #endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */ | 429 | #endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */ |
| 430 | 430 | ||
| 431 | 431 |
arch/arm/mach-omap2/ctrl_module_core_44xx.h
| File was created | 1 | /* | |
| 2 | * OMAP44xx CTRL_MODULE_CORE registers and bitfields | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | ||
| 5 | * | ||
| 6 | * Benoit Cousson (b-cousson@ti.com) | ||
| 7 | * Santosh Shilimkar (santosh.shilimkar@ti.com) | ||
| 8 | * | ||
| 9 | * This file is automatically generated from the OMAP hardware databases. | ||
| 10 | * We respectfully ask that any modifications to this file be coordinated | ||
| 11 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
| 12 | * authors above to ensure that the autogeneration scripts are kept | ||
| 13 | * up-to-date with the file contents. | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License version 2 as | ||
| 17 | * published by the Free Software Foundation. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H | ||
| 21 | #define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H | ||
| 22 | |||
| 23 | |||
| 24 | /* Base address */ | ||
| 25 | #define OMAP4_CTRL_MODULE_CORE 0x4a002000 | ||
| 26 | |||
| 27 | /* Registers offset */ | ||
| 28 | #define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000 | ||
| 29 | #define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004 | ||
| 30 | #define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010 | ||
| 31 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200 | ||
| 32 | #define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204 | ||
| 33 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208 | ||
| 34 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c | ||
| 35 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210 | ||
| 36 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214 | ||
| 37 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218 | ||
| 38 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c | ||
| 39 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228 | ||
| 40 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260 | ||
| 41 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264 | ||
| 42 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268 | ||
| 43 | #define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4 | ||
| 44 | #define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300 | ||
| 45 | #define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304 | ||
| 46 | #define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314 | ||
| 47 | #define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318 | ||
| 48 | #define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320 | ||
| 49 | #define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324 | ||
| 50 | #define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328 | ||
| 51 | #define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c | ||
| 52 | #define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330 | ||
| 53 | #define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334 | ||
| 54 | #define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c | ||
| 55 | #define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340 | ||
| 56 | #define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350 | ||
| 57 | #define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400 | ||
| 58 | #define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408 | ||
| 59 | #define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c | ||
| 60 | #define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430 | ||
| 61 | #define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434 | ||
| 62 | #define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438 | ||
| 63 | #define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440 | ||
| 64 | #define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444 | ||
| 65 | #define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448 | ||
| 66 | #define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c | ||
| 67 | #define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450 | ||
| 68 | #define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454 | ||
| 69 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480 | ||
| 70 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484 | ||
| 71 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488 | ||
| 72 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c | ||
| 73 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490 | ||
| 74 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494 | ||
| 75 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498 | ||
| 76 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c | ||
| 77 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0 | ||
| 78 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4 | ||
| 79 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8 | ||
| 80 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac | ||
| 81 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0 | ||
| 82 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4 | ||
| 83 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8 | ||
| 84 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc | ||
| 85 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0 | ||
| 86 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4 | ||
| 87 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8 | ||
| 88 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc | ||
| 89 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0 | ||
| 90 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4 | ||
| 91 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8 | ||
| 92 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc | ||
| 93 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0 | ||
| 94 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4 | ||
| 95 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8 | ||
| 96 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec | ||
| 97 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0 | ||
| 98 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4 | ||
| 99 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8 | ||
| 100 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc | ||
| 101 | |||
| 102 | /* Registers shifts and masks */ | ||
| 103 | |||
| 104 | /* IP_REVISION */ | ||
| 105 | #define OMAP4_IP_REV_SCHEME_SHIFT 30 | ||
| 106 | #define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) | ||
| 107 | #define OMAP4_IP_REV_FUNC_SHIFT 16 | ||
| 108 | #define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) | ||
| 109 | #define OMAP4_IP_REV_RTL_SHIFT 11 | ||
| 110 | #define OMAP4_IP_REV_RTL_MASK (0x1f << 11) | ||
| 111 | #define OMAP4_IP_REV_MAJOR_SHIFT 8 | ||
| 112 | #define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) | ||
| 113 | #define OMAP4_IP_REV_CUSTOM_SHIFT 6 | ||
| 114 | #define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) | ||
| 115 | #define OMAP4_IP_REV_MINOR_SHIFT 0 | ||
| 116 | #define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) | ||
| 117 | |||
| 118 | /* IP_HWINFO */ | ||
| 119 | #define OMAP4_IP_HWINFO_SHIFT 0 | ||
| 120 | #define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) | ||
| 121 | |||
| 122 | /* IP_SYSCONFIG */ | ||
| 123 | #define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 | ||
| 124 | #define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) | ||
| 125 | |||
| 126 | /* STD_FUSE_DIE_ID_0 */ | ||
| 127 | #define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0 | ||
| 128 | #define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0) | ||
| 129 | |||
| 130 | /* ID_CODE */ | ||
| 131 | #define OMAP4_STD_FUSE_IDCODE_SHIFT 0 | ||
| 132 | #define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0) | ||
| 133 | |||
| 134 | /* STD_FUSE_DIE_ID_1 */ | ||
| 135 | #define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0 | ||
| 136 | #define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0) | ||
| 137 | |||
| 138 | /* STD_FUSE_DIE_ID_2 */ | ||
| 139 | #define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0 | ||
| 140 | #define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0) | ||
| 141 | |||
| 142 | /* STD_FUSE_DIE_ID_3 */ | ||
| 143 | #define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0 | ||
| 144 | #define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0) | ||
| 145 | |||
| 146 | /* STD_FUSE_PROD_ID_0 */ | ||
| 147 | #define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0 | ||
| 148 | #define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0) | ||
| 149 | |||
| 150 | /* STD_FUSE_PROD_ID_1 */ | ||
| 151 | #define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0 | ||
| 152 | #define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0) | ||
| 153 | |||
| 154 | /* STD_FUSE_USB_CONF */ | ||
| 155 | #define OMAP4_USB_PROD_ID_SHIFT 16 | ||
| 156 | #define OMAP4_USB_PROD_ID_MASK (0xffff << 16) | ||
| 157 | #define OMAP4_USB_VENDOR_ID_SHIFT 0 | ||
| 158 | #define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0) | ||
| 159 | |||
| 160 | /* STD_FUSE_OPP_VDD_WKUP */ | ||
| 161 | #define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0 | ||
| 162 | #define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0) | ||
| 163 | |||
| 164 | /* STD_FUSE_OPP_BGAP */ | ||
| 165 | #define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0 | ||
| 166 | #define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0) | ||
| 167 | |||
| 168 | /* STD_FUSE_OPP_DPLL_0 */ | ||
| 169 | #define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0 | ||
| 170 | #define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0) | ||
| 171 | |||
| 172 | /* STD_FUSE_OPP_DPLL_1 */ | ||
| 173 | #define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0 | ||
| 174 | #define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0) | ||
| 175 | |||
| 176 | /* STATUS */ | ||
| 177 | #define OMAP4_ATTILA_CONF_SHIFT 11 | ||
| 178 | #define OMAP4_ATTILA_CONF_MASK (0x3 << 11) | ||
| 179 | #define OMAP4_DEVICE_TYPE_SHIFT 8 | ||
| 180 | #define OMAP4_DEVICE_TYPE_MASK (0x7 << 8) | ||
| 181 | #define OMAP4_SYS_BOOT_SHIFT 0 | ||
| 182 | #define OMAP4_SYS_BOOT_MASK (0xff << 0) | ||
| 183 | |||
| 184 | /* DEV_CONF */ | ||
| 185 | #define OMAP4_DEV_CONF_SHIFT 1 | ||
| 186 | #define OMAP4_DEV_CONF_MASK (0x7fffffff << 1) | ||
| 187 | #define OMAP4_USBPHY_PD_SHIFT 0 | ||
| 188 | #define OMAP4_USBPHY_PD_MASK (1 << 0) | ||
| 189 | |||
| 190 | /* LDOVBB_IVA_VOLTAGE_CTRL */ | ||
| 191 | #define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26 | ||
| 192 | #define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26) | ||
| 193 | #define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21 | ||
| 194 | #define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21) | ||
| 195 | #define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16 | ||
| 196 | #define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16) | ||
| 197 | #define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10 | ||
| 198 | #define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10) | ||
| 199 | #define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5 | ||
| 200 | #define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5) | ||
| 201 | #define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0 | ||
| 202 | #define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0) | ||
| 203 | |||
| 204 | /* LDOVBB_MPU_VOLTAGE_CTRL */ | ||
| 205 | #define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26 | ||
| 206 | #define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26) | ||
| 207 | #define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21 | ||
| 208 | #define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21) | ||
| 209 | #define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16 | ||
| 210 | #define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16) | ||
| 211 | #define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10 | ||
| 212 | #define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10) | ||
| 213 | #define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5 | ||
| 214 | #define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5) | ||
| 215 | #define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0 | ||
| 216 | #define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0) | ||
| 217 | |||
| 218 | /* LDOSRAM_IVA_VOLTAGE_CTRL */ | ||
| 219 | #define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26 | ||
| 220 | #define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26) | ||
| 221 | #define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21 | ||
| 222 | #define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21) | ||
| 223 | #define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16 | ||
| 224 | #define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16) | ||
| 225 | #define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10 | ||
| 226 | #define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10) | ||
| 227 | #define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5 | ||
| 228 | #define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5) | ||
| 229 | #define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0 | ||
| 230 | #define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0) | ||
| 231 | |||
| 232 | /* LDOSRAM_MPU_VOLTAGE_CTRL */ | ||
| 233 | #define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26 | ||
| 234 | #define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26) | ||
| 235 | #define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21 | ||
| 236 | #define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21) | ||
| 237 | #define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16 | ||
| 238 | #define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16) | ||
| 239 | #define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10 | ||
| 240 | #define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10) | ||
| 241 | #define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5 | ||
| 242 | #define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5) | ||
| 243 | #define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0 | ||
| 244 | #define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0) | ||
| 245 | |||
| 246 | /* LDOSRAM_CORE_VOLTAGE_CTRL */ | ||
| 247 | #define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26 | ||
| 248 | #define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26) | ||
| 249 | #define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21 | ||
| 250 | #define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21) | ||
| 251 | #define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16 | ||
| 252 | #define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16) | ||
| 253 | #define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10 | ||
| 254 | #define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10) | ||
| 255 | #define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5 | ||
| 256 | #define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5) | ||
| 257 | #define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0 | ||
| 258 | #define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0) | ||
| 259 | |||
| 260 | /* TEMP_SENSOR */ | ||
| 261 | #define OMAP4_BGAP_TEMPSOFF_SHIFT 12 | ||
| 262 | #define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12) | ||
| 263 | #define OMAP4_BGAP_TSHUT_SHIFT 11 | ||
| 264 | #define OMAP4_BGAP_TSHUT_MASK (1 << 11) | ||
| 265 | #define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10 | ||
| 266 | #define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10) | ||
| 267 | #define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9 | ||
| 268 | #define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9) | ||
| 269 | #define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8 | ||
| 270 | #define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8) | ||
| 271 | #define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0 | ||
| 272 | #define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0) | ||
| 273 | |||
| 274 | /* DPLL_NWELL_TRIM_0 */ | ||
| 275 | #define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29 | ||
| 276 | #define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29) | ||
| 277 | #define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24 | ||
| 278 | #define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24) | ||
| 279 | #define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23 | ||
| 280 | #define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23) | ||
| 281 | #define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18 | ||
| 282 | #define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18) | ||
| 283 | #define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17 | ||
| 284 | #define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17) | ||
| 285 | #define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12 | ||
| 286 | #define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12) | ||
| 287 | #define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11 | ||
| 288 | #define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11) | ||
| 289 | #define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6 | ||
| 290 | #define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6) | ||
| 291 | #define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5 | ||
| 292 | #define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5) | ||
| 293 | #define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0 | ||
| 294 | #define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0) | ||
| 295 | |||
| 296 | /* DPLL_NWELL_TRIM_1 */ | ||
| 297 | #define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29 | ||
| 298 | #define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29) | ||
| 299 | #define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24 | ||
| 300 | #define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24) | ||
| 301 | #define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23 | ||
| 302 | #define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23) | ||
| 303 | #define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18 | ||
| 304 | #define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18) | ||
| 305 | #define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17 | ||
| 306 | #define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17) | ||
| 307 | #define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12 | ||
| 308 | #define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12) | ||
| 309 | #define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11 | ||
| 310 | #define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11) | ||
| 311 | #define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6 | ||
| 312 | #define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6) | ||
| 313 | #define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5 | ||
| 314 | #define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5) | ||
| 315 | #define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0 | ||
| 316 | #define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0) | ||
| 317 | |||
| 318 | /* USBOTGHS_CONTROL */ | ||
| 319 | #define OMAP4_DISCHRGVBUS_SHIFT 8 | ||
| 320 | #define OMAP4_DISCHRGVBUS_MASK (1 << 8) | ||
| 321 | #define OMAP4_CHRGVBUS_SHIFT 7 | ||
| 322 | #define OMAP4_CHRGVBUS_MASK (1 << 7) | ||
| 323 | #define OMAP4_DRVVBUS_SHIFT 6 | ||
| 324 | #define OMAP4_DRVVBUS_MASK (1 << 6) | ||
| 325 | #define OMAP4_IDPULLUP_SHIFT 5 | ||
| 326 | #define OMAP4_IDPULLUP_MASK (1 << 5) | ||
| 327 | #define OMAP4_IDDIG_SHIFT 4 | ||
| 328 | #define OMAP4_IDDIG_MASK (1 << 4) | ||
| 329 | #define OMAP4_SESSEND_SHIFT 3 | ||
| 330 | #define OMAP4_SESSEND_MASK (1 << 3) | ||
| 331 | #define OMAP4_VBUSVALID_SHIFT 2 | ||
| 332 | #define OMAP4_VBUSVALID_MASK (1 << 2) | ||
| 333 | #define OMAP4_BVALID_SHIFT 1 | ||
| 334 | #define OMAP4_BVALID_MASK (1 << 1) | ||
| 335 | #define OMAP4_AVALID_SHIFT 0 | ||
| 336 | #define OMAP4_AVALID_MASK (1 << 0) | ||
| 337 | |||
| 338 | /* DSS_CONTROL */ | ||
| 339 | #define OMAP4_DSS_MUX6_SELECT_SHIFT 0 | ||
| 340 | #define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0) | ||
| 341 | |||
| 342 | /* HWOBS_CONTROL */ | ||
| 343 | #define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3 | ||
| 344 | #define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3) | ||
| 345 | #define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2 | ||
| 346 | #define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2) | ||
| 347 | #define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1 | ||
| 348 | #define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1) | ||
| 349 | #define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0 | ||
| 350 | #define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0) | ||
| 351 | |||
| 352 | /* DEBOBS_FINAL_MUX_SEL */ | ||
| 353 | #define OMAP4_SELECT_SHIFT 0 | ||
| 354 | #define OMAP4_SELECT_MASK (0xffffffff << 0) | ||
| 355 | |||
| 356 | /* DEBOBS_MMR_MPU */ | ||
| 357 | #define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0 | ||
| 358 | #define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0) | ||
| 359 | |||
| 360 | /* CONF_SDMA_REQ_SEL0 */ | ||
| 361 | #define OMAP4_MULT_SHIFT 0 | ||
| 362 | #define OMAP4_MULT_MASK (0x7f << 0) | ||
| 363 | |||
| 364 | /* CONF_CLK_SEL0 */ | ||
| 365 | #define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0 | ||
| 366 | #define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0) | ||
| 367 | |||
| 368 | /* CONF_CLK_SEL1 */ | ||
| 369 | #define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0 | ||
| 370 | #define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0) | ||
| 371 | |||
| 372 | /* CONF_CLK_SEL2 */ | ||
| 373 | #define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0 | ||
| 374 | #define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0) | ||
| 375 | |||
| 376 | /* CONF_DPLL_FREQLOCK_SEL */ | ||
| 377 | #define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0 | ||
| 378 | #define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0) | ||
| 379 | |||
| 380 | /* CONF_DPLL_TINITZ_SEL */ | ||
| 381 | #define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0 | ||
| 382 | #define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0) | ||
| 383 | |||
| 384 | /* CONF_DPLL_PHASELOCK_SEL */ | ||
| 385 | #define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0 | ||
| 386 | #define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0) | ||
| 387 | |||
| 388 | /* CONF_DEBUG_SEL_TST_0 */ | ||
| 389 | #define OMAP4_MODE_SHIFT 0 | ||
| 390 | #define OMAP4_MODE_MASK (0xf << 0) | ||
| 391 | |||
| 392 | #endif | ||
| 393 |
arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
| 1 | /* | File was deleted | |
| 2 | * OMAP44xx CTRL_MODULE_CORE registers and bitfields | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | ||
| 5 | * | ||
| 6 | * Benoit Cousson (b-cousson@ti.com) | ||
| 7 | * Santosh Shilimkar (santosh.shilimkar@ti.com) | ||
| 8 | * | ||
| 9 | * This file is automatically generated from the OMAP hardware databases. | ||
| 10 | * We respectfully ask that any modifications to this file be coordinated | ||
| 11 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
| 12 | * authors above to ensure that the autogeneration scripts are kept | ||
| 13 | * up-to-date with the file contents. | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License version 2 as | ||
| 17 | * published by the Free Software Foundation. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H | ||
| 21 | #define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H | ||
| 22 | |||
| 23 | |||
| 24 | /* Base address */ | ||
| 25 | #define OMAP4_CTRL_MODULE_CORE 0x4a002000 | ||
| 26 | |||
| 27 | /* Registers offset */ | ||
| 28 | #define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000 | ||
| 29 | #define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004 | ||
| 30 | #define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010 | ||
| 31 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200 | ||
| 32 | #define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204 | ||
| 33 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208 | ||
| 34 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c | ||
| 35 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210 | ||
| 36 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214 | ||
| 37 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218 | ||
| 38 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c | ||
| 39 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228 | ||
| 40 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260 | ||
| 41 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264 | ||
| 42 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268 | ||
| 43 | #define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4 | ||
| 44 | #define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300 | ||
| 45 | #define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304 | ||
| 46 | #define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314 | ||
| 47 | #define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318 | ||
| 48 | #define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320 | ||
| 49 | #define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324 | ||
| 50 | #define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328 | ||
| 51 | #define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c | ||
| 52 | #define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330 | ||
| 53 | #define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334 | ||
| 54 | #define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c | ||
| 55 | #define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340 | ||
| 56 | #define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350 | ||
| 57 | #define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400 | ||
| 58 | #define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408 | ||
| 59 | #define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c | ||
| 60 | #define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430 | ||
| 61 | #define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434 | ||
| 62 | #define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438 | ||
| 63 | #define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440 | ||
| 64 | #define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444 | ||
| 65 | #define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448 | ||
| 66 | #define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c | ||
| 67 | #define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450 | ||
| 68 | #define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454 | ||
| 69 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480 | ||
| 70 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484 | ||
| 71 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488 | ||
| 72 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c | ||
| 73 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490 | ||
| 74 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494 | ||
| 75 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498 | ||
| 76 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c | ||
| 77 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0 | ||
| 78 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4 | ||
| 79 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8 | ||
| 80 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac | ||
| 81 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0 | ||
| 82 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4 | ||
| 83 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8 | ||
| 84 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc | ||
| 85 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0 | ||
| 86 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4 | ||
| 87 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8 | ||
| 88 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc | ||
| 89 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0 | ||
| 90 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4 | ||
| 91 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8 | ||
| 92 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc | ||
| 93 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0 | ||
| 94 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4 | ||
| 95 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8 | ||
| 96 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec | ||
| 97 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0 | ||
| 98 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4 | ||
| 99 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8 | ||
| 100 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc | ||
| 101 | |||
| 102 | /* Registers shifts and masks */ | ||
| 103 | |||
| 104 | /* IP_REVISION */ | ||
| 105 | #define OMAP4_IP_REV_SCHEME_SHIFT 30 | ||
| 106 | #define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) | ||
| 107 | #define OMAP4_IP_REV_FUNC_SHIFT 16 | ||
| 108 | #define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) | ||
| 109 | #define OMAP4_IP_REV_RTL_SHIFT 11 | ||
| 110 | #define OMAP4_IP_REV_RTL_MASK (0x1f << 11) | ||
| 111 | #define OMAP4_IP_REV_MAJOR_SHIFT 8 | ||
| 112 | #define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) | ||
| 113 | #define OMAP4_IP_REV_CUSTOM_SHIFT 6 | ||
| 114 | #define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) | ||
| 115 | #define OMAP4_IP_REV_MINOR_SHIFT 0 | ||
| 116 | #define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) | ||
| 117 | |||
| 118 | /* IP_HWINFO */ | ||
| 119 | #define OMAP4_IP_HWINFO_SHIFT 0 | ||
| 120 | #define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) | ||
| 121 | |||
| 122 | /* IP_SYSCONFIG */ | ||
| 123 | #define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 | ||
| 124 | #define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) | ||
| 125 | |||
| 126 | /* STD_FUSE_DIE_ID_0 */ | ||
| 127 | #define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0 | ||
| 128 | #define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0) | ||
| 129 | |||
| 130 | /* ID_CODE */ | ||
| 131 | #define OMAP4_STD_FUSE_IDCODE_SHIFT 0 | ||
| 132 | #define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0) | ||
| 133 | |||
| 134 | /* STD_FUSE_DIE_ID_1 */ | ||
| 135 | #define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0 | ||
| 136 | #define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0) | ||
| 137 | |||
| 138 | /* STD_FUSE_DIE_ID_2 */ | ||
| 139 | #define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0 | ||
| 140 | #define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0) | ||
| 141 | |||
| 142 | /* STD_FUSE_DIE_ID_3 */ | ||
| 143 | #define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0 | ||
| 144 | #define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0) | ||
| 145 | |||
| 146 | /* STD_FUSE_PROD_ID_0 */ | ||
| 147 | #define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0 | ||
| 148 | #define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0) | ||
| 149 | |||
| 150 | /* STD_FUSE_PROD_ID_1 */ | ||
| 151 | #define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0 | ||
| 152 | #define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0) | ||
| 153 | |||
| 154 | /* STD_FUSE_USB_CONF */ | ||
| 155 | #define OMAP4_USB_PROD_ID_SHIFT 16 | ||
| 156 | #define OMAP4_USB_PROD_ID_MASK (0xffff << 16) | ||
| 157 | #define OMAP4_USB_VENDOR_ID_SHIFT 0 | ||
| 158 | #define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0) | ||
| 159 | |||
| 160 | /* STD_FUSE_OPP_VDD_WKUP */ | ||
| 161 | #define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0 | ||
| 162 | #define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0) | ||
| 163 | |||
| 164 | /* STD_FUSE_OPP_BGAP */ | ||
| 165 | #define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0 | ||
| 166 | #define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0) | ||
| 167 | |||
| 168 | /* STD_FUSE_OPP_DPLL_0 */ | ||
| 169 | #define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0 | ||
| 170 | #define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0) | ||
| 171 | |||
| 172 | /* STD_FUSE_OPP_DPLL_1 */ | ||
| 173 | #define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0 | ||
| 174 | #define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0) | ||
| 175 | |||
| 176 | /* STATUS */ | ||
| 177 | #define OMAP4_ATTILA_CONF_SHIFT 11 | ||
| 178 | #define OMAP4_ATTILA_CONF_MASK (0x3 << 11) | ||
| 179 | #define OMAP4_DEVICE_TYPE_SHIFT 8 | ||
| 180 | #define OMAP4_DEVICE_TYPE_MASK (0x7 << 8) | ||
| 181 | #define OMAP4_SYS_BOOT_SHIFT 0 | ||
| 182 | #define OMAP4_SYS_BOOT_MASK (0xff << 0) | ||
| 183 | |||
| 184 | /* DEV_CONF */ | ||
| 185 | #define OMAP4_DEV_CONF_SHIFT 1 | ||
| 186 | #define OMAP4_DEV_CONF_MASK (0x7fffffff << 1) | ||
| 187 | #define OMAP4_USBPHY_PD_SHIFT 0 | ||
| 188 | #define OMAP4_USBPHY_PD_MASK (1 << 0) | ||
| 189 | |||
| 190 | /* LDOVBB_IVA_VOLTAGE_CTRL */ | ||
| 191 | #define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26 | ||
| 192 | #define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26) | ||
| 193 | #define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21 | ||
| 194 | #define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21) | ||
| 195 | #define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16 | ||
| 196 | #define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16) | ||
| 197 | #define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10 | ||
| 198 | #define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10) | ||
| 199 | #define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5 | ||
| 200 | #define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5) | ||
| 201 | #define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0 | ||
| 202 | #define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0) | ||
| 203 | |||
| 204 | /* LDOVBB_MPU_VOLTAGE_CTRL */ | ||
| 205 | #define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26 | ||
| 206 | #define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26) | ||
| 207 | #define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21 | ||
| 208 | #define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21) | ||
| 209 | #define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16 | ||
| 210 | #define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16) | ||
| 211 | #define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10 | ||
| 212 | #define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10) | ||
| 213 | #define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5 | ||
| 214 | #define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5) | ||
| 215 | #define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0 | ||
| 216 | #define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0) | ||
| 217 | |||
| 218 | /* LDOSRAM_IVA_VOLTAGE_CTRL */ | ||
| 219 | #define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26 | ||
| 220 | #define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26) | ||
| 221 | #define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21 | ||
| 222 | #define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21) | ||
| 223 | #define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16 | ||
| 224 | #define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16) | ||
| 225 | #define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10 | ||
| 226 | #define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10) | ||
| 227 | #define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5 | ||
| 228 | #define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5) | ||
| 229 | #define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0 | ||
| 230 | #define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0) | ||
| 231 | |||
| 232 | /* LDOSRAM_MPU_VOLTAGE_CTRL */ | ||
| 233 | #define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26 | ||
| 234 | #define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26) | ||
| 235 | #define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21 | ||
| 236 | #define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21) | ||
| 237 | #define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16 | ||
| 238 | #define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16) | ||
| 239 | #define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10 | ||
| 240 | #define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10) | ||
| 241 | #define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5 | ||
| 242 | #define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5) | ||
| 243 | #define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0 | ||
| 244 | #define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0) | ||
| 245 | |||
| 246 | /* LDOSRAM_CORE_VOLTAGE_CTRL */ | ||
| 247 | #define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26 | ||
| 248 | #define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26) | ||
| 249 | #define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21 | ||
| 250 | #define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21) | ||
| 251 | #define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16 | ||
| 252 | #define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16) | ||
| 253 | #define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10 | ||
| 254 | #define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10) | ||
| 255 | #define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5 | ||
| 256 | #define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5) | ||
| 257 | #define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0 | ||
| 258 | #define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0) | ||
| 259 | |||
| 260 | /* TEMP_SENSOR */ | ||
| 261 | #define OMAP4_BGAP_TEMPSOFF_SHIFT 12 | ||
| 262 | #define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12) | ||
| 263 | #define OMAP4_BGAP_TSHUT_SHIFT 11 | ||
| 264 | #define OMAP4_BGAP_TSHUT_MASK (1 << 11) | ||
| 265 | #define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10 | ||
| 266 | #define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10) | ||
| 267 | #define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9 | ||
| 268 | #define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9) | ||
| 269 | #define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8 | ||
| 270 | #define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8) | ||
| 271 | #define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0 | ||
| 272 | #define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0) | ||
| 273 | |||
| 274 | /* DPLL_NWELL_TRIM_0 */ | ||
| 275 | #define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29 | ||
| 276 | #define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29) | ||
| 277 | #define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24 | ||
| 278 | #define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24) | ||
| 279 | #define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23 | ||
| 280 | #define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23) | ||
| 281 | #define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18 | ||
| 282 | #define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18) | ||
| 283 | #define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17 | ||
| 284 | #define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17) | ||
| 285 | #define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12 | ||
| 286 | #define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12) | ||
| 287 | #define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11 | ||
| 288 | #define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11) | ||
| 289 | #define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6 | ||
| 290 | #define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6) | ||
| 291 | #define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5 | ||
| 292 | #define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5) | ||
| 293 | #define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0 | ||
| 294 | #define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0) | ||
| 295 | |||
| 296 | /* DPLL_NWELL_TRIM_1 */ | ||
| 297 | #define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29 | ||
| 298 | #define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29) | ||
| 299 | #define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24 | ||
| 300 | #define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24) | ||
| 301 | #define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23 | ||
| 302 | #define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23) | ||
| 303 | #define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18 | ||
| 304 | #define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18) | ||
| 305 | #define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17 | ||
| 306 | #define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17) | ||
| 307 | #define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12 | ||
| 308 | #define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12) | ||
| 309 | #define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11 | ||
| 310 | #define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11) | ||
| 311 | #define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6 | ||
| 312 | #define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6) | ||
| 313 | #define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5 | ||
| 314 | #define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5) | ||
| 315 | #define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0 | ||
| 316 | #define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0) | ||
| 317 | |||
| 318 | /* USBOTGHS_CONTROL */ | ||
| 319 | #define OMAP4_DISCHRGVBUS_SHIFT 8 | ||
| 320 | #define OMAP4_DISCHRGVBUS_MASK (1 << 8) | ||
| 321 | #define OMAP4_CHRGVBUS_SHIFT 7 | ||
| 322 | #define OMAP4_CHRGVBUS_MASK (1 << 7) | ||
| 323 | #define OMAP4_DRVVBUS_SHIFT 6 | ||
| 324 | #define OMAP4_DRVVBUS_MASK (1 << 6) | ||
| 325 | #define OMAP4_IDPULLUP_SHIFT 5 | ||
| 326 | #define OMAP4_IDPULLUP_MASK (1 << 5) | ||
| 327 | #define OMAP4_IDDIG_SHIFT 4 | ||
| 328 | #define OMAP4_IDDIG_MASK (1 << 4) | ||
| 329 | #define OMAP4_SESSEND_SHIFT 3 | ||
| 330 | #define OMAP4_SESSEND_MASK (1 << 3) | ||
| 331 | #define OMAP4_VBUSVALID_SHIFT 2 | ||
| 332 | #define OMAP4_VBUSVALID_MASK (1 << 2) | ||
| 333 | #define OMAP4_BVALID_SHIFT 1 | ||
| 334 | #define OMAP4_BVALID_MASK (1 << 1) | ||
| 335 | #define OMAP4_AVALID_SHIFT 0 | ||
| 336 | #define OMAP4_AVALID_MASK (1 << 0) | ||
| 337 | |||
| 338 | /* DSS_CONTROL */ | ||
| 339 | #define OMAP4_DSS_MUX6_SELECT_SHIFT 0 | ||
| 340 | #define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0) | ||
| 341 | |||
| 342 | /* HWOBS_CONTROL */ | ||
| 343 | #define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3 | ||
| 344 | #define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3) | ||
| 345 | #define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2 | ||
| 346 | #define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2) | ||
| 347 | #define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1 | ||
| 348 | #define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1) | ||
| 349 | #define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0 | ||
| 350 | #define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0) | ||
| 351 | |||
| 352 | /* DEBOBS_FINAL_MUX_SEL */ | ||
| 353 | #define OMAP4_SELECT_SHIFT 0 | ||
| 354 | #define OMAP4_SELECT_MASK (0xffffffff << 0) | ||
| 355 | |||
| 356 | /* DEBOBS_MMR_MPU */ | ||
| 357 | #define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0 | ||
| 358 | #define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0) | ||
| 359 | |||
| 360 | /* CONF_SDMA_REQ_SEL0 */ | ||
| 361 | #define OMAP4_MULT_SHIFT 0 | ||
| 362 | #define OMAP4_MULT_MASK (0x7f << 0) | ||
| 363 | |||
| 364 | /* CONF_CLK_SEL0 */ | ||
| 365 | #define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0 | ||
| 366 | #define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0) | ||
| 367 | |||
| 368 | /* CONF_CLK_SEL1 */ | ||
| 369 | #define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0 | ||
| 370 | #define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0) | ||
| 371 | |||
| 372 | /* CONF_CLK_SEL2 */ | ||
| 373 | #define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0 | ||
| 374 | #define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0) | ||
| 375 | |||
| 376 | /* CONF_DPLL_FREQLOCK_SEL */ | ||
| 377 | #define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0 | ||
| 378 | #define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0) | ||
| 379 | |||
| 380 | /* CONF_DPLL_TINITZ_SEL */ | ||
| 381 | #define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0 | ||
| 382 | #define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0) | ||
| 383 | |||
| 384 | /* CONF_DPLL_PHASELOCK_SEL */ | ||
| 385 | #define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0 | ||
| 386 | #define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0) | ||
| 387 | |||
| 388 | /* CONF_DEBUG_SEL_TST_0 */ | ||
| 389 | #define OMAP4_MODE_SHIFT 0 | ||
| 390 | #define OMAP4_MODE_MASK (0xf << 0) | ||
| 391 | |||
| 392 | #endif | ||
| 393 | 1 | /* |