ARM: OMAP2+: Make ctrl_module_core_44xx.h local

This can be local to mach-omap2. Signed-off-by: Tony Lindgren <tony@atomide.com>

ARM: OMAP2+: Make ctrl_module_core_44xx.h local
This can be local to mach-omap2. Signed-off-by: Tony Lindgren <tony@atomide.com>
Tony Lindgren
1 parent 0a6f98c958
Showing 3 changed files with 393 additions and 393 deletions Side-by-side Diff
arch/arm/mach-omap2/control.h
arch/arm/mach-omap2/ctrl_module_core_44xx.h
arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
@@ -16,7 +16,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
 #define __ARCH_ARM_MACH_OMAP2_CONTROL_H
  
-#include <mach/ctrl_module_core_44xx.h>
+#include "ctrl_module_core_44xx.h"
 #include <mach/ctrl_module_wkup_44xx.h>
 #include <mach/ctrl_module_pad_core_44xx.h>
 #include <mach/ctrl_module_pad_wkup_44xx.h>
+/*
+ * OMAP44xx CTRL_MODULE_CORE registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
+
+
+/* Base address */
+#define OMAP4_CTRL_MODULE_CORE					0x4a002000
+
+/* Registers offset */
+#define OMAP4_CTRL_MODULE_CORE_IP_REVISION			0x0000
+#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO			0x0004
+#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG			0x0010
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0		0x0200
+#define OMAP4_CTRL_MODULE_CORE_ID_CODE				0x0204
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1		0x0208
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2		0x020c
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3		0x0210
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0		0x0214
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1		0x0218
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF		0x021c
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP		0x0228
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP		0x0260
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0		0x0264
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1		0x0268
+#define OMAP4_CTRL_MODULE_CORE_STATUS				0x02c4
+#define OMAP4_CTRL_MODULE_CORE_DEV_CONF				0x0300
+#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR			0x0304
+#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL		0x0314
+#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL		0x0318
+#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL		0x0320
+#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL		0x0324
+#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL	0x0328
+#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR			0x032c
+#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0		0x0330
+#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1		0x0334
+#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL			0x033c
+#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL			0x0340
+#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL			0x0350
+#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL		0x0400
+#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU			0x0408
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0		0x042c
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1		0x0430
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2		0x0434
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3		0x0438
+#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0			0x0440
+#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1			0x0444
+#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2			0x0448
+#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL		0x044c
+#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL		0x0450
+#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL		0x0454
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0		0x0480
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1		0x0484
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2		0x0488
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3		0x048c
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4		0x0490
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5		0x0494
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6		0x0498
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7		0x049c
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8		0x04a0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9		0x04a4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10		0x04a8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11		0x04ac
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12		0x04b0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13		0x04b4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14		0x04b8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15		0x04bc
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16		0x04c0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17		0x04c4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18		0x04c8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19		0x04cc
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20		0x04d0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21		0x04d4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22		0x04d8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23		0x04dc
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24		0x04e0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25		0x04e4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26		0x04e8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27		0x04ec
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28		0x04f0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29		0x04f4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30		0x04f8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31		0x04fc
+
+/* Registers shifts and masks */
+
+/* IP_REVISION */
+#define OMAP4_IP_REV_SCHEME_SHIFT			30
+#define OMAP4_IP_REV_SCHEME_MASK			(0x3 << 30)
+#define OMAP4_IP_REV_FUNC_SHIFT				16
+#define OMAP4_IP_REV_FUNC_MASK				(0xfff << 16)
+#define OMAP4_IP_REV_RTL_SHIFT				11
+#define OMAP4_IP_REV_RTL_MASK				(0x1f << 11)
+#define OMAP4_IP_REV_MAJOR_SHIFT			8
+#define OMAP4_IP_REV_MAJOR_MASK				(0x7 << 8)
+#define OMAP4_IP_REV_CUSTOM_SHIFT			6
+#define OMAP4_IP_REV_CUSTOM_MASK			(0x3 << 6)
+#define OMAP4_IP_REV_MINOR_SHIFT			0
+#define OMAP4_IP_REV_MINOR_MASK				(0x3f << 0)
+
+/* IP_HWINFO */
+#define OMAP4_IP_HWINFO_SHIFT				0
+#define OMAP4_IP_HWINFO_MASK				(0xffffffff << 0)
+
+/* IP_SYSCONFIG */
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT		2
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK		(0x3 << 2)
+
+/* STD_FUSE_DIE_ID_0 */
+#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT			0
+#define OMAP4_STD_FUSE_DIE_ID_0_MASK			(0xffffffff << 0)
+
+/* ID_CODE */
+#define OMAP4_STD_FUSE_IDCODE_SHIFT			0
+#define OMAP4_STD_FUSE_IDCODE_MASK			(0xffffffff << 0)
+
+/* STD_FUSE_DIE_ID_1 */
+#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT			0
+#define OMAP4_STD_FUSE_DIE_ID_1_MASK			(0xffffffff << 0)
+
+/* STD_FUSE_DIE_ID_2 */
+#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT			0
+#define OMAP4_STD_FUSE_DIE_ID_2_MASK			(0xffffffff << 0)
+
+/* STD_FUSE_DIE_ID_3 */
+#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT			0
+#define OMAP4_STD_FUSE_DIE_ID_3_MASK			(0xffffffff << 0)
+
+/* STD_FUSE_PROD_ID_0 */
+#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT			0
+#define OMAP4_STD_FUSE_PROD_ID_0_MASK			(0xffffffff << 0)
+
+/* STD_FUSE_PROD_ID_1 */
+#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT			0
+#define OMAP4_STD_FUSE_PROD_ID_1_MASK			(0xffffffff << 0)
+
+/* STD_FUSE_USB_CONF */
+#define OMAP4_USB_PROD_ID_SHIFT				16
+#define OMAP4_USB_PROD_ID_MASK				(0xffff << 16)
+#define OMAP4_USB_VENDOR_ID_SHIFT			0
+#define OMAP4_USB_VENDOR_ID_MASK			(0xffff << 0)
+
+/* STD_FUSE_OPP_VDD_WKUP */
+#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT		0
+#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK		(0xffffffff << 0)
+
+/* STD_FUSE_OPP_BGAP */
+#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT			0
+#define OMAP4_STD_FUSE_OPP_BGAP_MASK			(0xffffffff << 0)
+
+/* STD_FUSE_OPP_DPLL_0 */
+#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT			0
+#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK			(0xffffffff << 0)
+
+/* STD_FUSE_OPP_DPLL_1 */
+#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT			0
+#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK			(0xffffffff << 0)
+
+/* STATUS */
+#define OMAP4_ATTILA_CONF_SHIFT				11
+#define OMAP4_ATTILA_CONF_MASK				(0x3 << 11)
+#define OMAP4_DEVICE_TYPE_SHIFT				8
+#define OMAP4_DEVICE_TYPE_MASK				(0x7 << 8)
+#define OMAP4_SYS_BOOT_SHIFT				0
+#define OMAP4_SYS_BOOT_MASK				(0xff << 0)
+
+/* DEV_CONF */
+#define OMAP4_DEV_CONF_SHIFT				1
+#define OMAP4_DEV_CONF_MASK				(0x7fffffff << 1)
+#define OMAP4_USBPHY_PD_SHIFT				0
+#define OMAP4_USBPHY_PD_MASK				(1 << 0)
+
+/* LDOVBB_IVA_VOLTAGE_CTRL */
+#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT		26
+#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK		(1 << 26)
+#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT		21
+#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK		(0x1f << 21)
+#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT		16
+#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK		(0x1f << 16)
+#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT		10
+#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK		(1 << 10)
+#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT		5
+#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK		(0x1f << 5)
+#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT		0
+#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK		(0x1f << 0)
+
+/* LDOVBB_MPU_VOLTAGE_CTRL */
+#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT		26
+#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK		(1 << 26)
+#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT		21
+#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK		(0x1f << 21)
+#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT		16
+#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK		(0x1f << 16)
+#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT		10
+#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK		(1 << 10)
+#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT		5
+#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK		(0x1f << 5)
+#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT		0
+#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK		(0x1f << 0)
+
+/* LDOSRAM_IVA_VOLTAGE_CTRL */
+#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT		26
+#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK		(1 << 26)
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT		21
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK		(0x1f << 21)
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT		16
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK		(0x1f << 16)
+#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT		10
+#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK		(1 << 10)
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT		5
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK		(0x1f << 5)
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT		0
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK		(0x1f << 0)
+
+/* LDOSRAM_MPU_VOLTAGE_CTRL */
+#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT		26
+#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK		(1 << 26)
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT		21
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK		(0x1f << 21)
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT		16
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK		(0x1f << 16)
+#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT		10
+#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK		(1 << 10)
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT		5
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK		(0x1f << 5)
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT		0
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK		(0x1f << 0)
+
+/* LDOSRAM_CORE_VOLTAGE_CTRL */
+#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT	26
+#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK		(1 << 26)
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT		21
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK		(0x1f << 21)
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT	16
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK		(0x1f << 16)
+#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT	10
+#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK		(1 << 10)
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT		5
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK		(0x1f << 5)
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT	0
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK		(0x1f << 0)
+
+/* TEMP_SENSOR */
+#define OMAP4_BGAP_TEMPSOFF_SHIFT			12
+#define OMAP4_BGAP_TEMPSOFF_MASK			(1 << 12)
+#define OMAP4_BGAP_TSHUT_SHIFT				11
+#define OMAP4_BGAP_TSHUT_MASK				(1 << 11)
+#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT		10
+#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK		(1 << 10)
+#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT		9
+#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK			(1 << 9)
+#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT		8
+#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK		(1 << 8)
+#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT		0
+#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK		(0xff << 0)
+
+/* DPLL_NWELL_TRIM_0 */
+#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT	29
+#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK		(1 << 29)
+#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT			24
+#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK			(0x1f << 24)
+#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT	23
+#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK		(1 << 23)
+#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT			18
+#define OMAP4_DPLL_PER_NWELL_TRIM_MASK			(0x1f << 18)
+#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT	17
+#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK	(1 << 17)
+#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT		12
+#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK			(0x1f << 12)
+#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT	11
+#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK		(1 << 11)
+#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT			6
+#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK			(0x1f << 6)
+#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT	5
+#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK		(1 << 5)
+#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT			0
+#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK			(0x1f << 0)
+
+/* DPLL_NWELL_TRIM_1 */
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT	29
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK	(1 << 29)
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT		24
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK		(0x1f << 24)
+#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT	23
+#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK		(1 << 23)
+#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT			18
+#define OMAP4_DPLL_USB_NWELL_TRIM_MASK			(0x1f << 18)
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT	17
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK	(1 << 17)
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT		12
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK			(0x1f << 12)
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT	11
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK	(1 << 11)
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT		6
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK			(0x1f << 6)
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT	5
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK	(1 << 5)
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT		0
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK			(0x1f << 0)
+
+/* USBOTGHS_CONTROL */
+#define OMAP4_DISCHRGVBUS_SHIFT				8
+#define OMAP4_DISCHRGVBUS_MASK				(1 << 8)
+#define OMAP4_CHRGVBUS_SHIFT				7
+#define OMAP4_CHRGVBUS_MASK				(1 << 7)
+#define OMAP4_DRVVBUS_SHIFT				6
+#define OMAP4_DRVVBUS_MASK				(1 << 6)
+#define OMAP4_IDPULLUP_SHIFT				5
+#define OMAP4_IDPULLUP_MASK				(1 << 5)
+#define OMAP4_IDDIG_SHIFT				4
+#define OMAP4_IDDIG_MASK				(1 << 4)
+#define OMAP4_SESSEND_SHIFT				3
+#define OMAP4_SESSEND_MASK				(1 << 3)
+#define OMAP4_VBUSVALID_SHIFT				2
+#define OMAP4_VBUSVALID_MASK				(1 << 2)
+#define OMAP4_BVALID_SHIFT				1
+#define OMAP4_BVALID_MASK				(1 << 1)
+#define OMAP4_AVALID_SHIFT				0
+#define OMAP4_AVALID_MASK				(1 << 0)
+
+/* DSS_CONTROL */
+#define OMAP4_DSS_MUX6_SELECT_SHIFT			0
+#define OMAP4_DSS_MUX6_SELECT_MASK			(1 << 0)
+
+/* HWOBS_CONTROL */
+#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT			3
+#define OMAP4_HWOBS_CLKDIV_SEL_MASK			(0x1f << 3)
+#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT			2
+#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK			(1 << 2)
+#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT			1
+#define OMAP4_HWOBS_ALL_ONE_MODE_MASK			(1 << 1)
+#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT			0
+#define OMAP4_HWOBS_MACRO_ENABLE_MASK			(1 << 0)
+
+/* DEBOBS_FINAL_MUX_SEL */
+#define OMAP4_SELECT_SHIFT				0
+#define OMAP4_SELECT_MASK				(0xffffffff << 0)
+
+/* DEBOBS_MMR_MPU */
+#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT		0
+#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK		(0xf << 0)
+
+/* CONF_SDMA_REQ_SEL0 */
+#define OMAP4_MULT_SHIFT				0
+#define OMAP4_MULT_MASK					(0x7f << 0)
+
+/* CONF_CLK_SEL0 */
+#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT			0
+#define OMAP4_MULT_CONF_CLK_SEL0_MASK			(0x7 << 0)
+
+/* CONF_CLK_SEL1 */
+#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT			0
+#define OMAP4_MULT_CONF_CLK_SEL1_MASK			(0x7 << 0)
+
+/* CONF_CLK_SEL2 */
+#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT			0
+#define OMAP4_MULT_CONF_CLK_SEL2_MASK			(0x7 << 0)
+
+/* CONF_DPLL_FREQLOCK_SEL */
+#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT		0
+#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK		(0x7 << 0)
+
+/* CONF_DPLL_TINITZ_SEL */
+#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT		0
+#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK		(0x7 << 0)
+
+/* CONF_DPLL_PHASELOCK_SEL */
+#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT	0
+#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK		(0x7 << 0)
+
+/* CONF_DEBUG_SEL_TST_0 */
+#define OMAP4_MODE_SHIFT				0
+#define OMAP4_MODE_MASK					(0xf << 0)
+
+#endif
-/*
- * OMAP44xx CTRL_MODULE_CORE registers and bitfields
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- *
- * Benoit Cousson (b-cousson@ti.com)
- * Santosh Shilimkar (santosh.shilimkar@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
-#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
-
-
-/* Base address */
-#define OMAP4_CTRL_MODULE_CORE					0x4a002000
-
-/* Registers offset */
-#define OMAP4_CTRL_MODULE_CORE_IP_REVISION			0x0000
-#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO			0x0004
-#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG			0x0010
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0		0x0200
-#define OMAP4_CTRL_MODULE_CORE_ID_CODE				0x0204
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1		0x0208
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2		0x020c
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3		0x0210
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0		0x0214
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1		0x0218
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF		0x021c
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP		0x0228
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP		0x0260
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0		0x0264
-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1		0x0268
-#define OMAP4_CTRL_MODULE_CORE_STATUS				0x02c4
-#define OMAP4_CTRL_MODULE_CORE_DEV_CONF				0x0300
-#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR			0x0304
-#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL		0x0314
-#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL		0x0318
-#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL		0x0320
-#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL		0x0324
-#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL	0x0328
-#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR			0x032c
-#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0		0x0330
-#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1		0x0334
-#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL			0x033c
-#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL			0x0340
-#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL			0x0350
-#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL		0x0400
-#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU			0x0408
-#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0		0x042c
-#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1		0x0430
-#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2		0x0434
-#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3		0x0438
-#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0			0x0440
-#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1			0x0444
-#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2			0x0448
-#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL		0x044c
-#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL		0x0450
-#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL		0x0454
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0		0x0480
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1		0x0484
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2		0x0488
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3		0x048c
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4		0x0490
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5		0x0494
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6		0x0498
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7		0x049c
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8		0x04a0
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9		0x04a4
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10		0x04a8
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11		0x04ac
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12		0x04b0
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13		0x04b4
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14		0x04b8
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15		0x04bc
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16		0x04c0
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17		0x04c4
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18		0x04c8
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19		0x04cc
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20		0x04d0
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21		0x04d4
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22		0x04d8
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23		0x04dc
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24		0x04e0
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25		0x04e4
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26		0x04e8
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27		0x04ec
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28		0x04f0
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29		0x04f4
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30		0x04f8
-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31		0x04fc
-
-/* Registers shifts and masks */
-
-/* IP_REVISION */
-#define OMAP4_IP_REV_SCHEME_SHIFT			30
-#define OMAP4_IP_REV_SCHEME_MASK			(0x3 << 30)
-#define OMAP4_IP_REV_FUNC_SHIFT				16
-#define OMAP4_IP_REV_FUNC_MASK				(0xfff << 16)
-#define OMAP4_IP_REV_RTL_SHIFT				11
-#define OMAP4_IP_REV_RTL_MASK				(0x1f << 11)
-#define OMAP4_IP_REV_MAJOR_SHIFT			8
-#define OMAP4_IP_REV_MAJOR_MASK				(0x7 << 8)
-#define OMAP4_IP_REV_CUSTOM_SHIFT			6
-#define OMAP4_IP_REV_CUSTOM_MASK			(0x3 << 6)
-#define OMAP4_IP_REV_MINOR_SHIFT			0
-#define OMAP4_IP_REV_MINOR_MASK				(0x3f << 0)
-
-/* IP_HWINFO */
-#define OMAP4_IP_HWINFO_SHIFT				0
-#define OMAP4_IP_HWINFO_MASK				(0xffffffff << 0)
-
-/* IP_SYSCONFIG */
-#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT		2
-#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK		(0x3 << 2)
-
-/* STD_FUSE_DIE_ID_0 */
-#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT			0
-#define OMAP4_STD_FUSE_DIE_ID_0_MASK			(0xffffffff << 0)
-
-/* ID_CODE */
-#define OMAP4_STD_FUSE_IDCODE_SHIFT			0
-#define OMAP4_STD_FUSE_IDCODE_MASK			(0xffffffff << 0)
-
-/* STD_FUSE_DIE_ID_1 */
-#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT			0
-#define OMAP4_STD_FUSE_DIE_ID_1_MASK			(0xffffffff << 0)
-
-/* STD_FUSE_DIE_ID_2 */
-#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT			0
-#define OMAP4_STD_FUSE_DIE_ID_2_MASK			(0xffffffff << 0)
-
-/* STD_FUSE_DIE_ID_3 */
-#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT			0
-#define OMAP4_STD_FUSE_DIE_ID_3_MASK			(0xffffffff << 0)
-
-/* STD_FUSE_PROD_ID_0 */
-#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT			0
-#define OMAP4_STD_FUSE_PROD_ID_0_MASK			(0xffffffff << 0)
-
-/* STD_FUSE_PROD_ID_1 */
-#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT			0
-#define OMAP4_STD_FUSE_PROD_ID_1_MASK			(0xffffffff << 0)
-
-/* STD_FUSE_USB_CONF */
-#define OMAP4_USB_PROD_ID_SHIFT				16
-#define OMAP4_USB_PROD_ID_MASK				(0xffff << 16)
-#define OMAP4_USB_VENDOR_ID_SHIFT			0
-#define OMAP4_USB_VENDOR_ID_MASK			(0xffff << 0)
-
-/* STD_FUSE_OPP_VDD_WKUP */
-#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT		0
-#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK		(0xffffffff << 0)
-
-/* STD_FUSE_OPP_BGAP */
-#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT			0
-#define OMAP4_STD_FUSE_OPP_BGAP_MASK			(0xffffffff << 0)
-
-/* STD_FUSE_OPP_DPLL_0 */
-#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT			0
-#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK			(0xffffffff << 0)
-
-/* STD_FUSE_OPP_DPLL_1 */
-#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT			0
-#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK			(0xffffffff << 0)
-
-/* STATUS */
-#define OMAP4_ATTILA_CONF_SHIFT				11
-#define OMAP4_ATTILA_CONF_MASK				(0x3 << 11)
-#define OMAP4_DEVICE_TYPE_SHIFT				8
-#define OMAP4_DEVICE_TYPE_MASK				(0x7 << 8)
-#define OMAP4_SYS_BOOT_SHIFT				0
-#define OMAP4_SYS_BOOT_MASK				(0xff << 0)
-
-/* DEV_CONF */
-#define OMAP4_DEV_CONF_SHIFT				1
-#define OMAP4_DEV_CONF_MASK				(0x7fffffff << 1)
-#define OMAP4_USBPHY_PD_SHIFT				0
-#define OMAP4_USBPHY_PD_MASK				(1 << 0)
-
-/* LDOVBB_IVA_VOLTAGE_CTRL */
-#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT		26
-#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK		(1 << 26)
-#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT		21
-#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK		(0x1f << 21)
-#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT		16
-#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK		(0x1f << 16)
-#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT		10
-#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK		(1 << 10)
-#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT		5
-#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK		(0x1f << 5)
-#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT		0
-#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK		(0x1f << 0)
-
-/* LDOVBB_MPU_VOLTAGE_CTRL */
-#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT		26
-#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK		(1 << 26)
-#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT		21
-#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK		(0x1f << 21)
-#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT		16
-#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK		(0x1f << 16)
-#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT		10
-#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK		(1 << 10)
-#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT		5
-#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK		(0x1f << 5)
-#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT		0
-#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK		(0x1f << 0)
-
-/* LDOSRAM_IVA_VOLTAGE_CTRL */
-#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT		26
-#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK		(1 << 26)
-#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT		21
-#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK		(0x1f << 21)
-#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT		16
-#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK		(0x1f << 16)
-#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT		10
-#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK		(1 << 10)
-#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT		5
-#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK		(0x1f << 5)
-#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT		0
-#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK		(0x1f << 0)
-
-/* LDOSRAM_MPU_VOLTAGE_CTRL */
-#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT		26
-#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK		(1 << 26)
-#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT		21
-#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK		(0x1f << 21)
-#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT		16
-#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK		(0x1f << 16)
-#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT		10
-#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK		(1 << 10)
-#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT		5
-#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK		(0x1f << 5)
-#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT		0
-#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK		(0x1f << 0)
-
-/* LDOSRAM_CORE_VOLTAGE_CTRL */
-#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT	26
-#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK		(1 << 26)
-#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT		21
-#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK		(0x1f << 21)
-#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT	16
-#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK		(0x1f << 16)
-#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT	10
-#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK		(1 << 10)
-#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT		5
-#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK		(0x1f << 5)
-#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT	0
-#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK		(0x1f << 0)
-
-/* TEMP_SENSOR */
-#define OMAP4_BGAP_TEMPSOFF_SHIFT			12
-#define OMAP4_BGAP_TEMPSOFF_MASK			(1 << 12)
-#define OMAP4_BGAP_TSHUT_SHIFT				11
-#define OMAP4_BGAP_TSHUT_MASK				(1 << 11)
-#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT		10
-#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK		(1 << 10)
-#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT		9
-#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK			(1 << 9)
-#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT		8
-#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK		(1 << 8)
-#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT		0
-#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK		(0xff << 0)
-
-/* DPLL_NWELL_TRIM_0 */
-#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT	29
-#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK		(1 << 29)
-#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT			24
-#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK			(0x1f << 24)
-#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT	23
-#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK		(1 << 23)
-#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT			18
-#define OMAP4_DPLL_PER_NWELL_TRIM_MASK			(0x1f << 18)
-#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT	17
-#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK	(1 << 17)
-#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT		12
-#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK			(0x1f << 12)
-#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT	11
-#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK		(1 << 11)
-#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT			6
-#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK			(0x1f << 6)
-#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT	5
-#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK		(1 << 5)
-#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT			0
-#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK			(0x1f << 0)
-
-/* DPLL_NWELL_TRIM_1 */
-#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT	29
-#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK	(1 << 29)
-#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT		24
-#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK		(0x1f << 24)
-#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT	23
-#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK		(1 << 23)
-#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT			18
-#define OMAP4_DPLL_USB_NWELL_TRIM_MASK			(0x1f << 18)
-#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT	17
-#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK	(1 << 17)
-#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT		12
-#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK			(0x1f << 12)
-#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT	11
-#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK	(1 << 11)
-#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT		6
-#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK			(0x1f << 6)
-#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT	5
-#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK	(1 << 5)
-#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT		0
-#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK			(0x1f << 0)
-
-/* USBOTGHS_CONTROL */
-#define OMAP4_DISCHRGVBUS_SHIFT				8
-#define OMAP4_DISCHRGVBUS_MASK				(1 << 8)
-#define OMAP4_CHRGVBUS_SHIFT				7
-#define OMAP4_CHRGVBUS_MASK				(1 << 7)
-#define OMAP4_DRVVBUS_SHIFT				6
-#define OMAP4_DRVVBUS_MASK				(1 << 6)
-#define OMAP4_IDPULLUP_SHIFT				5
-#define OMAP4_IDPULLUP_MASK				(1 << 5)
-#define OMAP4_IDDIG_SHIFT				4
-#define OMAP4_IDDIG_MASK				(1 << 4)
-#define OMAP4_SESSEND_SHIFT				3
-#define OMAP4_SESSEND_MASK				(1 << 3)
-#define OMAP4_VBUSVALID_SHIFT				2
-#define OMAP4_VBUSVALID_MASK				(1 << 2)
-#define OMAP4_BVALID_SHIFT				1
-#define OMAP4_BVALID_MASK				(1 << 1)
-#define OMAP4_AVALID_SHIFT				0
-#define OMAP4_AVALID_MASK				(1 << 0)
-
-/* DSS_CONTROL */
-#define OMAP4_DSS_MUX6_SELECT_SHIFT			0
-#define OMAP4_DSS_MUX6_SELECT_MASK			(1 << 0)
-
-/* HWOBS_CONTROL */
-#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT			3
-#define OMAP4_HWOBS_CLKDIV_SEL_MASK			(0x1f << 3)
-#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT			2
-#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK			(1 << 2)
-#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT			1
-#define OMAP4_HWOBS_ALL_ONE_MODE_MASK			(1 << 1)
-#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT			0
-#define OMAP4_HWOBS_MACRO_ENABLE_MASK			(1 << 0)
-
-/* DEBOBS_FINAL_MUX_SEL */
-#define OMAP4_SELECT_SHIFT				0
-#define OMAP4_SELECT_MASK				(0xffffffff << 0)
-
-/* DEBOBS_MMR_MPU */
-#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT		0
-#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK		(0xf << 0)
-
-/* CONF_SDMA_REQ_SEL0 */
-#define OMAP4_MULT_SHIFT				0
-#define OMAP4_MULT_MASK					(0x7f << 0)
-
-/* CONF_CLK_SEL0 */
-#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT			0
-#define OMAP4_MULT_CONF_CLK_SEL0_MASK			(0x7 << 0)
-
-/* CONF_CLK_SEL1 */
-#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT			0
-#define OMAP4_MULT_CONF_CLK_SEL1_MASK			(0x7 << 0)
-
-/* CONF_CLK_SEL2 */
-#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT			0
-#define OMAP4_MULT_CONF_CLK_SEL2_MASK			(0x7 << 0)
-
-/* CONF_DPLL_FREQLOCK_SEL */
-#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT		0
-#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK		(0x7 << 0)
-
-/* CONF_DPLL_TINITZ_SEL */
-#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT		0
-#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK		(0x7 << 0)
-
-/* CONF_DPLL_PHASELOCK_SEL */
-#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT	0
-#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK		(0x7 << 0)
-
-/* CONF_DEBUG_SEL_TST_0 */
-#define OMAP4_MODE_SHIFT				0
-#define OMAP4_MODE_MASK					(0xf << 0)
-
-#endif
...	...	@@ -16,7 +16,7 @@
16	16	#ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
17	17	#define __ARCH_ARM_MACH_OMAP2_CONTROL_H
18	18
19		-#include <mach/ctrl_module_core_44xx.h>
	19	+#include "ctrl_module_core_44xx.h"
20	20	#include <mach/ctrl_module_wkup_44xx.h>
21	21	#include <mach/ctrl_module_pad_core_44xx.h>
22	22	#include <mach/ctrl_module_pad_wkup_44xx.h>
	1	+/*
	2	+ * OMAP44xx CTRL_MODULE_CORE registers and bitfields
	3	+ *
	4	+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
	5	+ *
	6	+ * Benoit Cousson (b-cousson@ti.com)
	7	+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
	8	+ *
	9	+ * This file is automatically generated from the OMAP hardware databases.
	10	+ * We respectfully ask that any modifications to this file be coordinated
	11	+ * with the public linux-omap@vger.kernel.org mailing list and the
	12	+ * authors above to ensure that the autogeneration scripts are kept
	13	+ * up-to-date with the file contents.
	14	+ *
	15	+ * This program is free software; you can redistribute it and/or modify
	16	+ * it under the terms of the GNU General Public License version 2 as
	17	+ * published by the Free Software Foundation.
	18	+ */
	19	+
	20	+#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
	21	+#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
	22	+
	23	+
	24	+/* Base address */
	25	+#define OMAP4_CTRL_MODULE_CORE 0x4a002000
	26	+
	27	+/* Registers offset */
	28	+#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000
	29	+#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004
	30	+#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010
	31	+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200
	32	+#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204
	33	+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208
	34	+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c
	35	+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210
	36	+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214
	37	+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
	38	+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c
	39	+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228
	40	+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260
	41	+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264
	42	+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268
	43	+#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
	44	+#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300
	45	+#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304
	46	+#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314
	47	+#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318
	48	+#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320
	49	+#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324
	50	+#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328
	51	+#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c
	52	+#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330
	53	+#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334
	54	+#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c
	55	+#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340
	56	+#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350
	57	+#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400
	58	+#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408
	59	+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c
	60	+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430
	61	+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434
	62	+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438
	63	+#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440
	64	+#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444
	65	+#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448
	66	+#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c
	67	+#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450
	68	+#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454
	69	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480
	70	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484
	71	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488
	72	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c
	73	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490
	74	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494
	75	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498
	76	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c
	77	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0
	78	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4
	79	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8
	80	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac
	81	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0
	82	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4
	83	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8
	84	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc
	85	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0
	86	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4
	87	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8
	88	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc
	89	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0
	90	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4
	91	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8
	92	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc
	93	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0
	94	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4
	95	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8
	96	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec
	97	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0
	98	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4
	99	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8
	100	+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc
	101	+
	102	+/* Registers shifts and masks */
	103	+
	104	+/* IP_REVISION */
	105	+#define OMAP4_IP_REV_SCHEME_SHIFT 30
	106	+#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
	107	+#define OMAP4_IP_REV_FUNC_SHIFT 16
	108	+#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
	109	+#define OMAP4_IP_REV_RTL_SHIFT 11
	110	+#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
	111	+#define OMAP4_IP_REV_MAJOR_SHIFT 8
	112	+#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
	113	+#define OMAP4_IP_REV_CUSTOM_SHIFT 6
	114	+#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
	115	+#define OMAP4_IP_REV_MINOR_SHIFT 0
	116	+#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
	117	+
	118	+/* IP_HWINFO */
	119	+#define OMAP4_IP_HWINFO_SHIFT 0
	120	+#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
	121	+
	122	+/* IP_SYSCONFIG */
	123	+#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
	124	+#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
	125	+
	126	+/* STD_FUSE_DIE_ID_0 */
	127	+#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0
	128	+#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0)
	129	+
	130	+/* ID_CODE */
	131	+#define OMAP4_STD_FUSE_IDCODE_SHIFT 0
	132	+#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0)
	133	+
	134	+/* STD_FUSE_DIE_ID_1 */
	135	+#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0
	136	+#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0)
	137	+
	138	+/* STD_FUSE_DIE_ID_2 */
	139	+#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0
	140	+#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0)
	141	+
	142	+/* STD_FUSE_DIE_ID_3 */
	143	+#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0
	144	+#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0)
	145	+
	146	+/* STD_FUSE_PROD_ID_0 */
	147	+#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0
	148	+#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0)
	149	+
	150	+/* STD_FUSE_PROD_ID_1 */
	151	+#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0
	152	+#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0)
	153	+
	154	+/* STD_FUSE_USB_CONF */
	155	+#define OMAP4_USB_PROD_ID_SHIFT 16
	156	+#define OMAP4_USB_PROD_ID_MASK (0xffff << 16)
	157	+#define OMAP4_USB_VENDOR_ID_SHIFT 0
	158	+#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0)
	159	+
	160	+/* STD_FUSE_OPP_VDD_WKUP */
	161	+#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0
	162	+#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0)
	163	+
	164	+/* STD_FUSE_OPP_BGAP */
	165	+#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0
	166	+#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0)
	167	+
	168	+/* STD_FUSE_OPP_DPLL_0 */
	169	+#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0
	170	+#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0)
	171	+
	172	+/* STD_FUSE_OPP_DPLL_1 */
	173	+#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0
	174	+#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0)
	175	+
	176	+/* STATUS */
	177	+#define OMAP4_ATTILA_CONF_SHIFT 11
	178	+#define OMAP4_ATTILA_CONF_MASK (0x3 << 11)
	179	+#define OMAP4_DEVICE_TYPE_SHIFT 8
	180	+#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8)
	181	+#define OMAP4_SYS_BOOT_SHIFT 0
	182	+#define OMAP4_SYS_BOOT_MASK (0xff << 0)
	183	+
	184	+/* DEV_CONF */
	185	+#define OMAP4_DEV_CONF_SHIFT 1
	186	+#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1)
	187	+#define OMAP4_USBPHY_PD_SHIFT 0
	188	+#define OMAP4_USBPHY_PD_MASK (1 << 0)
	189	+
	190	+/* LDOVBB_IVA_VOLTAGE_CTRL */
	191	+#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26
	192	+#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26)
	193	+#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21
	194	+#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21)
	195	+#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16
	196	+#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16)
	197	+#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10
	198	+#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10)
	199	+#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5
	200	+#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5)
	201	+#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0
	202	+#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0)
	203	+
	204	+/* LDOVBB_MPU_VOLTAGE_CTRL */
	205	+#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26
	206	+#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26)
	207	+#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21
	208	+#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21)
	209	+#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16
	210	+#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16)
	211	+#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10
	212	+#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10)
	213	+#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5
	214	+#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5)
	215	+#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0
	216	+#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0)
	217	+
	218	+/* LDOSRAM_IVA_VOLTAGE_CTRL */
	219	+#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26
	220	+#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26)
	221	+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21
	222	+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21)
	223	+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16
	224	+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16)
	225	+#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10
	226	+#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10)
	227	+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5
	228	+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5)
	229	+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0
	230	+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0)
	231	+
	232	+/* LDOSRAM_MPU_VOLTAGE_CTRL */
	233	+#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26
	234	+#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26)
	235	+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21
	236	+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21)
	237	+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16
	238	+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16)
	239	+#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10
	240	+#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10)
	241	+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5
	242	+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5)
	243	+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0
	244	+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0)
	245	+
	246	+/* LDOSRAM_CORE_VOLTAGE_CTRL */
	247	+#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26
	248	+#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26)
	249	+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21
	250	+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21)
	251	+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16
	252	+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16)
	253	+#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10
	254	+#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10)
	255	+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5
	256	+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5)
	257	+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0
	258	+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0)
	259	+
	260	+/* TEMP_SENSOR */
	261	+#define OMAP4_BGAP_TEMPSOFF_SHIFT 12
	262	+#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12)
	263	+#define OMAP4_BGAP_TSHUT_SHIFT 11
	264	+#define OMAP4_BGAP_TSHUT_MASK (1 << 11)
	265	+#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10
	266	+#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10)
	267	+#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9
	268	+#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9)
	269	+#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8
	270	+#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8)
	271	+#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
	272	+#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
	273	+
	274	+/* DPLL_NWELL_TRIM_0 */
	275	+#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29
	276	+#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
	277	+#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24
	278	+#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24)
	279	+#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23
	280	+#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
	281	+#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18
	282	+#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18)
	283	+#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17
	284	+#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
	285	+#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12
	286	+#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12)
	287	+#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11
	288	+#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
	289	+#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6
	290	+#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6)
	291	+#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5
	292	+#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
	293	+#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0
	294	+#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0)
	295	+
	296	+/* DPLL_NWELL_TRIM_1 */
	297	+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29
	298	+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
	299	+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24
	300	+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24)
	301	+#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23
	302	+#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
	303	+#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18
	304	+#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18)
	305	+#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17
	306	+#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
	307	+#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12
	308	+#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12)
	309	+#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11
	310	+#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
	311	+#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6
	312	+#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6)
	313	+#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5
	314	+#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
	315	+#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0
	316	+#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0)
	317	+
	318	+/* USBOTGHS_CONTROL */
	319	+#define OMAP4_DISCHRGVBUS_SHIFT 8
	320	+#define OMAP4_DISCHRGVBUS_MASK (1 << 8)
	321	+#define OMAP4_CHRGVBUS_SHIFT 7
	322	+#define OMAP4_CHRGVBUS_MASK (1 << 7)
	323	+#define OMAP4_DRVVBUS_SHIFT 6
	324	+#define OMAP4_DRVVBUS_MASK (1 << 6)
	325	+#define OMAP4_IDPULLUP_SHIFT 5
	326	+#define OMAP4_IDPULLUP_MASK (1 << 5)
	327	+#define OMAP4_IDDIG_SHIFT 4
	328	+#define OMAP4_IDDIG_MASK (1 << 4)
	329	+#define OMAP4_SESSEND_SHIFT 3
	330	+#define OMAP4_SESSEND_MASK (1 << 3)
	331	+#define OMAP4_VBUSVALID_SHIFT 2
	332	+#define OMAP4_VBUSVALID_MASK (1 << 2)
	333	+#define OMAP4_BVALID_SHIFT 1
	334	+#define OMAP4_BVALID_MASK (1 << 1)
	335	+#define OMAP4_AVALID_SHIFT 0
	336	+#define OMAP4_AVALID_MASK (1 << 0)
	337	+
	338	+/* DSS_CONTROL */
	339	+#define OMAP4_DSS_MUX6_SELECT_SHIFT 0
	340	+#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0)
	341	+
	342	+/* HWOBS_CONTROL */
	343	+#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3
	344	+#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3)
	345	+#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2
	346	+#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2)
	347	+#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1
	348	+#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1)
	349	+#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0
	350	+#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0)
	351	+
	352	+/* DEBOBS_FINAL_MUX_SEL */
	353	+#define OMAP4_SELECT_SHIFT 0
	354	+#define OMAP4_SELECT_MASK (0xffffffff << 0)
	355	+
	356	+/* DEBOBS_MMR_MPU */
	357	+#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0
	358	+#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0)
	359	+
	360	+/* CONF_SDMA_REQ_SEL0 */
	361	+#define OMAP4_MULT_SHIFT 0
	362	+#define OMAP4_MULT_MASK (0x7f << 0)
	363	+
	364	+/* CONF_CLK_SEL0 */
	365	+#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0
	366	+#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0)
	367	+
	368	+/* CONF_CLK_SEL1 */
	369	+#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0
	370	+#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0)
	371	+
	372	+/* CONF_CLK_SEL2 */
	373	+#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0
	374	+#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0)
	375	+
	376	+/* CONF_DPLL_FREQLOCK_SEL */
	377	+#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0
	378	+#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0)
	379	+
	380	+/* CONF_DPLL_TINITZ_SEL */
	381	+#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0
	382	+#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0)
	383	+
	384	+/* CONF_DPLL_PHASELOCK_SEL */
	385	+#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0
	386	+#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0)
	387	+
	388	+/* CONF_DEBUG_SEL_TST_0 */
	389	+#define OMAP4_MODE_SHIFT 0
	390	+#define OMAP4_MODE_MASK (0xf << 0)
	391	+
	392	+#endif
1		-/*
2		- * OMAP44xx CTRL_MODULE_CORE registers and bitfields
3		- *
4		- * Copyright (C) 2009-2010 Texas Instruments, Inc.
5		- *
6		- * Benoit Cousson (b-cousson@ti.com)
7		- * Santosh Shilimkar (santosh.shilimkar@ti.com)
8		- *
9		- * This file is automatically generated from the OMAP hardware databases.
10		- * We respectfully ask that any modifications to this file be coordinated
11		- * with the public linux-omap@vger.kernel.org mailing list and the
12		- * authors above to ensure that the autogeneration scripts are kept
13		- * up-to-date with the file contents.
14		- *
15		- * This program is free software; you can redistribute it and/or modify
16		- * it under the terms of the GNU General Public License version 2 as
17		- * published by the Free Software Foundation.
18		- */
19		-
20		-#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
21		-#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
22		-
23		-
24		-/* Base address */
25		-#define OMAP4_CTRL_MODULE_CORE 0x4a002000
26		-
27		-/* Registers offset */
28		-#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000
29		-#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004
30		-#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010
31		-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200
32		-#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204
33		-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208
34		-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c
35		-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210
36		-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214
37		-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
38		-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c
39		-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228
40		-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260
41		-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264
42		-#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268
43		-#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
44		-#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300
45		-#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304
46		-#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314
47		-#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318
48		-#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320
49		-#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324
50		-#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328
51		-#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c
52		-#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330
53		-#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334
54		-#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c
55		-#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340
56		-#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350
57		-#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400
58		-#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408
59		-#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c
60		-#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430
61		-#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434
62		-#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438
63		-#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440
64		-#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444
65		-#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448
66		-#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c
67		-#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450
68		-#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454
69		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480
70		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484
71		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488
72		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c
73		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490
74		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494
75		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498
76		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c
77		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0
78		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4
79		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8
80		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac
81		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0
82		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4
83		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8
84		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc
85		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0
86		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4
87		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8
88		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc
89		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0
90		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4
91		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8
92		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc
93		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0
94		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4
95		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8
96		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec
97		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0
98		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4
99		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8
100		-#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc
101		-
102		-/* Registers shifts and masks */
103		-
104		-/* IP_REVISION */
105		-#define OMAP4_IP_REV_SCHEME_SHIFT 30
106		-#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
107		-#define OMAP4_IP_REV_FUNC_SHIFT 16
108		-#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
109		-#define OMAP4_IP_REV_RTL_SHIFT 11
110		-#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
111		-#define OMAP4_IP_REV_MAJOR_SHIFT 8
112		-#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
113		-#define OMAP4_IP_REV_CUSTOM_SHIFT 6
114		-#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
115		-#define OMAP4_IP_REV_MINOR_SHIFT 0
116		-#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
117		-
118		-/* IP_HWINFO */
119		-#define OMAP4_IP_HWINFO_SHIFT 0
120		-#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
121		-
122		-/* IP_SYSCONFIG */
123		-#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
124		-#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
125		-
126		-/* STD_FUSE_DIE_ID_0 */
127		-#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0
128		-#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0)
129		-
130		-/* ID_CODE */
131		-#define OMAP4_STD_FUSE_IDCODE_SHIFT 0
132		-#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0)
133		-
134		-/* STD_FUSE_DIE_ID_1 */
135		-#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0
136		-#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0)
137		-
138		-/* STD_FUSE_DIE_ID_2 */
139		-#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0
140		-#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0)
141		-
142		-/* STD_FUSE_DIE_ID_3 */
143		-#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0
144		-#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0)
145		-
146		-/* STD_FUSE_PROD_ID_0 */
147		-#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0
148		-#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0)
149		-
150		-/* STD_FUSE_PROD_ID_1 */
151		-#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0
152		-#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0)
153		-
154		-/* STD_FUSE_USB_CONF */
155		-#define OMAP4_USB_PROD_ID_SHIFT 16
156		-#define OMAP4_USB_PROD_ID_MASK (0xffff << 16)
157		-#define OMAP4_USB_VENDOR_ID_SHIFT 0
158		-#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0)
159		-
160		-/* STD_FUSE_OPP_VDD_WKUP */
161		-#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0
162		-#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0)
163		-
164		-/* STD_FUSE_OPP_BGAP */
165		-#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0
166		-#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0)
167		-
168		-/* STD_FUSE_OPP_DPLL_0 */
169		-#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0
170		-#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0)
171		-
172		-/* STD_FUSE_OPP_DPLL_1 */
173		-#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0
174		-#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0)
175		-
176		-/* STATUS */
177		-#define OMAP4_ATTILA_CONF_SHIFT 11
178		-#define OMAP4_ATTILA_CONF_MASK (0x3 << 11)
179		-#define OMAP4_DEVICE_TYPE_SHIFT 8
180		-#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8)
181		-#define OMAP4_SYS_BOOT_SHIFT 0
182		-#define OMAP4_SYS_BOOT_MASK (0xff << 0)
183		-
184		-/* DEV_CONF */
185		-#define OMAP4_DEV_CONF_SHIFT 1
186		-#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1)
187		-#define OMAP4_USBPHY_PD_SHIFT 0
188		-#define OMAP4_USBPHY_PD_MASK (1 << 0)
189		-
190		-/* LDOVBB_IVA_VOLTAGE_CTRL */
191		-#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26
192		-#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26)
193		-#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21
194		-#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21)
195		-#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16
196		-#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16)
197		-#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10
198		-#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10)
199		-#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5
200		-#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5)
201		-#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0
202		-#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0)
203		-
204		-/* LDOVBB_MPU_VOLTAGE_CTRL */
205		-#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26
206		-#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26)
207		-#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21
208		-#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21)
209		-#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16
210		-#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16)
211		-#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10
212		-#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10)
213		-#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5
214		-#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5)
215		-#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0
216		-#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0)
217		-
218		-/* LDOSRAM_IVA_VOLTAGE_CTRL */
219		-#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26
220		-#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26)
221		-#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21
222		-#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21)
223		-#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16
224		-#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16)
225		-#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10
226		-#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10)
227		-#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5
228		-#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5)
229		-#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0
230		-#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0)
231		-
232		-/* LDOSRAM_MPU_VOLTAGE_CTRL */
233		-#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26
234		-#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26)
235		-#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21
236		-#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21)
237		-#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16
238		-#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16)
239		-#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10
240		-#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10)
241		-#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5
242		-#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5)
243		-#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0
244		-#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0)
245		-
246		-/* LDOSRAM_CORE_VOLTAGE_CTRL */
247		-#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26
248		-#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26)
249		-#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21
250		-#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21)
251		-#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16
252		-#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16)
253		-#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10
254		-#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10)
255		-#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5
256		-#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5)
257		-#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0
258		-#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0)
259		-
260		-/* TEMP_SENSOR */
261		-#define OMAP4_BGAP_TEMPSOFF_SHIFT 12
262		-#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12)
263		-#define OMAP4_BGAP_TSHUT_SHIFT 11
264		-#define OMAP4_BGAP_TSHUT_MASK (1 << 11)
265		-#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10
266		-#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10)
267		-#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9
268		-#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9)
269		-#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8
270		-#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8)
271		-#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
272		-#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
273		-
274		-/* DPLL_NWELL_TRIM_0 */
275		-#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29
276		-#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
277		-#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24
278		-#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24)
279		-#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23
280		-#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
281		-#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18
282		-#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18)
283		-#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17
284		-#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
285		-#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12
286		-#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12)
287		-#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11
288		-#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
289		-#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6
290		-#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6)
291		-#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5
292		-#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
293		-#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0
294		-#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0)
295		-
296		-/* DPLL_NWELL_TRIM_1 */
297		-#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29
298		-#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
299		-#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24
300		-#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24)
301		-#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23
302		-#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
303		-#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18
304		-#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18)
305		-#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17
306		-#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
307		-#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12
308		-#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12)
309		-#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11
310		-#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
311		-#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6
312		-#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6)
313		-#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5
314		-#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
315		-#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0
316		-#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0)
317		-
318		-/* USBOTGHS_CONTROL */
319		-#define OMAP4_DISCHRGVBUS_SHIFT 8
320		-#define OMAP4_DISCHRGVBUS_MASK (1 << 8)
321		-#define OMAP4_CHRGVBUS_SHIFT 7
322		-#define OMAP4_CHRGVBUS_MASK (1 << 7)
323		-#define OMAP4_DRVVBUS_SHIFT 6
324		-#define OMAP4_DRVVBUS_MASK (1 << 6)
325		-#define OMAP4_IDPULLUP_SHIFT 5
326		-#define OMAP4_IDPULLUP_MASK (1 << 5)
327		-#define OMAP4_IDDIG_SHIFT 4
328		-#define OMAP4_IDDIG_MASK (1 << 4)
329		-#define OMAP4_SESSEND_SHIFT 3
330		-#define OMAP4_SESSEND_MASK (1 << 3)
331		-#define OMAP4_VBUSVALID_SHIFT 2
332		-#define OMAP4_VBUSVALID_MASK (1 << 2)
333		-#define OMAP4_BVALID_SHIFT 1
334		-#define OMAP4_BVALID_MASK (1 << 1)
335		-#define OMAP4_AVALID_SHIFT 0
336		-#define OMAP4_AVALID_MASK (1 << 0)
337		-
338		-/* DSS_CONTROL */
339		-#define OMAP4_DSS_MUX6_SELECT_SHIFT 0
340		-#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0)
341		-
342		-/* HWOBS_CONTROL */
343		-#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3
344		-#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3)
345		-#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2
346		-#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2)
347		-#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1
348		-#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1)
349		-#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0
350		-#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0)
351		-
352		-/* DEBOBS_FINAL_MUX_SEL */
353		-#define OMAP4_SELECT_SHIFT 0
354		-#define OMAP4_SELECT_MASK (0xffffffff << 0)
355		-
356		-/* DEBOBS_MMR_MPU */
357		-#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0
358		-#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0)
359		-
360		-/* CONF_SDMA_REQ_SEL0 */
361		-#define OMAP4_MULT_SHIFT 0
362		-#define OMAP4_MULT_MASK (0x7f << 0)
363		-
364		-/* CONF_CLK_SEL0 */
365		-#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0
366		-#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0)
367		-
368		-/* CONF_CLK_SEL1 */
369		-#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0
370		-#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0)
371		-
372		-/* CONF_CLK_SEL2 */
373		-#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0
374		-#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0)
375		-
376		-/* CONF_DPLL_FREQLOCK_SEL */
377		-#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0
378		-#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0)
379		-
380		-/* CONF_DPLL_TINITZ_SEL */
381		-#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0
382		-#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0)
383		-
384		-/* CONF_DPLL_PHASELOCK_SEL */
385		-#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0
386		-#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0)
387		-
388		-/* CONF_DEBUG_SEL_TST_0 */
389		-#define OMAP4_MODE_SHIFT 0
390		-#define OMAP4_MODE_MASK (0xf << 0)
391		-
392		-#endif