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Commit 934b7024f0ed29003c95cef447d92737ab86dc4f

Authored by Linus Torvalds
1 parent 29591b92e1
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

Fix cardbus resource allocation 

Commit 884525655d07fdee9245716b998ecdc45cdd8007 ("PCI: clean up resource
alignment management") didn't set the alignment information for the
cardbus window resources, causing their subsequent allocations to fail
miserably with a message like

  yenta_cardbus 0000:15:00.0: device not available because of BAR 7 [100:1ff] collisions
  yenta_cardbus: probe of 0000:15:00.0 failed with error -16

or similar.

This fixes it and clarifies the code a bit too (we used to have to use
the insane PCI bridge alignment logic that put the alignment in the
"start" field, this makes it use the slightly easier-to-understand
size-based alignment, and allows us to set the resource start to zero
until it gets allocated).

Reported-and-tested-by: Jeff Chua <jeff.chua.linux@gmail.com>
Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Showing 1 changed file with 15 additions and 15 deletions Side-by-side Diff

drivers/pci/setup-bus.c
Diff comments   View file @ 934b702
... ... @@ -416,13 +416,13 @@
416 416 * Reserve some resources for CardBus. We reserve
417 417 * a fixed amount of bus space for CardBus bridges.
418 418 */
419   - b_res[0].start = pci_cardbus_io_size;
420   - b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
421   - b_res[0].flags |= IORESOURCE_IO;
  419 + b_res[0].start = 0;
  420 + b_res[0].end = pci_cardbus_io_size - 1;
  421 + b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
422 422  
423   - b_res[1].start = pci_cardbus_io_size;
424   - b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
425   - b_res[1].flags |= IORESOURCE_IO;
  423 + b_res[1].start = 0;
  424 + b_res[1].end = pci_cardbus_io_size - 1;
  425 + b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
426 426  
427 427 /*
428 428 * Check whether prefetchable memory is supported
429 429  
430 430  
... ... @@ -441,17 +441,17 @@
441 441 * twice the size.
442 442 */
443 443 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
444   - b_res[2].start = pci_cardbus_mem_size;
445   - b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
446   - b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
  444 + b_res[2].start = 0;
  445 + b_res[2].end = pci_cardbus_mem_size - 1;
  446 + b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
447 447  
448   - b_res[3].start = pci_cardbus_mem_size;
449   - b_res[3].end = b_res[3].start + pci_cardbus_mem_size - 1;
450   - b_res[3].flags |= IORESOURCE_MEM;
  448 + b_res[3].start = 0;
  449 + b_res[3].end = pci_cardbus_mem_size - 1;
  450 + b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
451 451 } else {
452   - b_res[3].start = pci_cardbus_mem_size * 2;
453   - b_res[3].end = b_res[3].start + pci_cardbus_mem_size * 2 - 1;
454   - b_res[3].flags |= IORESOURCE_MEM;
  452 + b_res[3].start = 0;
  453 + b_res[3].end = pci_cardbus_mem_size * 2 - 1;
  454 + b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
455 455 }
456 456 }
457 457