amd64_edac: Add Family 16h support

Add code to handle DRAM ECC errors decoding for Fam16h. Tested on Fam16h with ECC turned on using the mce_amd_inj facility and works fine. Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> [ Boris: cleanups and clarifications ] Signed-off-by: Borislav Petkov <bp@suse.de>

amd64_edac: Add Family 16h support
Add code to handle DRAM ECC errors decoding for Fam16h. Tested on Fam16h with ECC turned on using the mce_amd_inj facility and works fine. Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> [ Boris: cleanups and clarifications ] Signed-off-by: Borislav Petkov <bp@suse.de>
Aravind Gopalakrishnan · Borislav Petkov
1 parent 41ef2d5678
Showing 4 changed files with 71 additions and 3 deletions Side-by-side Diff
arch/x86/kernel/amd_nb.c
drivers/edac/amd64_edac.c
drivers/edac/amd64_edac.h
include/linux/pci_ids.h
@@ -20,12 +20,14 @@
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
 	{}
 };
 EXPORT_SYMBOL(amd_nb_misc_ids);
  
 static struct pci_device_id amd_nb_link_ids[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
 	{}
 };
  
@@ -81,7 +83,6 @@
 			next_northbridge(link, amd_nb_link_ids);
         }
  
-	/* some CPU families (e.g. family 0x11) do not support GART */
 	if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||
 	    boot_cpu_data.x86 == 0x15)
 		amd_northbridges.flags |= AMD_NB_GART;
@@ -98,6 +98,7 @@
  *
  * F15h: we select which DCT we access using F1x10C[DctCfgSel]
  *
+ * F16h: has only 1 DCT
  */
 static int k8_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
 			       const char *func)
@@ -340,6 +341,27 @@
 		base_bits	= GENMASK(21, 31) | GENMASK(9, 15);
 		mask_bits	= GENMASK(21, 29) | GENMASK(9, 15);
 		addr_shift	= 4;
+
+	/*
+	* F16h needs two addr_shift values: 8 for high and 6 for low
+	* (cf. F16h BKDG).
+	*/
+	} else if (boot_cpu_data.x86 == 0x16) {
+		csbase          = pvt->csels[dct].csbases[csrow];
+		csmask          = pvt->csels[dct].csmasks[csrow >> 1];
+
+		*base  = (csbase & GENMASK(5,  15)) << 6;
+		*base |= (csbase & GENMASK(19, 30)) << 8;
+
+		*mask = ~0ULL;
+		/* poke holes for the csmask */
+		*mask &= ~((GENMASK(5, 15)  << 6) |
+			   (GENMASK(19, 30) << 8));
+
+		*mask |= (csmask & GENMASK(5, 15))  << 6;
+		*mask |= (csmask & GENMASK(19, 30)) << 8;
+
+		return;
 	} else {
 		csbase		= pvt->csels[dct].csbases[csrow];
 		csmask		= pvt->csels[dct].csmasks[csrow >> 1];
@@ -1150,6 +1172,21 @@
 	return ddr3_cs_size(cs_mode, false);
 }
  
+/*
+ * F16h has only limited cs_modes
+ */
+static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
+				unsigned cs_mode)
+{
+	WARN_ON(cs_mode > 12);
+
+	if (cs_mode == 6 || cs_mode == 8 ||
+	    cs_mode == 9 || cs_mode == 12)
+		return -1;
+	else
+		return ddr3_cs_size(cs_mode, false);
+}
+
 static void read_dram_ctl_register(struct amd64_pvt *pvt)
 {
  
@@ -1587,6 +1624,17 @@
 			.read_dct_pci_cfg	= f15_read_dct_pci_cfg,
 		}
 	},
+	[F16_CPUS] = {
+		.ctl_name = "F16h",
+		.f1_id = PCI_DEVICE_ID_AMD_16H_NB_F1,
+		.f3_id = PCI_DEVICE_ID_AMD_16H_NB_F3,
+		.ops = {
+			.early_channel_count	= f1x_early_channel_count,
+			.map_sysaddr_to_csrow	= f1x_map_sysaddr_to_csrow,
+			.dbam_to_cs		= f16_dbam_to_chip_select,
+			.read_dct_pci_cfg	= f10_read_dct_pci_cfg,
+		}
+	},
 };
  
 /*
@@ -1939,7 +1987,9 @@
  
 	if (c->x86 >= 0x10) {
 		amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);
-		amd64_read_dct_pci_cfg(pvt, DBAM1, &pvt->dbam1);
+		if (c->x86 != 0x16)
+			/* F16h has only DCT0 */
+			amd64_read_dct_pci_cfg(pvt, DBAM1, &pvt->dbam1);
  
 		/* F10h, revD and later can do x8 ECC too */
 		if ((c->x86 > 0x10 || c->x86_model > 7) && tmp & BIT(25))
@@ -2356,6 +2406,11 @@
 		pvt->ops		= &amd64_family_types[F15_CPUS].ops;
 		break;
  
+	case 0x16:
+		fam_type		= &amd64_family_types[F16_CPUS];
+		pvt->ops		= &amd64_family_types[F16_CPUS].ops;
+		break;
+
 	default:
 		amd64_err("Unsupported family!\n");
 		return NULL;
@@ -2576,6 +2631,14 @@
 	{
 		.vendor		= PCI_VENDOR_ID_AMD,
 		.device		= PCI_DEVICE_ID_AMD_15H_NB_F2,
+		.subvendor	= PCI_ANY_ID,
+		.subdevice	= PCI_ANY_ID,
+		.class		= 0,
+		.class_mask	= 0,
+	},
+	{
+		.vendor		= PCI_VENDOR_ID_AMD,
+		.device		= PCI_DEVICE_ID_AMD_16H_NB_F2,
 		.subvendor	= PCI_ANY_ID,
 		.subdevice	= PCI_ANY_ID,
 		.class		= 0,
@@ -172,8 +172,9 @@
  */
 #define PCI_DEVICE_ID_AMD_15H_NB_F1	0x1601
 #define PCI_DEVICE_ID_AMD_15H_NB_F2	0x1602
+#define PCI_DEVICE_ID_AMD_16H_NB_F1	0x1531
+#define PCI_DEVICE_ID_AMD_16H_NB_F2	0x1532
  
-
 /*
  * Function 1 - Address Map
  */
@@ -296,6 +297,7 @@
 	K8_CPUS = 0,
 	F10_CPUS,
 	F15_CPUS,
+	F16_CPUS,
 	NUM_FAMILIES,
 };
  
@@ -524,6 +524,8 @@
 #define PCI_DEVICE_ID_AMD_15H_NB_F3	0x1603
 #define PCI_DEVICE_ID_AMD_15H_NB_F4	0x1604
 #define PCI_DEVICE_ID_AMD_15H_NB_F5	0x1605
+#define PCI_DEVICE_ID_AMD_16H_NB_F3	0x1533
+#define PCI_DEVICE_ID_AMD_16H_NB_F4	0x1534
 #define PCI_DEVICE_ID_AMD_CNB17H_F3	0x1703
 #define PCI_DEVICE_ID_AMD_LANCE		0x2000
 #define PCI_DEVICE_ID_AMD_LANCE_HOME	0x2001
...	...	@@ -20,12 +20,14 @@
20	20	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
21	21	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
22	22	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
	23	+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
23	24	{}
24	25	};
25	26	EXPORT_SYMBOL(amd_nb_misc_ids);
26	27
27	28	static struct pci_device_id amd_nb_link_ids[] = {
28	29	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
	30	+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
29	31	{}
30	32	};
31	33
...	...	@@ -81,7 +83,6 @@
81	83	next_northbridge(link, amd_nb_link_ids);
82	84	}
83	85
84		- /* some CPU families (e.g. family 0x11) do not support GART */
85	86	if (boot_cpu_data.x86 == 0xf \|\| boot_cpu_data.x86 == 0x10 \|\|
86	87	boot_cpu_data.x86 == 0x15)
87	88	amd_northbridges.flags \|= AMD_NB_GART;
...	...	@@ -98,6 +98,7 @@
98	98	*
99	99	* F15h: we select which DCT we access using F1x10C[DctCfgSel]
100	100	*
	101	+ * F16h: has only 1 DCT
101	102	*/
102	103	static int k8_read_dct_pci_cfg(struct amd64_pvt pvt, int addr, u32 val,
103	104	const char *func)
...	...	@@ -340,6 +341,27 @@
340	341	base_bits = GENMASK(21, 31) \| GENMASK(9, 15);
341	342	mask_bits = GENMASK(21, 29) \| GENMASK(9, 15);
342	343	addr_shift = 4;
	344	+
	345	+ /*
	346	+ * F16h needs two addr_shift values: 8 for high and 6 for low
	347	+ * (cf. F16h BKDG).
	348	+ */
	349	+ } else if (boot_cpu_data.x86 == 0x16) {
	350	+ csbase = pvt->csels[dct].csbases[csrow];
	351	+ csmask = pvt->csels[dct].csmasks[csrow >> 1];
	352	+
	353	+ *base = (csbase & GENMASK(5, 15)) << 6;
	354	+ *base \|= (csbase & GENMASK(19, 30)) << 8;
	355	+
	356	+ *mask = ~0ULL;
	357	+ /* poke holes for the csmask */
	358	+ *mask &= ~((GENMASK(5, 15) << 6) \|
	359	+ (GENMASK(19, 30) << 8));
	360	+
	361	+ *mask \|= (csmask & GENMASK(5, 15)) << 6;
	362	+ *mask \|= (csmask & GENMASK(19, 30)) << 8;
	363	+
	364	+ return;
343	365	} else {
344	366	csbase = pvt->csels[dct].csbases[csrow];
345	367	csmask = pvt->csels[dct].csmasks[csrow >> 1];
...	...	@@ -1150,6 +1172,21 @@
1150	1172	return ddr3_cs_size(cs_mode, false);
1151	1173	}
1152	1174
	1175	+/*
	1176	+ * F16h has only limited cs_modes
	1177	+ */
	1178	+static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
	1179	+ unsigned cs_mode)
	1180	+{
	1181	+ WARN_ON(cs_mode > 12);
	1182	+
	1183	+ if (cs_mode == 6 \|\| cs_mode == 8 \|\|
	1184	+ cs_mode == 9 \|\| cs_mode == 12)
	1185	+ return -1;
	1186	+ else
	1187	+ return ddr3_cs_size(cs_mode, false);
	1188	+}
	1189	+
1153	1190	static void read_dram_ctl_register(struct amd64_pvt *pvt)
1154	1191	{
1155	1192
...	...	@@ -1587,6 +1624,17 @@
1587	1624	.read_dct_pci_cfg = f15_read_dct_pci_cfg,
1588	1625	}
1589	1626	},
	1627	+ [F16_CPUS] = {
	1628	+ .ctl_name = "F16h",
	1629	+ .f1_id = PCI_DEVICE_ID_AMD_16H_NB_F1,
	1630	+ .f3_id = PCI_DEVICE_ID_AMD_16H_NB_F3,
	1631	+ .ops = {
	1632	+ .early_channel_count = f1x_early_channel_count,
	1633	+ .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
	1634	+ .dbam_to_cs = f16_dbam_to_chip_select,
	1635	+ .read_dct_pci_cfg = f10_read_dct_pci_cfg,
	1636	+ }
	1637	+ },
1590	1638	};
1591	1639
1592	1640	/*
...	...	@@ -1939,7 +1987,9 @@
1939	1987
1940	1988	if (c->x86 >= 0x10) {
1941	1989	amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);
1942		- amd64_read_dct_pci_cfg(pvt, DBAM1, &pvt->dbam1);
	1990	+ if (c->x86 != 0x16)
	1991	+ /* F16h has only DCT0 */
	1992	+ amd64_read_dct_pci_cfg(pvt, DBAM1, &pvt->dbam1);
1943	1993
1944	1994	/* F10h, revD and later can do x8 ECC too */
1945	1995	if ((c->x86 > 0x10 \|\| c->x86_model > 7) && tmp & BIT(25))
...	...	@@ -2356,6 +2406,11 @@
2356	2406	pvt->ops = &amd64_family_types[F15_CPUS].ops;
2357	2407	break;
2358	2408
	2409	+ case 0x16:
	2410	+ fam_type = &amd64_family_types[F16_CPUS];
	2411	+ pvt->ops = &amd64_family_types[F16_CPUS].ops;
	2412	+ break;
	2413	+
2359	2414	default:
2360	2415	amd64_err("Unsupported family!\n");
2361	2416	return NULL;
...	...	@@ -2576,6 +2631,14 @@
2576	2631	{
2577	2632	.vendor = PCI_VENDOR_ID_AMD,
2578	2633	.device = PCI_DEVICE_ID_AMD_15H_NB_F2,
	2634	+ .subvendor = PCI_ANY_ID,
	2635	+ .subdevice = PCI_ANY_ID,
	2636	+ .class = 0,
	2637	+ .class_mask = 0,
	2638	+ },
	2639	+ {
	2640	+ .vendor = PCI_VENDOR_ID_AMD,
	2641	+ .device = PCI_DEVICE_ID_AMD_16H_NB_F2,
2579	2642	.subvendor = PCI_ANY_ID,
2580	2643	.subdevice = PCI_ANY_ID,
2581	2644	.class = 0,
...	...	@@ -172,8 +172,9 @@
172	172	*/
173	173	#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
174	174	#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
	175	+#define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
	176	+#define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
175	177
176		-
177	178	/*
178	179	* Function 1 - Address Map
179	180	*/
...	...	@@ -296,6 +297,7 @@
296	297	K8_CPUS = 0,
297	298	F10_CPUS,
298	299	F15_CPUS,
	300	+ F16_CPUS,
299	301	NUM_FAMILIES,
300	302	};
301	303
...	...	@@ -524,6 +524,8 @@
524	524	#define PCI_DEVICE_ID_AMD_15H_NB_F3 0x1603
525	525	#define PCI_DEVICE_ID_AMD_15H_NB_F4 0x1604
526	526	#define PCI_DEVICE_ID_AMD_15H_NB_F5 0x1605
	527	+#define PCI_DEVICE_ID_AMD_16H_NB_F3 0x1533
	528	+#define PCI_DEVICE_ID_AMD_16H_NB_F4 0x1534
527	529	#define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
528	530	#define PCI_DEVICE_ID_AMD_LANCE 0x2000
529	531	#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001