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Commit 96983ffefce46312e9372d357309dda413553009

Authored by Kevin Cernekee
Committed by Ralf Baechle
1 parent a648e81196
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines. 

This extends commit a8ca8b64e3fdfec17679cba0ca5ce6e3ffed092d to cover
MIPSxx-style board cache code.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Showing 1 changed file with 5 additions and 0 deletions Side-by-side Diff

arch/mips/mm/sc-mips.c
Diff comments   View file @ 96983ff
... ... @@ -32,6 +32,11 @@
32 32 */
33 33 static void mips_sc_inv(unsigned long addr, unsigned long size)
34 34 {
  35 + unsigned long lsize = cpu_scache_line_size();
  36 + unsigned long almask = ~(lsize - 1);
  37 +
  38 + cache_op(Hit_Writeback_Inv_SD, addr & almask);
  39 + cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
35 40 blast_inv_scache_range(addr, addr + size);
36 41 }
37 42