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Commit 977b58e1dd6fc2a751fb427798bfb8256476c93e

Authored by Linus Torvalds
2 parents f5b8fcb48b 2842e5b00e
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu 

Pull m68knommu updates from Greg Ungerer:
 "The bulk of the changes are generalizing the ColdFire v3 core support
  and adding in 537x CPU support.  Also a couple of other bug fixes, one
  to fix a reintroduction of a past bug in the romfs filesystem nommu
  support."

* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu:
  m68knommu: enable Timer on coldfire 532x
  m68knommu: fix ColdFire 5373/5329 QSPI base address
  m68knommu: add support for configuring a Freescale M5373EVB board
  m68knommu: add support for the ColdFire 537x family of CPUs
  m68knommu: make ColdFire M532x platform support more v3 generic
  m68knommu: create and use a common M53xx ColdFire class of CPUs
  m68k: remove unused asm/dbg.h
  m68k: Set ColdFire ACR1 cache mode depending on kernel configuration
  romfs: fix nommu map length to keep inside filesystem
  m68k: clean up unused "config ROMVECSIZE"

Showing 18 changed files Side-by-side Diff

arch/m68k/Kconfig.cpu
Diff comments   View file @ 977b58e
... ... @@ -223,12 +223,24 @@
223 223 help
224 224 Motorola ColdFire 5307 processor support.
225 225  
  226 +config M53xx
  227 + bool
  228 +
226 229 config M532x
227 230 bool "MCF532x"
228 231 depends on !MMU
  232 + select M53xx
229 233 select HAVE_CACHE_CB
230 234 help
231 235 Freescale (Motorola) ColdFire 532x processor support.
  236 +
  237 +config M537x
  238 + bool "MCF537x"
  239 + depends on !MMU
  240 + select M53xx
  241 + select HAVE_CACHE_CB
  242 + help
  243 + Freescale ColdFire 537x processor support.
232 244  
233 245 config M5407
234 246 bool "MCF5407"
arch/m68k/Kconfig.machine
Diff comments   View file @ 977b58e
... ... @@ -358,6 +358,13 @@
358 358 help
359 359 Support for the senTec COBRA5329 board.
360 360  
  361 +config M5373EVB
  362 + bool "Freescale M5373EVB board support"
  363 + depends on M537x
  364 + select FREESCALE
  365 + help
  366 + Support for the Freescale M5373EVB board.
  367 +
361 368 config M5407C3
362 369 bool "Motorola M5407C3 board support"
363 370 depends on M5407
... ... @@ -538,15 +545,6 @@
538 545 This is almost always the same as the base of the ROM. Since on all
539 546 68000 type variants the vectors are at the base of the boot device
540 547 on system startup.
541   -
542   -config ROMVECSIZE
543   - hex "Size of ROM vector region (in bytes)"
544   - default "0x400"
545   - depends on ROM
546   - help
547   - Define the size of the vector region in ROM. For most 68000
548   - variants this would be 0x400 bytes in size. Set to 0 if you do
549   - not want a vector region at the start of the ROM.
550 548  
551 549 config ROMSTART
552 550 hex "Address of the base of system image in ROM"
... ... @@ -45,6 +45,7 @@
45 45 cpuflags-$(CONFIG_M54xx) := $(call cc-option,-mcpu=5475,-m5200)
46 46 cpuflags-$(CONFIG_M5407) := $(call cc-option,-mcpu=5407,-m5200)
47 47 cpuflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307)
  48 +cpuflags-$(CONFIG_M537x) := $(call cc-option,-mcpu=537x,-m5307)
48 49 cpuflags-$(CONFIG_M5307) := $(call cc-option,-mcpu=5307,-m5200)
49 50 cpuflags-$(CONFIG_M528x) := $(call cc-option,-mcpu=528x,-m5307)
50 51 cpuflags-$(CONFIG_M5275) := $(call cc-option,-mcpu=5275,-m5307)
arch/m68k/include/asm/dbg.h
View file @ 977b58e
1   -#define DEBUG 1
2   -#ifdef CONFIG_COLDFIRE
3   -#define BREAK asm volatile ("halt")
4   -#else
5   -#define BREAK *(volatile unsigned char *)0xdeadbee0 = 0
6   -#endif
arch/m68k/include/asm/dma.h
Diff comments   View file @ 977b58e
... ... @@ -39,7 +39,7 @@
39 39 #define MAX_M68K_DMA_CHANNELS 4
40 40 #elif defined(CONFIG_M5272)
41 41 #define MAX_M68K_DMA_CHANNELS 1
42   -#elif defined(CONFIG_M532x)
  42 +#elif defined(CONFIG_M53xx)
43 43 #define MAX_M68K_DMA_CHANNELS 0
44 44 #else
45 45 #define MAX_M68K_DMA_CHANNELS 2
arch/m68k/include/asm/m532xsim.h
View file @ 977b58e
Changes suppressed. Click to show
1   -/****************************************************************************/
2   -
3   -/*
4   - * m532xsim.h -- ColdFire 5329 registers
5   - */
6   -
7   -/****************************************************************************/
8   -#ifndef m532xsim_h
9   -#define m532xsim_h
10   -/****************************************************************************/
11   -
12   -#define CPU_NAME "COLDFIRE(m532x)"
13   -#define CPU_INSTR_PER_JIFFY 3
14   -#define MCF_BUSCLK (MCF_CLK / 3)
15   -
16   -#include <asm/m53xxacr.h>
17   -
18   -#define MCFINT_VECBASE 64
19   -#define MCFINT_UART0 26 /* Interrupt number for UART0 */
20   -#define MCFINT_UART1 27 /* Interrupt number for UART1 */
21   -#define MCFINT_UART2 28 /* Interrupt number for UART2 */
22   -#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
23   -#define MCFINT_FECRX0 36 /* Interrupt number for FEC */
24   -#define MCFINT_FECTX0 40 /* Interrupt number for FEC */
25   -#define MCFINT_FECENTC0 42 /* Interrupt number for FEC */
26   -
27   -#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
28   -#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
29   -#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
30   -
31   -#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
32   -#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
33   -#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
34   -
35   -#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
36   -
37   -#define MCF_WTM_WCR 0xFC098000
38   -
39   -/*
40   - * Define the 532x SIM register set addresses.
41   - */
42   -#define MCFSIM_IPRL 0xFC048004
43   -#define MCFSIM_IPRH 0xFC048000
44   -#define MCFSIM_IPR MCFSIM_IPRL
45   -#define MCFSIM_IMRL 0xFC04800C
46   -#define MCFSIM_IMRH 0xFC048008
47   -#define MCFSIM_IMR MCFSIM_IMRL
48   -#define MCFSIM_ICR0 0xFC048040
49   -#define MCFSIM_ICR1 0xFC048041
50   -#define MCFSIM_ICR2 0xFC048042
51   -#define MCFSIM_ICR3 0xFC048043
52   -#define MCFSIM_ICR4 0xFC048044
53   -#define MCFSIM_ICR5 0xFC048045
54   -#define MCFSIM_ICR6 0xFC048046
55   -#define MCFSIM_ICR7 0xFC048047
56   -#define MCFSIM_ICR8 0xFC048048
57   -#define MCFSIM_ICR9 0xFC048049
58   -#define MCFSIM_ICR10 0xFC04804A
59   -#define MCFSIM_ICR11 0xFC04804B
60   -
61   -/*
62   - * Some symbol defines for the above...
63   - */
64   -#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
65   -#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
66   -#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
67   -#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
68   -#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
69   -#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
70   -#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
71   -#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
72   -#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
73   -
74   -
75   -#define MCFINTC0_SIMR 0xFC04801C
76   -#define MCFINTC0_CIMR 0xFC04801D
77   -#define MCFINTC0_ICR0 0xFC048040
78   -#define MCFINTC1_SIMR 0xFC04C01C
79   -#define MCFINTC1_CIMR 0xFC04C01D
80   -#define MCFINTC1_ICR0 0xFC04C040
81   -#define MCFINTC2_SIMR (0)
82   -#define MCFINTC2_CIMR (0)
83   -#define MCFINTC2_ICR0 (0)
84   -
85   -#define MCFSIM_ICR_TIMER1 (0xFC048040+32)
86   -#define MCFSIM_ICR_TIMER2 (0xFC048040+33)
87   -
88   -/*
89   - * Define system peripheral IRQ usage.
90   - */
91   -#define MCF_IRQ_TIMER (64 + 32) /* Timer0 */
92   -#define MCF_IRQ_PROFILER (64 + 33) /* Timer1 */
93   -
94   -/*
95   - * UART module.
96   - */
97   -#define MCFUART_BASE0 0xFC060000 /* Base address of UART1 */
98   -#define MCFUART_BASE1 0xFC064000 /* Base address of UART2 */
99   -#define MCFUART_BASE2 0xFC068000 /* Base address of UART3 */
100   -
101   -/*
102   - * FEC module.
103   - */
104   -#define MCFFEC_BASE0 0xFC030000 /* Base address of FEC0 */
105   -#define MCFFEC_SIZE0 0x800 /* Size of FEC0 region */
106   -
107   -/*
108   - * QSPI module.
109   - */
110   -#define MCFQSPI_BASE 0xFC058000 /* Base address of QSPI */
111   -#define MCFQSPI_SIZE 0x40 /* Size of QSPI region */
112   -
113   -#define MCFQSPI_CS0 84
114   -#define MCFQSPI_CS1 85
115   -#define MCFQSPI_CS2 86
116   -
117   -/*
118   - * Timer module.
119   - */
120   -#define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */
121   -#define MCFTIMER_BASE2 0xFC074000 /* Base address of TIMER2 */
122   -#define MCFTIMER_BASE3 0xFC078000 /* Base address of TIMER3 */
123   -#define MCFTIMER_BASE4 0xFC07C000 /* Base address of TIMER4 */
124   -
125   -/*********************************************************************
126   - *
127   - * Reset Controller Module
128   - *
129   - *********************************************************************/
130   -
131   -#define MCF_RCR 0xFC0A0000
132   -#define MCF_RSR 0xFC0A0001
133   -
134   -#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
135   -#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
136   -
137   -
138   -/*
139   - * Power Management
140   - */
141   -#define MCFPM_WCR 0xfc040013
142   -#define MCFPM_PPMSR0 0xfc04002c
143   -#define MCFPM_PPMCR0 0xfc04002d
144   -#define MCFPM_PPMSR1 0xfc04002e
145   -#define MCFPM_PPMCR1 0xfc04002f
146   -#define MCFPM_PPMHR0 0xfc040030
147   -#define MCFPM_PPMLR0 0xfc040034
148   -#define MCFPM_PPMHR1 0xfc040038
149   -#define MCFPM_LPCR 0xec090007
150   -
151   -/*
152   - * The M5329EVB board needs a help getting its devices initialized
153   - * at kernel start time if dBUG doesn't set it up (for example
154   - * it is not used), so we need to do it manually.
155   - */
156   -#ifdef __ASSEMBLER__
157   -.macro m5329EVB_setup
158   - movel #0xFC098000, %a7
159   - movel #0x0, (%a7)
160   -#define CORE_SRAM 0x80000000
161   -#define CORE_SRAM_SIZE 0x8000
162   - movel #CORE_SRAM, %d0
163   - addl #0x221, %d0
164   - movec %d0,%RAMBAR1
165   - movel #CORE_SRAM, %sp
166   - addl #CORE_SRAM_SIZE, %sp
167   - jsr sysinit
168   -.endm
169   -#define PLATFORM_SETUP m5329EVB_setup
170   -
171   -#endif /* __ASSEMBLER__ */
172   -
173   -/*********************************************************************
174   - *
175   - * Chip Configuration Module (CCM)
176   - *
177   - *********************************************************************/
178   -
179   -/* Register read/write macros */
180   -#define MCF_CCM_CCR 0xFC0A0004
181   -#define MCF_CCM_RCON 0xFC0A0008
182   -#define MCF_CCM_CIR 0xFC0A000A
183   -#define MCF_CCM_MISCCR 0xFC0A0010
184   -#define MCF_CCM_CDR 0xFC0A0012
185   -#define MCF_CCM_UHCSR 0xFC0A0014
186   -#define MCF_CCM_UOCSR 0xFC0A0016
187   -
188   -/* Bit definitions and macros for MCF_CCM_CCR */
189   -#define MCF_CCM_CCR_RESERVED (0x0001)
190   -#define MCF_CCM_CCR_PLL_MODE (0x0003)
191   -#define MCF_CCM_CCR_OSC_MODE (0x0005)
192   -#define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
193   -#define MCF_CCM_CCR_LOAD (0x0021)
194   -#define MCF_CCM_CCR_LIMP (0x0041)
195   -#define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001)
196   -
197   -/* Bit definitions and macros for MCF_CCM_RCON */
198   -#define MCF_CCM_RCON_RESERVED (0x0001)
199   -#define MCF_CCM_RCON_PLL_MODE (0x0003)
200   -#define MCF_CCM_RCON_OSC_MODE (0x0005)
201   -#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
202   -#define MCF_CCM_RCON_LOAD (0x0021)
203   -#define MCF_CCM_RCON_LIMP (0x0041)
204   -#define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001)
205   -
206   -/* Bit definitions and macros for MCF_CCM_CIR */
207   -#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0)
208   -#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
209   -
210   -/* Bit definitions and macros for MCF_CCM_MISCCR */
211   -#define MCF_CCM_MISCCR_USBSRC (0x0001)
212   -#define MCF_CCM_MISCCR_USBDIV (0x0002)
213   -#define MCF_CCM_MISCCR_SSI_SRC (0x0010)
214   -#define MCF_CCM_MISCCR_TIM_DMA (0x0020)
215   -#define MCF_CCM_MISCCR_SSI_PUS (0x0040)
216   -#define MCF_CCM_MISCCR_SSI_PUE (0x0080)
217   -#define MCF_CCM_MISCCR_LCD_CHEN (0x0100)
218   -#define MCF_CCM_MISCCR_LIMP (0x1000)
219   -#define MCF_CCM_MISCCR_PLL_LOCK (0x2000)
220   -
221   -/* Bit definitions and macros for MCF_CCM_CDR */
222   -#define MCF_CCM_CDR_SSIDIV(x) (((x)&0x000F)<<0)
223   -#define MCF_CCM_CDR_LPDIV(x) (((x)&0x000F)<<8)
224   -
225   -/* Bit definitions and macros for MCF_CCM_UHCSR */
226   -#define MCF_CCM_UHCSR_XPDE (0x0001)
227   -#define MCF_CCM_UHCSR_UHMIE (0x0002)
228   -#define MCF_CCM_UHCSR_WKUP (0x0004)
229   -#define MCF_CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14)
230   -
231   -/* Bit definitions and macros for MCF_CCM_UOCSR */
232   -#define MCF_CCM_UOCSR_XPDE (0x0001)
233   -#define MCF_CCM_UOCSR_UOMIE (0x0002)
234   -#define MCF_CCM_UOCSR_WKUP (0x0004)
235   -#define MCF_CCM_UOCSR_PWRFLT (0x0008)
236   -#define MCF_CCM_UOCSR_SEND (0x0010)
237   -#define MCF_CCM_UOCSR_VVLD (0x0020)
238   -#define MCF_CCM_UOCSR_BVLD (0x0040)
239   -#define MCF_CCM_UOCSR_AVLD (0x0080)
240   -#define MCF_CCM_UOCSR_DPPU (0x0100)
241   -#define MCF_CCM_UOCSR_DCR_VBUS (0x0200)
242   -#define MCF_CCM_UOCSR_CRG_VBUS (0x0400)
243   -#define MCF_CCM_UOCSR_DRV_VBUS (0x0800)
244   -#define MCF_CCM_UOCSR_DMPD (0x1000)
245   -#define MCF_CCM_UOCSR_DPPD (0x2000)
246   -#define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14)
247   -
248   -/*********************************************************************
249   - *
250   - * FlexBus Chip Selects (FBCS)
251   - *
252   - *********************************************************************/
253   -
254   -/* Register read/write macros */
255   -#define MCF_FBCS0_CSAR 0xFC008000
256   -#define MCF_FBCS0_CSMR 0xFC008004
257   -#define MCF_FBCS0_CSCR 0xFC008008
258   -#define MCF_FBCS1_CSAR 0xFC00800C
259   -#define MCF_FBCS1_CSMR 0xFC008010
260   -#define MCF_FBCS1_CSCR 0xFC008014
261   -#define MCF_FBCS2_CSAR 0xFC008018
262   -#define MCF_FBCS2_CSMR 0xFC00801C
263   -#define MCF_FBCS2_CSCR 0xFC008020
264   -#define MCF_FBCS3_CSAR 0xFC008024
265   -#define MCF_FBCS3_CSMR 0xFC008028
266   -#define MCF_FBCS3_CSCR 0xFC00802C
267   -#define MCF_FBCS4_CSAR 0xFC008030
268   -#define MCF_FBCS4_CSMR 0xFC008034
269   -#define MCF_FBCS4_CSCR 0xFC008038
270   -#define MCF_FBCS5_CSAR 0xFC00803C
271   -#define MCF_FBCS5_CSMR 0xFC008040
272   -#define MCF_FBCS5_CSCR 0xFC008044
273   -
274   -/* Bit definitions and macros for MCF_FBCS_CSAR */
275   -#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
276   -
277   -/* Bit definitions and macros for MCF_FBCS_CSMR */
278   -#define MCF_FBCS_CSMR_V (0x00000001)
279   -#define MCF_FBCS_CSMR_WP (0x00000100)
280   -#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16)
281   -#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
282   -#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
283   -#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
284   -#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
285   -#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
286   -#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000)
287   -#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000)
288   -#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000)
289   -#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000)
290   -#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000)
291   -#define MCF_FBCS_CSMR_BAM_8M (0x007F0000)
292   -#define MCF_FBCS_CSMR_BAM_4M (0x003F0000)
293   -#define MCF_FBCS_CSMR_BAM_2M (0x001F0000)
294   -#define MCF_FBCS_CSMR_BAM_1M (0x000F0000)
295   -#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000)
296   -#define MCF_FBCS_CSMR_BAM_512K (0x00070000)
297   -#define MCF_FBCS_CSMR_BAM_256K (0x00030000)
298   -#define MCF_FBCS_CSMR_BAM_128K (0x00010000)
299   -#define MCF_FBCS_CSMR_BAM_64K (0x00000000)
300   -
301   -/* Bit definitions and macros for MCF_FBCS_CSCR */
302   -#define MCF_FBCS_CSCR_BSTW (0x00000008)
303   -#define MCF_FBCS_CSCR_BSTR (0x00000010)
304   -#define MCF_FBCS_CSCR_BEM (0x00000020)
305   -#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6)
306   -#define MCF_FBCS_CSCR_AA (0x00000100)
307   -#define MCF_FBCS_CSCR_SBM (0x00000200)
308   -#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10)
309   -#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16)
310   -#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18)
311   -#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20)
312   -#define MCF_FBCS_CSCR_SWSEN (0x00800000)
313   -#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26)
314   -#define MCF_FBCS_CSCR_PS_8 (0x0040)
315   -#define MCF_FBCS_CSCR_PS_16 (0x0080)
316   -#define MCF_FBCS_CSCR_PS_32 (0x0000)
317   -
318   -/*********************************************************************
319   - *
320   - * General Purpose I/O (GPIO)
321   - *
322   - *********************************************************************/
323   -
324   -/* Register read/write macros */
325   -#define MCFGPIO_PODR_FECH (0xFC0A4000)
326   -#define MCFGPIO_PODR_FECL (0xFC0A4001)
327   -#define MCFGPIO_PODR_SSI (0xFC0A4002)
328   -#define MCFGPIO_PODR_BUSCTL (0xFC0A4003)
329   -#define MCFGPIO_PODR_BE (0xFC0A4004)
330   -#define MCFGPIO_PODR_CS (0xFC0A4005)
331   -#define MCFGPIO_PODR_PWM (0xFC0A4006)
332   -#define MCFGPIO_PODR_FECI2C (0xFC0A4007)
333   -#define MCFGPIO_PODR_UART (0xFC0A4009)
334   -#define MCFGPIO_PODR_QSPI (0xFC0A400A)
335   -#define MCFGPIO_PODR_TIMER (0xFC0A400B)
336   -#define MCFGPIO_PODR_LCDDATAH (0xFC0A400D)
337   -#define MCFGPIO_PODR_LCDDATAM (0xFC0A400E)
338   -#define MCFGPIO_PODR_LCDDATAL (0xFC0A400F)
339   -#define MCFGPIO_PODR_LCDCTLH (0xFC0A4010)
340   -#define MCFGPIO_PODR_LCDCTLL (0xFC0A4011)
341   -#define MCFGPIO_PDDR_FECH (0xFC0A4014)
342   -#define MCFGPIO_PDDR_FECL (0xFC0A4015)
343   -#define MCFGPIO_PDDR_SSI (0xFC0A4016)
344   -#define MCFGPIO_PDDR_BUSCTL (0xFC0A4017)
345   -#define MCFGPIO_PDDR_BE (0xFC0A4018)
346   -#define MCFGPIO_PDDR_CS (0xFC0A4019)
347   -#define MCFGPIO_PDDR_PWM (0xFC0A401A)
348   -#define MCFGPIO_PDDR_FECI2C (0xFC0A401B)
349   -#define MCFGPIO_PDDR_UART (0xFC0A401C)
350   -#define MCFGPIO_PDDR_QSPI (0xFC0A401E)
351   -#define MCFGPIO_PDDR_TIMER (0xFC0A401F)
352   -#define MCFGPIO_PDDR_LCDDATAH (0xFC0A4021)
353   -#define MCFGPIO_PDDR_LCDDATAM (0xFC0A4022)
354   -#define MCFGPIO_PDDR_LCDDATAL (0xFC0A4023)
355   -#define MCFGPIO_PDDR_LCDCTLH (0xFC0A4024)
356   -#define MCFGPIO_PDDR_LCDCTLL (0xFC0A4025)
357   -#define MCFGPIO_PPDSDR_FECH (0xFC0A4028)
358   -#define MCFGPIO_PPDSDR_FECL (0xFC0A4029)
359   -#define MCFGPIO_PPDSDR_SSI (0xFC0A402A)
360   -#define MCFGPIO_PPDSDR_BUSCTL (0xFC0A402B)
361   -#define MCFGPIO_PPDSDR_BE (0xFC0A402C)
362   -#define MCFGPIO_PPDSDR_CS (0xFC0A402D)
363   -#define MCFGPIO_PPDSDR_PWM (0xFC0A402E)
364   -#define MCFGPIO_PPDSDR_FECI2C (0xFC0A402F)
365   -#define MCFGPIO_PPDSDR_UART (0xFC0A4031)
366   -#define MCFGPIO_PPDSDR_QSPI (0xFC0A4032)
367   -#define MCFGPIO_PPDSDR_TIMER (0xFC0A4033)
368   -#define MCFGPIO_PPDSDR_LCDDATAH (0xFC0A4035)
369   -#define MCFGPIO_PPDSDR_LCDDATAM (0xFC0A4036)
370   -#define MCFGPIO_PPDSDR_LCDDATAL (0xFC0A4037)
371   -#define MCFGPIO_PPDSDR_LCDCTLH (0xFC0A4038)
372   -#define MCFGPIO_PPDSDR_LCDCTLL (0xFC0A4039)
373   -#define MCFGPIO_PCLRR_FECH (0xFC0A403C)
374   -#define MCFGPIO_PCLRR_FECL (0xFC0A403D)
375   -#define MCFGPIO_PCLRR_SSI (0xFC0A403E)
376   -#define MCFGPIO_PCLRR_BUSCTL (0xFC0A403F)
377   -#define MCFGPIO_PCLRR_BE (0xFC0A4040)
378   -#define MCFGPIO_PCLRR_CS (0xFC0A4041)
379   -#define MCFGPIO_PCLRR_PWM (0xFC0A4042)
380   -#define MCFGPIO_PCLRR_FECI2C (0xFC0A4043)
381   -#define MCFGPIO_PCLRR_UART (0xFC0A4045)
382   -#define MCFGPIO_PCLRR_QSPI (0xFC0A4046)
383   -#define MCFGPIO_PCLRR_TIMER (0xFC0A4047)
384   -#define MCFGPIO_PCLRR_LCDDATAH (0xFC0A4049)
385   -#define MCFGPIO_PCLRR_LCDDATAM (0xFC0A404A)
386   -#define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B)
387   -#define MCFGPIO_PCLRR_LCDCTLH (0xFC0A404C)
388   -#define MCFGPIO_PCLRR_LCDCTLL (0xFC0A404D)
389   -#define MCFGPIO_PAR_FEC (0xFC0A4050)
390   -#define MCFGPIO_PAR_PWM (0xFC0A4051)
391   -#define MCFGPIO_PAR_BUSCTL (0xFC0A4052)
392   -#define MCFGPIO_PAR_FECI2C (0xFC0A4053)
393   -#define MCFGPIO_PAR_BE (0xFC0A4054)
394   -#define MCFGPIO_PAR_CS (0xFC0A4055)
395   -#define MCFGPIO_PAR_SSI (0xFC0A4056)
396   -#define MCFGPIO_PAR_UART (0xFC0A4058)
397   -#define MCFGPIO_PAR_QSPI (0xFC0A405A)
398   -#define MCFGPIO_PAR_TIMER (0xFC0A405C)
399   -#define MCFGPIO_PAR_LCDDATA (0xFC0A405D)
400   -#define MCFGPIO_PAR_LCDCTL (0xFC0A405E)
401   -#define MCFGPIO_PAR_IRQ (0xFC0A4060)
402   -#define MCFGPIO_MSCR_FLEXBUS (0xFC0A4064)
403   -#define MCFGPIO_MSCR_SDRAM (0xFC0A4065)
404   -#define MCFGPIO_DSCR_I2C (0xFC0A4068)
405   -#define MCFGPIO_DSCR_PWM (0xFC0A4069)
406   -#define MCFGPIO_DSCR_FEC (0xFC0A406A)
407   -#define MCFGPIO_DSCR_UART (0xFC0A406B)
408   -#define MCFGPIO_DSCR_QSPI (0xFC0A406C)
409   -#define MCFGPIO_DSCR_TIMER (0xFC0A406D)
410   -#define MCFGPIO_DSCR_SSI (0xFC0A406E)
411   -#define MCFGPIO_DSCR_LCD (0xFC0A406F)
412   -#define MCFGPIO_DSCR_DEBUG (0xFC0A4070)
413   -#define MCFGPIO_DSCR_CLKRST (0xFC0A4071)
414   -#define MCFGPIO_DSCR_IRQ (0xFC0A4072)
415   -
416   -/* Bit definitions and macros for MCF_GPIO_PODR_FECH */
417   -#define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01)
418   -#define MCF_GPIO_PODR_FECH_PODR_FECH1 (0x02)
419   -#define MCF_GPIO_PODR_FECH_PODR_FECH2 (0x04)
420   -#define MCF_GPIO_PODR_FECH_PODR_FECH3 (0x08)
421   -#define MCF_GPIO_PODR_FECH_PODR_FECH4 (0x10)
422   -#define MCF_GPIO_PODR_FECH_PODR_FECH5 (0x20)
423   -#define MCF_GPIO_PODR_FECH_PODR_FECH6 (0x40)
424   -#define MCF_GPIO_PODR_FECH_PODR_FECH7 (0x80)
425   -
426   -/* Bit definitions and macros for MCF_GPIO_PODR_FECL */
427   -#define MCF_GPIO_PODR_FECL_PODR_FECL0 (0x01)
428   -#define MCF_GPIO_PODR_FECL_PODR_FECL1 (0x02)
429   -#define MCF_GPIO_PODR_FECL_PODR_FECL2 (0x04)
430   -#define MCF_GPIO_PODR_FECL_PODR_FECL3 (0x08)
431   -#define MCF_GPIO_PODR_FECL_PODR_FECL4 (0x10)
432   -#define MCF_GPIO_PODR_FECL_PODR_FECL5 (0x20)
433   -#define MCF_GPIO_PODR_FECL_PODR_FECL6 (0x40)
434   -#define MCF_GPIO_PODR_FECL_PODR_FECL7 (0x80)
435   -
436   -/* Bit definitions and macros for MCF_GPIO_PODR_SSI */
437   -#define MCF_GPIO_PODR_SSI_PODR_SSI0 (0x01)
438   -#define MCF_GPIO_PODR_SSI_PODR_SSI1 (0x02)
439   -#define MCF_GPIO_PODR_SSI_PODR_SSI2 (0x04)
440   -#define MCF_GPIO_PODR_SSI_PODR_SSI3 (0x08)
441   -#define MCF_GPIO_PODR_SSI_PODR_SSI4 (0x10)
442   -
443   -/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */
444   -#define MCF_GPIO_PODR_BUSCTL_POSDR_BUSCTL0 (0x01)
445   -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02)
446   -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04)
447   -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08)
448   -
449   -/* Bit definitions and macros for MCF_GPIO_PODR_BE */
450   -#define MCF_GPIO_PODR_BE_PODR_BE0 (0x01)
451   -#define MCF_GPIO_PODR_BE_PODR_BE1 (0x02)
452   -#define MCF_GPIO_PODR_BE_PODR_BE2 (0x04)
453   -#define MCF_GPIO_PODR_BE_PODR_BE3 (0x08)
454   -
455   -/* Bit definitions and macros for MCF_GPIO_PODR_CS */
456   -#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02)
457   -#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04)
458   -#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08)
459   -#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10)
460   -#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20)
461   -
462   -/* Bit definitions and macros for MCF_GPIO_PODR_PWM */
463   -#define MCF_GPIO_PODR_PWM_PODR_PWM2 (0x04)
464   -#define MCF_GPIO_PODR_PWM_PODR_PWM3 (0x08)
465   -#define MCF_GPIO_PODR_PWM_PODR_PWM4 (0x10)
466   -#define MCF_GPIO_PODR_PWM_PODR_PWM5 (0x20)
467   -
468   -/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
469   -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01)
470   -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02)
471   -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04)
472   -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08)
473   -
474   -/* Bit definitions and macros for MCF_GPIO_PODR_UART */
475   -#define MCF_GPIO_PODR_UART_PODR_UART0 (0x01)
476   -#define MCF_GPIO_PODR_UART_PODR_UART1 (0x02)
477   -#define MCF_GPIO_PODR_UART_PODR_UART2 (0x04)
478   -#define MCF_GPIO_PODR_UART_PODR_UART3 (0x08)
479   -#define MCF_GPIO_PODR_UART_PODR_UART4 (0x10)
480   -#define MCF_GPIO_PODR_UART_PODR_UART5 (0x20)
481   -#define MCF_GPIO_PODR_UART_PODR_UART6 (0x40)
482   -#define MCF_GPIO_PODR_UART_PODR_UART7 (0x80)
483   -
484   -/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */
485   -#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01)
486   -#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02)
487   -#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04)
488   -#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08)
489   -#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10)
490   -#define MCF_GPIO_PODR_QSPI_PODR_QSPI5 (0x20)
491   -
492   -/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */
493   -#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01)
494   -#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02)
495   -#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04)
496   -#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08)
497   -
498   -/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */
499   -#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0 (0x01)
500   -#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1 (0x02)
501   -
502   -/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */
503   -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0 (0x01)
504   -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1 (0x02)
505   -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2 (0x04)
506   -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3 (0x08)
507   -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4 (0x10)
508   -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5 (0x20)
509   -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6 (0x40)
510   -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7 (0x80)
511   -
512   -/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */
513   -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0 (0x01)
514   -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1 (0x02)
515   -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2 (0x04)
516   -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3 (0x08)
517   -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4 (0x10)
518   -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5 (0x20)
519   -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6 (0x40)
520   -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7 (0x80)
521   -
522   -/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */
523   -#define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0 (0x01)
524   -
525   -/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */
526   -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0 (0x01)
527   -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1 (0x02)
528   -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2 (0x04)
529   -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3 (0x08)
530   -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4 (0x10)
531   -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5 (0x20)
532   -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6 (0x40)
533   -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7 (0x80)
534   -
535   -/* Bit definitions and macros for MCF_GPIO_PDDR_FECH */
536   -#define MCF_GPIO_PDDR_FECH_PDDR_FECH0 (0x01)
537   -#define MCF_GPIO_PDDR_FECH_PDDR_FECH1 (0x02)
538   -#define MCF_GPIO_PDDR_FECH_PDDR_FECH2 (0x04)
539   -#define MCF_GPIO_PDDR_FECH_PDDR_FECH3 (0x08)
540   -#define MCF_GPIO_PDDR_FECH_PDDR_FECH4 (0x10)
541   -#define MCF_GPIO_PDDR_FECH_PDDR_FECH5 (0x20)
542   -#define MCF_GPIO_PDDR_FECH_PDDR_FECH6 (0x40)
543   -#define MCF_GPIO_PDDR_FECH_PDDR_FECH7 (0x80)
544   -
545   -/* Bit definitions and macros for MCF_GPIO_PDDR_FECL */
546   -#define MCF_GPIO_PDDR_FECL_PDDR_FECL0 (0x01)
547   -#define MCF_GPIO_PDDR_FECL_PDDR_FECL1 (0x02)
548   -#define MCF_GPIO_PDDR_FECL_PDDR_FECL2 (0x04)
549   -#define MCF_GPIO_PDDR_FECL_PDDR_FECL3 (0x08)
550   -#define MCF_GPIO_PDDR_FECL_PDDR_FECL4 (0x10)
551   -#define MCF_GPIO_PDDR_FECL_PDDR_FECL5 (0x20)
552   -#define MCF_GPIO_PDDR_FECL_PDDR_FECL6 (0x40)
553   -#define MCF_GPIO_PDDR_FECL_PDDR_FECL7 (0x80)
554   -
555   -/* Bit definitions and macros for MCF_GPIO_PDDR_SSI */
556   -#define MCF_GPIO_PDDR_SSI_PDDR_SSI0 (0x01)
557   -#define MCF_GPIO_PDDR_SSI_PDDR_SSI1 (0x02)
558   -#define MCF_GPIO_PDDR_SSI_PDDR_SSI2 (0x04)
559   -#define MCF_GPIO_PDDR_SSI_PDDR_SSI3 (0x08)
560   -#define MCF_GPIO_PDDR_SSI_PDDR_SSI4 (0x10)
561   -
562   -/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */
563   -#define MCF_GPIO_PDDR_BUSCTL_POSDR_BUSCTL0 (0x01)
564   -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02)
565   -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04)
566   -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08)
567   -
568   -/* Bit definitions and macros for MCF_GPIO_PDDR_BE */
569   -#define MCF_GPIO_PDDR_BE_PDDR_BE0 (0x01)
570   -#define MCF_GPIO_PDDR_BE_PDDR_BE1 (0x02)
571   -#define MCF_GPIO_PDDR_BE_PDDR_BE2 (0x04)
572   -#define MCF_GPIO_PDDR_BE_PDDR_BE3 (0x08)
573   -
574   -/* Bit definitions and macros for MCF_GPIO_PDDR_CS */
575   -#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02)
576   -#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04)
577   -#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08)
578   -#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10)
579   -#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20)
580   -
581   -/* Bit definitions and macros for MCF_GPIO_PDDR_PWM */
582   -#define MCF_GPIO_PDDR_PWM_PDDR_PWM2 (0x04)
583   -#define MCF_GPIO_PDDR_PWM_PDDR_PWM3 (0x08)
584   -#define MCF_GPIO_PDDR_PWM_PDDR_PWM4 (0x10)
585   -#define MCF_GPIO_PDDR_PWM_PDDR_PWM5 (0x20)
586   -
587   -/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
588   -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01)
589   -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02)
590   -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04)
591   -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08)
592   -
593   -/* Bit definitions and macros for MCF_GPIO_PDDR_UART */
594   -#define MCF_GPIO_PDDR_UART_PDDR_UART0 (0x01)
595   -#define MCF_GPIO_PDDR_UART_PDDR_UART1 (0x02)
596   -#define MCF_GPIO_PDDR_UART_PDDR_UART2 (0x04)
597   -#define MCF_GPIO_PDDR_UART_PDDR_UART3 (0x08)
598   -#define MCF_GPIO_PDDR_UART_PDDR_UART4 (0x10)
599   -#define MCF_GPIO_PDDR_UART_PDDR_UART5 (0x20)
600   -#define MCF_GPIO_PDDR_UART_PDDR_UART6 (0x40)
601   -#define MCF_GPIO_PDDR_UART_PDDR_UART7 (0x80)
602   -
603   -/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */
604   -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01)
605   -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02)
606   -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04)
607   -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08)
608   -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10)
609   -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5 (0x20)
610   -
611   -/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */
612   -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01)
613   -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02)
614   -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04)
615   -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08)
616   -
617   -/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */
618   -#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0 (0x01)
619   -#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1 (0x02)
620   -
621   -/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */
622   -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0 (0x01)
623   -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1 (0x02)
624   -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2 (0x04)
625   -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3 (0x08)
626   -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4 (0x10)
627   -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5 (0x20)
628   -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6 (0x40)
629   -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7 (0x80)
630   -
631   -/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */
632   -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0 (0x01)
633   -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1 (0x02)
634   -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2 (0x04)
635   -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3 (0x08)
636   -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4 (0x10)
637   -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5 (0x20)
638   -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6 (0x40)
639   -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7 (0x80)
640   -
641   -/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */
642   -#define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0 (0x01)
643   -
644   -/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */
645   -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0 (0x01)
646   -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1 (0x02)
647   -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2 (0x04)
648   -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3 (0x08)
649   -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4 (0x10)
650   -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5 (0x20)
651   -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6 (0x40)
652   -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7 (0x80)
653   -
654   -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */
655   -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0 (0x01)
656   -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1 (0x02)
657   -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2 (0x04)
658   -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3 (0x08)
659   -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4 (0x10)
660   -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5 (0x20)
661   -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6 (0x40)
662   -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7 (0x80)
663   -
664   -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */
665   -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0 (0x01)
666   -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1 (0x02)
667   -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2 (0x04)
668   -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3 (0x08)
669   -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4 (0x10)
670   -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5 (0x20)
671   -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6 (0x40)
672   -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7 (0x80)
673   -
674   -/* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */
675   -#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0 (0x01)
676   -#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1 (0x02)
677   -#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2 (0x04)
678   -#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3 (0x08)
679   -#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4 (0x10)
680   -
681   -/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */
682   -#define MCF_GPIO_PPDSDR_BUSCTL_POSDR_BUSCTL0 (0x01)
683   -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02)
684   -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04)
685   -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08)
686   -
687   -/* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */
688   -#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0 (0x01)
689   -#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1 (0x02)
690   -#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2 (0x04)
691   -#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3 (0x08)
692   -
693   -/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */
694   -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02)
695   -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04)
696   -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08)
697   -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10)
698   -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20)
699   -
700   -/* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */
701   -#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2 (0x04)
702   -#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3 (0x08)
703   -#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4 (0x10)
704   -#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5 (0x20)
705   -
706   -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
707   -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01)
708   -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02)
709   -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04)
710   -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08)
711   -
712   -/* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */
713   -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0 (0x01)
714   -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1 (0x02)
715   -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2 (0x04)
716   -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3 (0x08)
717   -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4 (0x10)
718   -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5 (0x20)
719   -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6 (0x40)
720   -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7 (0x80)
721   -
722   -/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */
723   -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01)
724   -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02)
725   -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04)
726   -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08)
727   -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10)
728   -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5 (0x20)
729   -
730   -/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */
731   -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01)
732   -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02)
733   -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04)
734   -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08)
735   -
736   -/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */
737   -#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0 (0x01)
738   -#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1 (0x02)
739   -
740   -/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */
741   -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0 (0x01)
742   -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1 (0x02)
743   -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2 (0x04)
744   -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3 (0x08)
745   -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4 (0x10)
746   -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5 (0x20)
747   -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6 (0x40)
748   -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7 (0x80)
749   -
750   -/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */
751   -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0 (0x01)
752   -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1 (0x02)
753   -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2 (0x04)
754   -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3 (0x08)
755   -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4 (0x10)
756   -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5 (0x20)
757   -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6 (0x40)
758   -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7 (0x80)
759   -
760   -/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */
761   -#define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0 (0x01)
762   -
763   -/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */
764   -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0 (0x01)
765   -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1 (0x02)
766   -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2 (0x04)
767   -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3 (0x08)
768   -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4 (0x10)
769   -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5 (0x20)
770   -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6 (0x40)
771   -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7 (0x80)
772   -
773   -/* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */
774   -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0 (0x01)
775   -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1 (0x02)
776   -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2 (0x04)
777   -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3 (0x08)
778   -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4 (0x10)
779   -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5 (0x20)
780   -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6 (0x40)
781   -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7 (0x80)
782   -
783   -/* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */
784   -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0 (0x01)
785   -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1 (0x02)
786   -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2 (0x04)
787   -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3 (0x08)
788   -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4 (0x10)
789   -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5 (0x20)
790   -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6 (0x40)
791   -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7 (0x80)
792   -
793   -/* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */
794   -#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0 (0x01)
795   -#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1 (0x02)
796   -#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2 (0x04)
797   -#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3 (0x08)
798   -#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4 (0x10)
799   -
800   -/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */
801   -#define MCF_GPIO_PCLRR_BUSCTL_POSDR_BUSCTL0 (0x01)
802   -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02)
803   -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04)
804   -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08)
805   -
806   -/* Bit definitions and macros for MCF_GPIO_PCLRR_BE */
807   -#define MCF_GPIO_PCLRR_BE_PCLRR_BE0 (0x01)
808   -#define MCF_GPIO_PCLRR_BE_PCLRR_BE1 (0x02)
809   -#define MCF_GPIO_PCLRR_BE_PCLRR_BE2 (0x04)
810   -#define MCF_GPIO_PCLRR_BE_PCLRR_BE3 (0x08)
811   -
812   -/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */
813   -#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02)
814   -#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04)
815   -#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08)
816   -#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10)
817   -#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20)
818   -
819   -/* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */
820   -#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2 (0x04)
821   -#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3 (0x08)
822   -#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4 (0x10)
823   -#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5 (0x20)
824   -
825   -/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
826   -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01)
827   -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02)
828   -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04)
829   -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08)
830   -
831   -/* Bit definitions and macros for MCF_GPIO_PCLRR_UART */
832   -#define MCF_GPIO_PCLRR_UART_PCLRR_UART0 (0x01)
833   -#define MCF_GPIO_PCLRR_UART_PCLRR_UART1 (0x02)
834   -#define MCF_GPIO_PCLRR_UART_PCLRR_UART2 (0x04)
835   -#define MCF_GPIO_PCLRR_UART_PCLRR_UART3 (0x08)
836   -#define MCF_GPIO_PCLRR_UART_PCLRR_UART4 (0x10)
837   -#define MCF_GPIO_PCLRR_UART_PCLRR_UART5 (0x20)
838   -#define MCF_GPIO_PCLRR_UART_PCLRR_UART6 (0x40)
839   -#define MCF_GPIO_PCLRR_UART_PCLRR_UART7 (0x80)
840   -
841   -/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */
842   -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01)
843   -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02)
844   -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04)
845   -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08)
846   -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10)
847   -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5 (0x20)
848   -
849   -/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */
850   -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01)
851   -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02)
852   -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04)
853   -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08)
854   -
855   -/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */
856   -#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0 (0x01)
857   -#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1 (0x02)
858   -
859   -/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */
860   -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0 (0x01)
861   -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1 (0x02)
862   -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2 (0x04)
863   -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3 (0x08)
864   -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4 (0x10)
865   -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5 (0x20)
866   -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6 (0x40)
867   -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7 (0x80)
868   -
869   -/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */
870   -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0 (0x01)
871   -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1 (0x02)
872   -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2 (0x04)
873   -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3 (0x08)
874   -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4 (0x10)
875   -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5 (0x20)
876   -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6 (0x40)
877   -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7 (0x80)
878   -
879   -/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */
880   -#define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01)
881   -
882   -/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */
883   -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0 (0x01)
884   -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1 (0x02)
885   -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2 (0x04)
886   -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3 (0x08)
887   -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4 (0x10)
888   -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5 (0x20)
889   -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6 (0x40)
890   -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7 (0x80)
891   -
892   -/* Bit definitions and macros for MCF_GPIO_PAR_FEC */
893   -#define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x) (((x)&0x03)<<0)
894   -#define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x) (((x)&0x03)<<2)
895   -#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO (0x00)
896   -#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1 (0x04)
897   -#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC (0x0C)
898   -#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO (0x00)
899   -#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART (0x01)
900   -#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC (0x03)
901   -
902   -/* Bit definitions and macros for MCF_GPIO_PAR_PWM */
903   -#define MCF_GPIO_PAR_PWM_PAR_PWM1(x) (((x)&0x03)<<0)
904   -#define MCF_GPIO_PAR_PWM_PAR_PWM3(x) (((x)&0x03)<<2)
905   -#define MCF_GPIO_PAR_PWM_PAR_PWM5 (0x10)
906   -#define MCF_GPIO_PAR_PWM_PAR_PWM7 (0x20)
907   -
908   -/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */
909   -#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x03)<<3)
910   -#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x20)
911   -#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x40)
912   -#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x80)
913   -#define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO (0x00)
914   -#define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE (0x80)
915   -#define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO (0x00)
916   -#define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA (0x40)
917   -#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO (0x00)
918   -#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB (0x20)
919   -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x00)
920   -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0 (0x10)
921   -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x18)
922   -
923   -/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */
924   -#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0)
925   -#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2)
926   -#define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x) (((x)&0x03)<<4)
927   -#define MCF_GPIO_PAR_FECI2C_PAR_MDC(x) (((x)&0x03)<<6)
928   -#define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO (0x00)
929   -#define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2 (0x40)
930   -#define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL (0x80)
931   -#define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC (0xC0)
932   -#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO (0x00)
933   -#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2 (0x10)
934   -#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA (0x20)
935   -#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO (0x30)
936   -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00)
937   -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
938   -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL (0x0C)
939   -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00)
940   -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
941   -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA (0x03)
942   -
943   -/* Bit definitions and macros for MCF_GPIO_PAR_BE */
944   -#define MCF_GPIO_PAR_BE_PAR_BE0 (0x01)
945   -#define MCF_GPIO_PAR_BE_PAR_BE1 (0x02)
946   -#define MCF_GPIO_PAR_BE_PAR_BE2 (0x04)
947   -#define MCF_GPIO_PAR_BE_PAR_BE3 (0x08)
948   -
949   -/* Bit definitions and macros for MCF_GPIO_PAR_CS */
950   -#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02)
951   -#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04)
952   -#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08)
953   -#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10)
954   -#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20)
955   -#define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO (0x00)
956   -#define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1 (0x01)
957   -#define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1 (0x03)
958   -
959   -/* Bit definitions and macros for MCF_GPIO_PAR_SSI */
960   -#define MCF_GPIO_PAR_SSI_PAR_MCLK (0x0080)
961   -#define MCF_GPIO_PAR_SSI_PAR_TXD(x) (((x)&0x0003)<<8)
962   -#define MCF_GPIO_PAR_SSI_PAR_RXD(x) (((x)&0x0003)<<10)
963   -#define MCF_GPIO_PAR_SSI_PAR_FS(x) (((x)&0x0003)<<12)
964   -#define MCF_GPIO_PAR_SSI_PAR_BCLK(x) (((x)&0x0003)<<14)
965   -
966   -/* Bit definitions and macros for MCF_GPIO_PAR_UART */
967   -#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0001)
968   -#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0002)
969   -#define MCF_GPIO_PAR_UART_PAR_URTS0 (0x0004)
970   -#define MCF_GPIO_PAR_UART_PAR_UCTS0 (0x0008)
971   -#define MCF_GPIO_PAR_UART_PAR_UTXD1(x) (((x)&0x0003)<<4)
972   -#define MCF_GPIO_PAR_UART_PAR_URXD1(x) (((x)&0x0003)<<6)
973   -#define MCF_GPIO_PAR_UART_PAR_URTS1(x) (((x)&0x0003)<<8)
974   -#define MCF_GPIO_PAR_UART_PAR_UCTS1(x) (((x)&0x0003)<<10)
975   -#define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO (0x0000)
976   -#define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK (0x0800)
977   -#define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7 (0x0400)
978   -#define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1 (0x0C00)
979   -#define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO (0x0000)
980   -#define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS (0x0200)
981   -#define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6 (0x0100)
982   -#define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1 (0x0300)
983   -#define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO (0x0000)
984   -#define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD (0x0080)
985   -#define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5 (0x0040)
986   -#define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1 (0x00C0)
987   -#define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO (0x0000)
988   -#define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD (0x0020)
989   -#define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4 (0x0010)
990   -#define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1 (0x0030)
991   -
992   -/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */
993   -#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x0003)<<4)
994   -#define MCF_GPIO_PAR_QSPI_PAR_DOUT(x) (((x)&0x0003)<<6)
995   -#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x0003)<<8)
996   -#define MCF_GPIO_PAR_QSPI_PAR_PCS0(x) (((x)&0x0003)<<10)
997   -#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x0003)<<12)
998   -#define MCF_GPIO_PAR_QSPI_PAR_PCS2(x) (((x)&0x0003)<<14)
999   -
1000   -/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
1001   -#define MCF_GPIO_PAR_TIMER_PAR_TIN0(x) (((x)&0x03)<<0)
1002   -#define MCF_GPIO_PAR_TIMER_PAR_TIN1(x) (((x)&0x03)<<2)
1003   -#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<4)
1004   -#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<6)
1005   -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO (0x00)
1006   -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3 (0x80)
1007   -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2 (0x40)
1008   -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3 (0xC0)
1009   -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO (0x00)
1010   -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2 (0x20)
1011   -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2 (0x10)
1012   -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2 (0x30)
1013   -#define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO (0x00)
1014   -#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1 (0x08)
1015   -#define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1 (0x04)
1016   -#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1 (0x0C)
1017   -#define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO (0x00)
1018   -#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0 (0x02)
1019   -#define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0 (0x01)
1020   -#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0 (0x03)
1021   -
1022   -/* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */
1023   -#define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x) (((x)&0x03)<<0)
1024   -#define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x) (((x)&0x03)<<2)
1025   -#define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x) (((x)&0x03)<<4)
1026   -#define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x) (((x)&0x03)<<6)
1027   -
1028   -/* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */
1029   -#define MCF_GPIO_PAR_LCDCTL_PAR_CLS (0x0001)
1030   -#define MCF_GPIO_PAR_LCDCTL_PAR_PS (0x0002)
1031   -#define MCF_GPIO_PAR_LCDCTL_PAR_REV (0x0004)
1032   -#define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR (0x0008)
1033   -#define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST (0x0010)
1034   -#define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK (0x0020)
1035   -#define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC (0x0040)
1036   -#define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC (0x0080)
1037   -#define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE (0x0100)
1038   -
1039   -/* Bit definitions and macros for MCF_GPIO_PAR_IRQ */
1040   -#define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x) (((x)&0x0003)<<4)
1041   -#define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x) (((x)&0x0003)<<6)
1042   -#define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x) (((x)&0x0003)<<8)
1043   -#define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x) (((x)&0x0003)<<10)
1044   -#define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x) (((x)&0x0003)<<12)
1045   -
1046   -/* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */
1047   -#define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x) (((x)&0x03)<<0)
1048   -#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x) (((x)&0x03)<<2)
1049   -#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x) (((x)&0x03)<<4)
1050   -
1051   -/* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */
1052   -#define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x) (((x)&0x03)<<0)
1053   -#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x) (((x)&0x03)<<2)
1054   -#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x) (((x)&0x03)<<4)
1055   -
1056   -/* Bit definitions and macros for MCF_GPIO_DSCR_I2C */
1057   -#define MCF_GPIO_DSCR_I2C_I2C_DSE(x) (((x)&0x03)<<0)
1058   -
1059   -/* Bit definitions and macros for MCF_GPIO_DSCR_PWM */
1060   -#define MCF_GPIO_DSCR_PWM_PWM_DSE(x) (((x)&0x03)<<0)
1061   -
1062   -/* Bit definitions and macros for MCF_GPIO_DSCR_FEC */
1063   -#define MCF_GPIO_DSCR_FEC_FEC_DSE(x) (((x)&0x03)<<0)
1064   -
1065   -/* Bit definitions and macros for MCF_GPIO_DSCR_UART */
1066   -#define MCF_GPIO_DSCR_UART_UART0_DSE(x) (((x)&0x03)<<0)
1067   -#define MCF_GPIO_DSCR_UART_UART1_DSE(x) (((x)&0x03)<<2)
1068   -
1069   -/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */
1070   -#define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x) (((x)&0x03)<<0)
1071   -
1072   -/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */
1073   -#define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x) (((x)&0x03)<<0)
1074   -
1075   -/* Bit definitions and macros for MCF_GPIO_DSCR_SSI */
1076   -#define MCF_GPIO_DSCR_SSI_SSI_DSE(x) (((x)&0x03)<<0)
1077   -
1078   -/* Bit definitions and macros for MCF_GPIO_DSCR_LCD */
1079   -#define MCF_GPIO_DSCR_LCD_LCD_DSE(x) (((x)&0x03)<<0)
1080   -
1081   -/* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */
1082   -#define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x) (((x)&0x03)<<0)
1083   -
1084   -/* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */
1085   -#define MCF_GPIO_DSCR_CLKRST_CLKRST_DSE(x) (((x)&0x03)<<0)
1086   -
1087   -/* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */
1088   -#define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0)
1089   -
1090   -/*
1091   - * Generic GPIO support
1092   - */
1093   -#define MCFGPIO_PODR MCFGPIO_PODR_FECH
1094   -#define MCFGPIO_PDDR MCFGPIO_PDDR_FECH
1095   -#define MCFGPIO_PPDR MCFGPIO_PPDSDR_FECH
1096   -#define MCFGPIO_SETR MCFGPIO_PPDSDR_FECH
1097   -#define MCFGPIO_CLRR MCFGPIO_PCLRR_FECH
1098   -
1099   -#define MCFGPIO_PIN_MAX 136
1100   -#define MCFGPIO_IRQ_MAX 8
1101   -#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
1102   -
1103   -/*********************************************************************
1104   - *
1105   - * Phase Locked Loop (PLL)
1106   - *
1107   - *********************************************************************/
1108   -
1109   -/* Register read/write macros */
1110   -#define MCF_PLL_PODR 0xFC0C0000
1111   -#define MCF_PLL_PLLCR 0xFC0C0004
1112   -#define MCF_PLL_PMDR 0xFC0C0008
1113   -#define MCF_PLL_PFDR 0xFC0C000C
1114   -
1115   -/* Bit definitions and macros for MCF_PLL_PODR */
1116   -#define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0)
1117   -#define MCF_PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4)
1118   -
1119   -/* Bit definitions and macros for MCF_PLL_PLLCR */
1120   -#define MCF_PLL_PLLCR_DITHDEV(x) (((x)&0x07)<<0)
1121   -#define MCF_PLL_PLLCR_DITHEN (0x80)
1122   -
1123   -/* Bit definitions and macros for MCF_PLL_PMDR */
1124   -#define MCF_PLL_PMDR_MODDIV(x) (((x)&0xFF)<<0)
1125   -
1126   -/* Bit definitions and macros for MCF_PLL_PFDR */
1127   -#define MCF_PLL_PFDR_MFD(x) (((x)&0xFF)<<0)
1128   -
1129   -/*********************************************************************
1130   - *
1131   - * System Control Module Registers (SCM)
1132   - *
1133   - *********************************************************************/
1134   -
1135   -/* Register read/write macros */
1136   -#define MCF_SCM_MPR 0xFC000000
1137   -#define MCF_SCM_PACRA 0xFC000020
1138   -#define MCF_SCM_PACRB 0xFC000024
1139   -#define MCF_SCM_PACRC 0xFC000028
1140   -#define MCF_SCM_PACRD 0xFC00002C
1141   -#define MCF_SCM_PACRE 0xFC000040
1142   -#define MCF_SCM_PACRF 0xFC000044
1143   -
1144   -#define MCF_SCM_BCR 0xFC040024
1145   -
1146   -/*********************************************************************
1147   - *
1148   - * SDRAM Controller (SDRAMC)
1149   - *
1150   - *********************************************************************/
1151   -
1152   -/* Register read/write macros */
1153   -#define MCF_SDRAMC_SDMR 0xFC0B8000
1154   -#define MCF_SDRAMC_SDCR 0xFC0B8004
1155   -#define MCF_SDRAMC_SDCFG1 0xFC0B8008
1156   -#define MCF_SDRAMC_SDCFG2 0xFC0B800C
1157   -#define MCF_SDRAMC_LIMP_FIX 0xFC0B8080
1158   -#define MCF_SDRAMC_SDDS 0xFC0B8100
1159   -#define MCF_SDRAMC_SDCS0 0xFC0B8110
1160   -#define MCF_SDRAMC_SDCS1 0xFC0B8114
1161   -#define MCF_SDRAMC_SDCS2 0xFC0B8118
1162   -#define MCF_SDRAMC_SDCS3 0xFC0B811C
1163   -
1164   -/* Bit definitions and macros for MCF_SDRAMC_SDMR */
1165   -#define MCF_SDRAMC_SDMR_CMD (0x00010000)
1166   -#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
1167   -#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30)
1168   -#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000)
1169   -#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
1170   -
1171   -/* Bit definitions and macros for MCF_SDRAMC_SDCR */
1172   -#define MCF_SDRAMC_SDCR_IPALL (0x00000002)
1173   -#define MCF_SDRAMC_SDCR_IREF (0x00000004)
1174   -#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8)
1175   -#define MCF_SDRAMC_SDCR_PS(x) (((x)&0x00000003)<<12)
1176   -#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
1177   -#define MCF_SDRAMC_SDCR_OE_RULE (0x00400000)
1178   -#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
1179   -#define MCF_SDRAMC_SDCR_REF (0x10000000)
1180   -#define MCF_SDRAMC_SDCR_DDR (0x20000000)
1181   -#define MCF_SDRAMC_SDCR_CKE (0x40000000)
1182   -#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
1183   -#define MCF_SDRAMC_SDCR_PS_16 (0x00002000)
1184   -#define MCF_SDRAMC_SDCR_PS_32 (0x00000000)
1185   -
1186   -/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
1187   -#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
1188   -#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
1189   -#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
1190   -#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
1191   -#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
1192   -#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
1193   -#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
1194   -
1195   -/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
1196   -#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
1197   -#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
1198   -#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
1199   -#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
1200   -
1201   -/* Device Errata - LIMP mode work around */
1202   -#define MCF_SDRAMC_REFRESH (0x40000000)
1203   -
1204   -/* Bit definitions and macros for MCF_SDRAMC_SDDS */
1205   -#define MCF_SDRAMC_SDDS_SB_D(x) (((x)&0x00000003)<<0)
1206   -#define MCF_SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2)
1207   -#define MCF_SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4)
1208   -#define MCF_SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6)
1209   -#define MCF_SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8)
1210   -
1211   -/* Bit definitions and macros for MCF_SDRAMC_SDCS */
1212   -#define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)<<0)
1213   -#define MCF_SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20)
1214   -#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
1215   -#define MCF_SDRAMC_SDCS_CSSZ_DIABLE (0x00000000)
1216   -#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
1217   -#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
1218   -#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
1219   -#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
1220   -#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
1221   -#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
1222   -#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
1223   -#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
1224   -#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
1225   -#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
1226   -#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
1227   -#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
1228   -#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
1229   -
1230   -/*
1231   - * Edge Port Module (EPORT)
1232   - */
1233   -#define MCFEPORT_EPPAR (0xFC094000)
1234   -#define MCFEPORT_EPDDR (0xFC094002)
1235   -#define MCFEPORT_EPIER (0xFC094003)
1236   -#define MCFEPORT_EPDR (0xFC094004)
1237   -#define MCFEPORT_EPPDR (0xFC094005)
1238   -#define MCFEPORT_EPFR (0xFC094006)
1239   -
1240   -/********************************************************************/
1241   -#endif /* m532xsim_h */
arch/m68k/include/asm/m53xxacr.h
Diff comments   View file @ 977b58e
... ... @@ -55,8 +55,8 @@
55 55 #define CACHE_SIZE 0x2000 /* 8k of unified cache */
56 56 #define ICACHE_SIZE CACHE_SIZE
57 57 #define DCACHE_SIZE CACHE_SIZE
58   -#elif defined(CONFIG_M532x)
59   -#define CACHE_SIZE 0x4000 /* 32k of unified cache */
  58 +#elif defined(CONFIG_M53xx)
  59 +#define CACHE_SIZE 0x4000 /* 16k of unified cache */
60 60 #define ICACHE_SIZE CACHE_SIZE
61 61 #define DCACHE_SIZE CACHE_SIZE
62 62 #endif
arch/m68k/include/asm/m53xxsim.h
Diff comments   View file @ 977b58e
Changes suppressed. Click to show
  1 +/****************************************************************************/
  2 +
  3 +/*
  4 + * m53xxsim.h -- ColdFire 5329 registers
  5 + */
  6 +
  7 +/****************************************************************************/
  8 +#ifndef m53xxsim_h
  9 +#define m53xxsim_h
  10 +/****************************************************************************/
  11 +
  12 +#define CPU_NAME "COLDFIRE(m53xx)"
  13 +#define CPU_INSTR_PER_JIFFY 3
  14 +#define MCF_BUSCLK (MCF_CLK / 3)
  15 +
  16 +#include <asm/m53xxacr.h>
  17 +
  18 +#define MCFINT_VECBASE 64
  19 +#define MCFINT_UART0 26 /* Interrupt number for UART0 */
  20 +#define MCFINT_UART1 27 /* Interrupt number for UART1 */
  21 +#define MCFINT_UART2 28 /* Interrupt number for UART2 */
  22 +#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
  23 +#define MCFINT_FECRX0 36 /* Interrupt number for FEC */
  24 +#define MCFINT_FECTX0 40 /* Interrupt number for FEC */
  25 +#define MCFINT_FECENTC0 42 /* Interrupt number for FEC */
  26 +
  27 +#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
  28 +#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
  29 +#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
  30 +
  31 +#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
  32 +#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
  33 +#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
  34 +
  35 +#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
  36 +
  37 +#define MCF_WTM_WCR 0xFC098000
  38 +
  39 +/*
  40 + * Define the 532x SIM register set addresses.
  41 + */
  42 +#define MCFSIM_IPRL 0xFC048004
  43 +#define MCFSIM_IPRH 0xFC048000
  44 +#define MCFSIM_IPR MCFSIM_IPRL
  45 +#define MCFSIM_IMRL 0xFC04800C
  46 +#define MCFSIM_IMRH 0xFC048008
  47 +#define MCFSIM_IMR MCFSIM_IMRL
  48 +#define MCFSIM_ICR0 0xFC048040
  49 +#define MCFSIM_ICR1 0xFC048041
  50 +#define MCFSIM_ICR2 0xFC048042
  51 +#define MCFSIM_ICR3 0xFC048043
  52 +#define MCFSIM_ICR4 0xFC048044
  53 +#define MCFSIM_ICR5 0xFC048045
  54 +#define MCFSIM_ICR6 0xFC048046
  55 +#define MCFSIM_ICR7 0xFC048047
  56 +#define MCFSIM_ICR8 0xFC048048
  57 +#define MCFSIM_ICR9 0xFC048049
  58 +#define MCFSIM_ICR10 0xFC04804A
  59 +#define MCFSIM_ICR11 0xFC04804B
  60 +
  61 +/*
  62 + * Some symbol defines for the above...
  63 + */
  64 +#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
  65 +#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
  66 +#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
  67 +#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
  68 +#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
  69 +#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
  70 +#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
  71 +#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
  72 +#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
  73 +
  74 +
  75 +#define MCFINTC0_SIMR 0xFC04801C
  76 +#define MCFINTC0_CIMR 0xFC04801D
  77 +#define MCFINTC0_ICR0 0xFC048040
  78 +#define MCFINTC1_SIMR 0xFC04C01C
  79 +#define MCFINTC1_CIMR 0xFC04C01D
  80 +#define MCFINTC1_ICR0 0xFC04C040
  81 +#define MCFINTC2_SIMR (0)
  82 +#define MCFINTC2_CIMR (0)
  83 +#define MCFINTC2_ICR0 (0)
  84 +
  85 +#define MCFSIM_ICR_TIMER1 (0xFC048040+32)
  86 +#define MCFSIM_ICR_TIMER2 (0xFC048040+33)
  87 +
  88 +/*
  89 + * Define system peripheral IRQ usage.
  90 + */
  91 +#define MCF_IRQ_TIMER (64 + 32) /* Timer0 */
  92 +#define MCF_IRQ_PROFILER (64 + 33) /* Timer1 */
  93 +
  94 +/*
  95 + * UART module.
  96 + */
  97 +#define MCFUART_BASE0 0xFC060000 /* Base address of UART1 */
  98 +#define MCFUART_BASE1 0xFC064000 /* Base address of UART2 */
  99 +#define MCFUART_BASE2 0xFC068000 /* Base address of UART3 */
  100 +
  101 +/*
  102 + * FEC module.
  103 + */
  104 +#define MCFFEC_BASE0 0xFC030000 /* Base address of FEC0 */
  105 +#define MCFFEC_SIZE0 0x800 /* Size of FEC0 region */
  106 +
  107 +/*
  108 + * QSPI module.
  109 + */
  110 +#define MCFQSPI_BASE 0xFC05C000 /* Base address of QSPI */
  111 +#define MCFQSPI_SIZE 0x40 /* Size of QSPI region */
  112 +
  113 +#define MCFQSPI_CS0 84
  114 +#define MCFQSPI_CS1 85
  115 +#define MCFQSPI_CS2 86
  116 +
  117 +/*
  118 + * Timer module.
  119 + */
  120 +#define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */
  121 +#define MCFTIMER_BASE2 0xFC074000 /* Base address of TIMER2 */
  122 +#define MCFTIMER_BASE3 0xFC078000 /* Base address of TIMER3 */
  123 +#define MCFTIMER_BASE4 0xFC07C000 /* Base address of TIMER4 */
  124 +
  125 +/*********************************************************************
  126 + *
  127 + * Reset Controller Module
  128 + *
  129 + *********************************************************************/
  130 +
  131 +#define MCF_RCR 0xFC0A0000
  132 +#define MCF_RSR 0xFC0A0001
  133 +
  134 +#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
  135 +#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
  136 +
  137 +
  138 +/*
  139 + * Power Management
  140 + */
  141 +#define MCFPM_WCR 0xfc040013
  142 +#define MCFPM_PPMSR0 0xfc04002c
  143 +#define MCFPM_PPMCR0 0xfc04002d
  144 +#define MCFPM_PPMSR1 0xfc04002e
  145 +#define MCFPM_PPMCR1 0xfc04002f
  146 +#define MCFPM_PPMHR0 0xfc040030
  147 +#define MCFPM_PPMLR0 0xfc040034
  148 +#define MCFPM_PPMHR1 0xfc040038
  149 +#define MCFPM_LPCR 0xec090007
  150 +
  151 +/*
  152 + * The M5329EVB board needs a help getting its devices initialized
  153 + * at kernel start time if dBUG doesn't set it up (for example
  154 + * it is not used), so we need to do it manually.
  155 + */
  156 +#ifdef __ASSEMBLER__
  157 +.macro m5329EVB_setup
  158 + movel #0xFC098000, %a7
  159 + movel #0x0, (%a7)
  160 +#define CORE_SRAM 0x80000000
  161 +#define CORE_SRAM_SIZE 0x8000
  162 + movel #CORE_SRAM, %d0
  163 + addl #0x221, %d0
  164 + movec %d0,%RAMBAR1
  165 + movel #CORE_SRAM, %sp
  166 + addl #CORE_SRAM_SIZE, %sp
  167 + jsr sysinit
  168 +.endm
  169 +#define PLATFORM_SETUP m5329EVB_setup
  170 +
  171 +#endif /* __ASSEMBLER__ */
  172 +
  173 +/*********************************************************************
  174 + *
  175 + * Chip Configuration Module (CCM)
  176 + *
  177 + *********************************************************************/
  178 +
  179 +/* Register read/write macros */
  180 +#define MCF_CCM_CCR 0xFC0A0004
  181 +#define MCF_CCM_RCON 0xFC0A0008
  182 +#define MCF_CCM_CIR 0xFC0A000A
  183 +#define MCF_CCM_MISCCR 0xFC0A0010
  184 +#define MCF_CCM_CDR 0xFC0A0012
  185 +#define MCF_CCM_UHCSR 0xFC0A0014
  186 +#define MCF_CCM_UOCSR 0xFC0A0016
  187 +
  188 +/* Bit definitions and macros for MCF_CCM_CCR */
  189 +#define MCF_CCM_CCR_RESERVED (0x0001)
  190 +#define MCF_CCM_CCR_PLL_MODE (0x0003)
  191 +#define MCF_CCM_CCR_OSC_MODE (0x0005)
  192 +#define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
  193 +#define MCF_CCM_CCR_LOAD (0x0021)
  194 +#define MCF_CCM_CCR_LIMP (0x0041)
  195 +#define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001)
  196 +
  197 +/* Bit definitions and macros for MCF_CCM_RCON */
  198 +#define MCF_CCM_RCON_RESERVED (0x0001)
  199 +#define MCF_CCM_RCON_PLL_MODE (0x0003)
  200 +#define MCF_CCM_RCON_OSC_MODE (0x0005)
  201 +#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
  202 +#define MCF_CCM_RCON_LOAD (0x0021)
  203 +#define MCF_CCM_RCON_LIMP (0x0041)
  204 +#define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001)
  205 +
  206 +/* Bit definitions and macros for MCF_CCM_CIR */
  207 +#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0)
  208 +#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
  209 +
  210 +/* Bit definitions and macros for MCF_CCM_MISCCR */
  211 +#define MCF_CCM_MISCCR_USBSRC (0x0001)
  212 +#define MCF_CCM_MISCCR_USBDIV (0x0002)
  213 +#define MCF_CCM_MISCCR_SSI_SRC (0x0010)
  214 +#define MCF_CCM_MISCCR_TIM_DMA (0x0020)
  215 +#define MCF_CCM_MISCCR_SSI_PUS (0x0040)
  216 +#define MCF_CCM_MISCCR_SSI_PUE (0x0080)
  217 +#define MCF_CCM_MISCCR_LCD_CHEN (0x0100)
  218 +#define MCF_CCM_MISCCR_LIMP (0x1000)
  219 +#define MCF_CCM_MISCCR_PLL_LOCK (0x2000)
  220 +
  221 +/* Bit definitions and macros for MCF_CCM_CDR */
  222 +#define MCF_CCM_CDR_SSIDIV(x) (((x)&0x000F)<<0)
  223 +#define MCF_CCM_CDR_LPDIV(x) (((x)&0x000F)<<8)
  224 +
  225 +/* Bit definitions and macros for MCF_CCM_UHCSR */
  226 +#define MCF_CCM_UHCSR_XPDE (0x0001)
  227 +#define MCF_CCM_UHCSR_UHMIE (0x0002)
  228 +#define MCF_CCM_UHCSR_WKUP (0x0004)
  229 +#define MCF_CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14)
  230 +
  231 +/* Bit definitions and macros for MCF_CCM_UOCSR */
  232 +#define MCF_CCM_UOCSR_XPDE (0x0001)
  233 +#define MCF_CCM_UOCSR_UOMIE (0x0002)
  234 +#define MCF_CCM_UOCSR_WKUP (0x0004)
  235 +#define MCF_CCM_UOCSR_PWRFLT (0x0008)
  236 +#define MCF_CCM_UOCSR_SEND (0x0010)
  237 +#define MCF_CCM_UOCSR_VVLD (0x0020)
  238 +#define MCF_CCM_UOCSR_BVLD (0x0040)
  239 +#define MCF_CCM_UOCSR_AVLD (0x0080)
  240 +#define MCF_CCM_UOCSR_DPPU (0x0100)
  241 +#define MCF_CCM_UOCSR_DCR_VBUS (0x0200)
  242 +#define MCF_CCM_UOCSR_CRG_VBUS (0x0400)
  243 +#define MCF_CCM_UOCSR_DRV_VBUS (0x0800)
  244 +#define MCF_CCM_UOCSR_DMPD (0x1000)
  245 +#define MCF_CCM_UOCSR_DPPD (0x2000)
  246 +#define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14)
  247 +
  248 +/*********************************************************************
  249 + *
  250 + * FlexBus Chip Selects (FBCS)
  251 + *
  252 + *********************************************************************/
  253 +
  254 +/* Register read/write macros */
  255 +#define MCF_FBCS0_CSAR 0xFC008000
  256 +#define MCF_FBCS0_CSMR 0xFC008004
  257 +#define MCF_FBCS0_CSCR 0xFC008008
  258 +#define MCF_FBCS1_CSAR 0xFC00800C
  259 +#define MCF_FBCS1_CSMR 0xFC008010
  260 +#define MCF_FBCS1_CSCR 0xFC008014
  261 +#define MCF_FBCS2_CSAR 0xFC008018
  262 +#define MCF_FBCS2_CSMR 0xFC00801C
  263 +#define MCF_FBCS2_CSCR 0xFC008020
  264 +#define MCF_FBCS3_CSAR 0xFC008024
  265 +#define MCF_FBCS3_CSMR 0xFC008028
  266 +#define MCF_FBCS3_CSCR 0xFC00802C
  267 +#define MCF_FBCS4_CSAR 0xFC008030
  268 +#define MCF_FBCS4_CSMR 0xFC008034
  269 +#define MCF_FBCS4_CSCR 0xFC008038
  270 +#define MCF_FBCS5_CSAR 0xFC00803C
  271 +#define MCF_FBCS5_CSMR 0xFC008040
  272 +#define MCF_FBCS5_CSCR 0xFC008044
  273 +
  274 +/* Bit definitions and macros for MCF_FBCS_CSAR */
  275 +#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
  276 +
  277 +/* Bit definitions and macros for MCF_FBCS_CSMR */
  278 +#define MCF_FBCS_CSMR_V (0x00000001)
  279 +#define MCF_FBCS_CSMR_WP (0x00000100)
  280 +#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16)
  281 +#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
  282 +#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
  283 +#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
  284 +#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
  285 +#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
  286 +#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000)
  287 +#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000)
  288 +#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000)
  289 +#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000)
  290 +#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000)
  291 +#define MCF_FBCS_CSMR_BAM_8M (0x007F0000)
  292 +#define MCF_FBCS_CSMR_BAM_4M (0x003F0000)
  293 +#define MCF_FBCS_CSMR_BAM_2M (0x001F0000)
  294 +#define MCF_FBCS_CSMR_BAM_1M (0x000F0000)
  295 +#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000)
  296 +#define MCF_FBCS_CSMR_BAM_512K (0x00070000)
  297 +#define MCF_FBCS_CSMR_BAM_256K (0x00030000)
  298 +#define MCF_FBCS_CSMR_BAM_128K (0x00010000)
  299 +#define MCF_FBCS_CSMR_BAM_64K (0x00000000)
  300 +
  301 +/* Bit definitions and macros for MCF_FBCS_CSCR */
  302 +#define MCF_FBCS_CSCR_BSTW (0x00000008)
  303 +#define MCF_FBCS_CSCR_BSTR (0x00000010)
  304 +#define MCF_FBCS_CSCR_BEM (0x00000020)
  305 +#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6)
  306 +#define MCF_FBCS_CSCR_AA (0x00000100)
  307 +#define MCF_FBCS_CSCR_SBM (0x00000200)
  308 +#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10)
  309 +#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16)
  310 +#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18)
  311 +#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20)
  312 +#define MCF_FBCS_CSCR_SWSEN (0x00800000)
  313 +#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26)
  314 +#define MCF_FBCS_CSCR_PS_8 (0x0040)
  315 +#define MCF_FBCS_CSCR_PS_16 (0x0080)
  316 +#define MCF_FBCS_CSCR_PS_32 (0x0000)
  317 +
  318 +/*********************************************************************
  319 + *
  320 + * General Purpose I/O (GPIO)
  321 + *
  322 + *********************************************************************/
  323 +
  324 +/* Register read/write macros */
  325 +#define MCFGPIO_PODR_FECH (0xFC0A4000)
  326 +#define MCFGPIO_PODR_FECL (0xFC0A4001)
  327 +#define MCFGPIO_PODR_SSI (0xFC0A4002)
  328 +#define MCFGPIO_PODR_BUSCTL (0xFC0A4003)
  329 +#define MCFGPIO_PODR_BE (0xFC0A4004)
  330 +#define MCFGPIO_PODR_CS (0xFC0A4005)
  331 +#define MCFGPIO_PODR_PWM (0xFC0A4006)
  332 +#define MCFGPIO_PODR_FECI2C (0xFC0A4007)
  333 +#define MCFGPIO_PODR_UART (0xFC0A4009)
  334 +#define MCFGPIO_PODR_QSPI (0xFC0A400A)
  335 +#define MCFGPIO_PODR_TIMER (0xFC0A400B)
  336 +#define MCFGPIO_PODR_LCDDATAH (0xFC0A400D)
  337 +#define MCFGPIO_PODR_LCDDATAM (0xFC0A400E)
  338 +#define MCFGPIO_PODR_LCDDATAL (0xFC0A400F)
  339 +#define MCFGPIO_PODR_LCDCTLH (0xFC0A4010)
  340 +#define MCFGPIO_PODR_LCDCTLL (0xFC0A4011)
  341 +#define MCFGPIO_PDDR_FECH (0xFC0A4014)
  342 +#define MCFGPIO_PDDR_FECL (0xFC0A4015)
  343 +#define MCFGPIO_PDDR_SSI (0xFC0A4016)
  344 +#define MCFGPIO_PDDR_BUSCTL (0xFC0A4017)
  345 +#define MCFGPIO_PDDR_BE (0xFC0A4018)
  346 +#define MCFGPIO_PDDR_CS (0xFC0A4019)
  347 +#define MCFGPIO_PDDR_PWM (0xFC0A401A)
  348 +#define MCFGPIO_PDDR_FECI2C (0xFC0A401B)
  349 +#define MCFGPIO_PDDR_UART (0xFC0A401C)
  350 +#define MCFGPIO_PDDR_QSPI (0xFC0A401E)
  351 +#define MCFGPIO_PDDR_TIMER (0xFC0A401F)
  352 +#define MCFGPIO_PDDR_LCDDATAH (0xFC0A4021)
  353 +#define MCFGPIO_PDDR_LCDDATAM (0xFC0A4022)
  354 +#define MCFGPIO_PDDR_LCDDATAL (0xFC0A4023)
  355 +#define MCFGPIO_PDDR_LCDCTLH (0xFC0A4024)
  356 +#define MCFGPIO_PDDR_LCDCTLL (0xFC0A4025)
  357 +#define MCFGPIO_PPDSDR_FECH (0xFC0A4028)
  358 +#define MCFGPIO_PPDSDR_FECL (0xFC0A4029)
  359 +#define MCFGPIO_PPDSDR_SSI (0xFC0A402A)
  360 +#define MCFGPIO_PPDSDR_BUSCTL (0xFC0A402B)
  361 +#define MCFGPIO_PPDSDR_BE (0xFC0A402C)
  362 +#define MCFGPIO_PPDSDR_CS (0xFC0A402D)
  363 +#define MCFGPIO_PPDSDR_PWM (0xFC0A402E)
  364 +#define MCFGPIO_PPDSDR_FECI2C (0xFC0A402F)
  365 +#define MCFGPIO_PPDSDR_UART (0xFC0A4031)
  366 +#define MCFGPIO_PPDSDR_QSPI (0xFC0A4032)
  367 +#define MCFGPIO_PPDSDR_TIMER (0xFC0A4033)
  368 +#define MCFGPIO_PPDSDR_LCDDATAH (0xFC0A4035)
  369 +#define MCFGPIO_PPDSDR_LCDDATAM (0xFC0A4036)
  370 +#define MCFGPIO_PPDSDR_LCDDATAL (0xFC0A4037)
  371 +#define MCFGPIO_PPDSDR_LCDCTLH (0xFC0A4038)
  372 +#define MCFGPIO_PPDSDR_LCDCTLL (0xFC0A4039)
  373 +#define MCFGPIO_PCLRR_FECH (0xFC0A403C)
  374 +#define MCFGPIO_PCLRR_FECL (0xFC0A403D)
  375 +#define MCFGPIO_PCLRR_SSI (0xFC0A403E)
  376 +#define MCFGPIO_PCLRR_BUSCTL (0xFC0A403F)
  377 +#define MCFGPIO_PCLRR_BE (0xFC0A4040)
  378 +#define MCFGPIO_PCLRR_CS (0xFC0A4041)
  379 +#define MCFGPIO_PCLRR_PWM (0xFC0A4042)
  380 +#define MCFGPIO_PCLRR_FECI2C (0xFC0A4043)
  381 +#define MCFGPIO_PCLRR_UART (0xFC0A4045)
  382 +#define MCFGPIO_PCLRR_QSPI (0xFC0A4046)
  383 +#define MCFGPIO_PCLRR_TIMER (0xFC0A4047)
  384 +#define MCFGPIO_PCLRR_LCDDATAH (0xFC0A4049)
  385 +#define MCFGPIO_PCLRR_LCDDATAM (0xFC0A404A)
  386 +#define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B)
  387 +#define MCFGPIO_PCLRR_LCDCTLH (0xFC0A404C)
  388 +#define MCFGPIO_PCLRR_LCDCTLL (0xFC0A404D)
  389 +#define MCFGPIO_PAR_FEC (0xFC0A4050)
  390 +#define MCFGPIO_PAR_PWM (0xFC0A4051)
  391 +#define MCFGPIO_PAR_BUSCTL (0xFC0A4052)
  392 +#define MCFGPIO_PAR_FECI2C (0xFC0A4053)
  393 +#define MCFGPIO_PAR_BE (0xFC0A4054)
  394 +#define MCFGPIO_PAR_CS (0xFC0A4055)
  395 +#define MCFGPIO_PAR_SSI (0xFC0A4056)
  396 +#define MCFGPIO_PAR_UART (0xFC0A4058)
  397 +#define MCFGPIO_PAR_QSPI (0xFC0A405A)
  398 +#define MCFGPIO_PAR_TIMER (0xFC0A405C)
  399 +#define MCFGPIO_PAR_LCDDATA (0xFC0A405D)
  400 +#define MCFGPIO_PAR_LCDCTL (0xFC0A405E)
  401 +#define MCFGPIO_PAR_IRQ (0xFC0A4060)
  402 +#define MCFGPIO_MSCR_FLEXBUS (0xFC0A4064)
  403 +#define MCFGPIO_MSCR_SDRAM (0xFC0A4065)
  404 +#define MCFGPIO_DSCR_I2C (0xFC0A4068)
  405 +#define MCFGPIO_DSCR_PWM (0xFC0A4069)
  406 +#define MCFGPIO_DSCR_FEC (0xFC0A406A)
  407 +#define MCFGPIO_DSCR_UART (0xFC0A406B)
  408 +#define MCFGPIO_DSCR_QSPI (0xFC0A406C)
  409 +#define MCFGPIO_DSCR_TIMER (0xFC0A406D)
  410 +#define MCFGPIO_DSCR_SSI (0xFC0A406E)
  411 +#define MCFGPIO_DSCR_LCD (0xFC0A406F)
  412 +#define MCFGPIO_DSCR_DEBUG (0xFC0A4070)
  413 +#define MCFGPIO_DSCR_CLKRST (0xFC0A4071)
  414 +#define MCFGPIO_DSCR_IRQ (0xFC0A4072)
  415 +
  416 +/* Bit definitions and macros for MCF_GPIO_PODR_FECH */
  417 +#define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01)
  418 +#define MCF_GPIO_PODR_FECH_PODR_FECH1 (0x02)
  419 +#define MCF_GPIO_PODR_FECH_PODR_FECH2 (0x04)
  420 +#define MCF_GPIO_PODR_FECH_PODR_FECH3 (0x08)
  421 +#define MCF_GPIO_PODR_FECH_PODR_FECH4 (0x10)
  422 +#define MCF_GPIO_PODR_FECH_PODR_FECH5 (0x20)
  423 +#define MCF_GPIO_PODR_FECH_PODR_FECH6 (0x40)
  424 +#define MCF_GPIO_PODR_FECH_PODR_FECH7 (0x80)
  425 +
  426 +/* Bit definitions and macros for MCF_GPIO_PODR_FECL */
  427 +#define MCF_GPIO_PODR_FECL_PODR_FECL0 (0x01)
  428 +#define MCF_GPIO_PODR_FECL_PODR_FECL1 (0x02)
  429 +#define MCF_GPIO_PODR_FECL_PODR_FECL2 (0x04)
  430 +#define MCF_GPIO_PODR_FECL_PODR_FECL3 (0x08)
  431 +#define MCF_GPIO_PODR_FECL_PODR_FECL4 (0x10)
  432 +#define MCF_GPIO_PODR_FECL_PODR_FECL5 (0x20)
  433 +#define MCF_GPIO_PODR_FECL_PODR_FECL6 (0x40)
  434 +#define MCF_GPIO_PODR_FECL_PODR_FECL7 (0x80)
  435 +
  436 +/* Bit definitions and macros for MCF_GPIO_PODR_SSI */
  437 +#define MCF_GPIO_PODR_SSI_PODR_SSI0 (0x01)
  438 +#define MCF_GPIO_PODR_SSI_PODR_SSI1 (0x02)
  439 +#define MCF_GPIO_PODR_SSI_PODR_SSI2 (0x04)
  440 +#define MCF_GPIO_PODR_SSI_PODR_SSI3 (0x08)
  441 +#define MCF_GPIO_PODR_SSI_PODR_SSI4 (0x10)
  442 +
  443 +/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */
  444 +#define MCF_GPIO_PODR_BUSCTL_POSDR_BUSCTL0 (0x01)
  445 +#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02)
  446 +#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04)
  447 +#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08)
  448 +
  449 +/* Bit definitions and macros for MCF_GPIO_PODR_BE */
  450 +#define MCF_GPIO_PODR_BE_PODR_BE0 (0x01)
  451 +#define MCF_GPIO_PODR_BE_PODR_BE1 (0x02)
  452 +#define MCF_GPIO_PODR_BE_PODR_BE2 (0x04)
  453 +#define MCF_GPIO_PODR_BE_PODR_BE3 (0x08)
  454 +
  455 +/* Bit definitions and macros for MCF_GPIO_PODR_CS */
  456 +#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02)
  457 +#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04)
  458 +#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08)
  459 +#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10)
  460 +#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20)
  461 +
  462 +/* Bit definitions and macros for MCF_GPIO_PODR_PWM */
  463 +#define MCF_GPIO_PODR_PWM_PODR_PWM2 (0x04)
  464 +#define MCF_GPIO_PODR_PWM_PODR_PWM3 (0x08)
  465 +#define MCF_GPIO_PODR_PWM_PODR_PWM4 (0x10)
  466 +#define MCF_GPIO_PODR_PWM_PODR_PWM5 (0x20)
  467 +
  468 +/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
  469 +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01)
  470 +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02)
  471 +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04)
  472 +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08)
  473 +
  474 +/* Bit definitions and macros for MCF_GPIO_PODR_UART */
  475 +#define MCF_GPIO_PODR_UART_PODR_UART0 (0x01)
  476 +#define MCF_GPIO_PODR_UART_PODR_UART1 (0x02)
  477 +#define MCF_GPIO_PODR_UART_PODR_UART2 (0x04)
  478 +#define MCF_GPIO_PODR_UART_PODR_UART3 (0x08)
  479 +#define MCF_GPIO_PODR_UART_PODR_UART4 (0x10)
  480 +#define MCF_GPIO_PODR_UART_PODR_UART5 (0x20)
  481 +#define MCF_GPIO_PODR_UART_PODR_UART6 (0x40)
  482 +#define MCF_GPIO_PODR_UART_PODR_UART7 (0x80)
  483 +
  484 +/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */
  485 +#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01)
  486 +#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02)
  487 +#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04)
  488 +#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08)
  489 +#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10)
  490 +#define MCF_GPIO_PODR_QSPI_PODR_QSPI5 (0x20)
  491 +
  492 +/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */
  493 +#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01)
  494 +#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02)
  495 +#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04)
  496 +#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08)
  497 +
  498 +/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */
  499 +#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0 (0x01)
  500 +#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1 (0x02)
  501 +
  502 +/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */
  503 +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0 (0x01)
  504 +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1 (0x02)
  505 +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2 (0x04)
  506 +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3 (0x08)
  507 +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4 (0x10)
  508 +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5 (0x20)
  509 +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6 (0x40)
  510 +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7 (0x80)
  511 +
  512 +/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */
  513 +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0 (0x01)
  514 +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1 (0x02)
  515 +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2 (0x04)
  516 +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3 (0x08)
  517 +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4 (0x10)
  518 +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5 (0x20)
  519 +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6 (0x40)
  520 +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7 (0x80)
  521 +
  522 +/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */
  523 +#define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0 (0x01)
  524 +
  525 +/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */
  526 +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0 (0x01)
  527 +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1 (0x02)
  528 +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2 (0x04)
  529 +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3 (0x08)
  530 +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4 (0x10)
  531 +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5 (0x20)
  532 +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6 (0x40)
  533 +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7 (0x80)
  534 +
  535 +/* Bit definitions and macros for MCF_GPIO_PDDR_FECH */
  536 +#define MCF_GPIO_PDDR_FECH_PDDR_FECH0 (0x01)
  537 +#define MCF_GPIO_PDDR_FECH_PDDR_FECH1 (0x02)
  538 +#define MCF_GPIO_PDDR_FECH_PDDR_FECH2 (0x04)
  539 +#define MCF_GPIO_PDDR_FECH_PDDR_FECH3 (0x08)
  540 +#define MCF_GPIO_PDDR_FECH_PDDR_FECH4 (0x10)
  541 +#define MCF_GPIO_PDDR_FECH_PDDR_FECH5 (0x20)
  542 +#define MCF_GPIO_PDDR_FECH_PDDR_FECH6 (0x40)
  543 +#define MCF_GPIO_PDDR_FECH_PDDR_FECH7 (0x80)
  544 +
  545 +/* Bit definitions and macros for MCF_GPIO_PDDR_FECL */
  546 +#define MCF_GPIO_PDDR_FECL_PDDR_FECL0 (0x01)
  547 +#define MCF_GPIO_PDDR_FECL_PDDR_FECL1 (0x02)
  548 +#define MCF_GPIO_PDDR_FECL_PDDR_FECL2 (0x04)
  549 +#define MCF_GPIO_PDDR_FECL_PDDR_FECL3 (0x08)
  550 +#define MCF_GPIO_PDDR_FECL_PDDR_FECL4 (0x10)
  551 +#define MCF_GPIO_PDDR_FECL_PDDR_FECL5 (0x20)
  552 +#define MCF_GPIO_PDDR_FECL_PDDR_FECL6 (0x40)
  553 +#define MCF_GPIO_PDDR_FECL_PDDR_FECL7 (0x80)
  554 +
  555 +/* Bit definitions and macros for MCF_GPIO_PDDR_SSI */
  556 +#define MCF_GPIO_PDDR_SSI_PDDR_SSI0 (0x01)
  557 +#define MCF_GPIO_PDDR_SSI_PDDR_SSI1 (0x02)
  558 +#define MCF_GPIO_PDDR_SSI_PDDR_SSI2 (0x04)
  559 +#define MCF_GPIO_PDDR_SSI_PDDR_SSI3 (0x08)
  560 +#define MCF_GPIO_PDDR_SSI_PDDR_SSI4 (0x10)
  561 +
  562 +/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */
  563 +#define MCF_GPIO_PDDR_BUSCTL_POSDR_BUSCTL0 (0x01)
  564 +#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02)
  565 +#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04)
  566 +#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08)
  567 +
  568 +/* Bit definitions and macros for MCF_GPIO_PDDR_BE */
  569 +#define MCF_GPIO_PDDR_BE_PDDR_BE0 (0x01)
  570 +#define MCF_GPIO_PDDR_BE_PDDR_BE1 (0x02)
  571 +#define MCF_GPIO_PDDR_BE_PDDR_BE2 (0x04)
  572 +#define MCF_GPIO_PDDR_BE_PDDR_BE3 (0x08)
  573 +
  574 +/* Bit definitions and macros for MCF_GPIO_PDDR_CS */
  575 +#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02)
  576 +#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04)
  577 +#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08)
  578 +#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10)
  579 +#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20)
  580 +
  581 +/* Bit definitions and macros for MCF_GPIO_PDDR_PWM */
  582 +#define MCF_GPIO_PDDR_PWM_PDDR_PWM2 (0x04)
  583 +#define MCF_GPIO_PDDR_PWM_PDDR_PWM3 (0x08)
  584 +#define MCF_GPIO_PDDR_PWM_PDDR_PWM4 (0x10)
  585 +#define MCF_GPIO_PDDR_PWM_PDDR_PWM5 (0x20)
  586 +
  587 +/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
  588 +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01)
  589 +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02)
  590 +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04)
  591 +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08)
  592 +
  593 +/* Bit definitions and macros for MCF_GPIO_PDDR_UART */
  594 +#define MCF_GPIO_PDDR_UART_PDDR_UART0 (0x01)
  595 +#define MCF_GPIO_PDDR_UART_PDDR_UART1 (0x02)
  596 +#define MCF_GPIO_PDDR_UART_PDDR_UART2 (0x04)
  597 +#define MCF_GPIO_PDDR_UART_PDDR_UART3 (0x08)
  598 +#define MCF_GPIO_PDDR_UART_PDDR_UART4 (0x10)
  599 +#define MCF_GPIO_PDDR_UART_PDDR_UART5 (0x20)
  600 +#define MCF_GPIO_PDDR_UART_PDDR_UART6 (0x40)
  601 +#define MCF_GPIO_PDDR_UART_PDDR_UART7 (0x80)
  602 +
  603 +/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */
  604 +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01)
  605 +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02)
  606 +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04)
  607 +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08)
  608 +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10)
  609 +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5 (0x20)
  610 +
  611 +/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */
  612 +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01)
  613 +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02)
  614 +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04)
  615 +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08)
  616 +
  617 +/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */
  618 +#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0 (0x01)
  619 +#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1 (0x02)
  620 +
  621 +/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */
  622 +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0 (0x01)
  623 +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1 (0x02)
  624 +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2 (0x04)
  625 +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3 (0x08)
  626 +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4 (0x10)
  627 +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5 (0x20)
  628 +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6 (0x40)
  629 +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7 (0x80)
  630 +
  631 +/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */
  632 +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0 (0x01)
  633 +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1 (0x02)
  634 +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2 (0x04)
  635 +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3 (0x08)
  636 +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4 (0x10)
  637 +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5 (0x20)
  638 +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6 (0x40)
  639 +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7 (0x80)
  640 +
  641 +/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */
  642 +#define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0 (0x01)
  643 +
  644 +/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */
  645 +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0 (0x01)
  646 +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1 (0x02)
  647 +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2 (0x04)
  648 +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3 (0x08)
  649 +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4 (0x10)
  650 +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5 (0x20)
  651 +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6 (0x40)
  652 +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7 (0x80)
  653 +
  654 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */
  655 +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0 (0x01)
  656 +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1 (0x02)
  657 +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2 (0x04)
  658 +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3 (0x08)
  659 +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4 (0x10)
  660 +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5 (0x20)
  661 +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6 (0x40)
  662 +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7 (0x80)
  663 +
  664 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */
  665 +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0 (0x01)
  666 +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1 (0x02)
  667 +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2 (0x04)
  668 +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3 (0x08)
  669 +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4 (0x10)
  670 +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5 (0x20)
  671 +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6 (0x40)
  672 +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7 (0x80)
  673 +
  674 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */
  675 +#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0 (0x01)
  676 +#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1 (0x02)
  677 +#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2 (0x04)
  678 +#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3 (0x08)
  679 +#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4 (0x10)
  680 +
  681 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */
  682 +#define MCF_GPIO_PPDSDR_BUSCTL_POSDR_BUSCTL0 (0x01)
  683 +#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02)
  684 +#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04)
  685 +#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08)
  686 +
  687 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */
  688 +#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0 (0x01)
  689 +#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1 (0x02)
  690 +#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2 (0x04)
  691 +#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3 (0x08)
  692 +
  693 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */
  694 +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02)
  695 +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04)
  696 +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08)
  697 +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10)
  698 +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20)
  699 +
  700 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */
  701 +#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2 (0x04)
  702 +#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3 (0x08)
  703 +#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4 (0x10)
  704 +#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5 (0x20)
  705 +
  706 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
  707 +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01)
  708 +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02)
  709 +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04)
  710 +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08)
  711 +
  712 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */
  713 +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0 (0x01)
  714 +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1 (0x02)
  715 +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2 (0x04)
  716 +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3 (0x08)
  717 +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4 (0x10)
  718 +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5 (0x20)
  719 +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6 (0x40)
  720 +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7 (0x80)
  721 +
  722 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */
  723 +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01)
  724 +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02)
  725 +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04)
  726 +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08)
  727 +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10)
  728 +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5 (0x20)
  729 +
  730 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */
  731 +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01)
  732 +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02)
  733 +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04)
  734 +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08)
  735 +
  736 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */
  737 +#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0 (0x01)
  738 +#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1 (0x02)
  739 +
  740 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */
  741 +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0 (0x01)
  742 +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1 (0x02)
  743 +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2 (0x04)
  744 +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3 (0x08)
  745 +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4 (0x10)
  746 +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5 (0x20)
  747 +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6 (0x40)
  748 +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7 (0x80)
  749 +
  750 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */
  751 +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0 (0x01)
  752 +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1 (0x02)
  753 +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2 (0x04)
  754 +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3 (0x08)
  755 +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4 (0x10)
  756 +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5 (0x20)
  757 +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6 (0x40)
  758 +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7 (0x80)
  759 +
  760 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */
  761 +#define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0 (0x01)
  762 +
  763 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */
  764 +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0 (0x01)
  765 +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1 (0x02)
  766 +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2 (0x04)
  767 +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3 (0x08)
  768 +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4 (0x10)
  769 +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5 (0x20)
  770 +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6 (0x40)
  771 +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7 (0x80)
  772 +
  773 +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */
  774 +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0 (0x01)
  775 +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1 (0x02)
  776 +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2 (0x04)
  777 +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3 (0x08)
  778 +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4 (0x10)
  779 +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5 (0x20)
  780 +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6 (0x40)
  781 +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7 (0x80)
  782 +
  783 +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */
  784 +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0 (0x01)
  785 +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1 (0x02)
  786 +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2 (0x04)
  787 +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3 (0x08)
  788 +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4 (0x10)
  789 +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5 (0x20)
  790 +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6 (0x40)
  791 +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7 (0x80)
  792 +
  793 +/* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */
  794 +#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0 (0x01)
  795 +#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1 (0x02)
  796 +#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2 (0x04)
  797 +#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3 (0x08)
  798 +#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4 (0x10)
  799 +
  800 +/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */
  801 +#define MCF_GPIO_PCLRR_BUSCTL_POSDR_BUSCTL0 (0x01)
  802 +#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02)
  803 +#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04)
  804 +#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08)
  805 +
  806 +/* Bit definitions and macros for MCF_GPIO_PCLRR_BE */
  807 +#define MCF_GPIO_PCLRR_BE_PCLRR_BE0 (0x01)
  808 +#define MCF_GPIO_PCLRR_BE_PCLRR_BE1 (0x02)
  809 +#define MCF_GPIO_PCLRR_BE_PCLRR_BE2 (0x04)
  810 +#define MCF_GPIO_PCLRR_BE_PCLRR_BE3 (0x08)
  811 +
  812 +/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */
  813 +#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02)
  814 +#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04)
  815 +#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08)
  816 +#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10)
  817 +#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20)
  818 +
  819 +/* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */
  820 +#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2 (0x04)
  821 +#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3 (0x08)
  822 +#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4 (0x10)
  823 +#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5 (0x20)
  824 +
  825 +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
  826 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01)
  827 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02)
  828 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04)
  829 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08)
  830 +
  831 +/* Bit definitions and macros for MCF_GPIO_PCLRR_UART */
  832 +#define MCF_GPIO_PCLRR_UART_PCLRR_UART0 (0x01)
  833 +#define MCF_GPIO_PCLRR_UART_PCLRR_UART1 (0x02)
  834 +#define MCF_GPIO_PCLRR_UART_PCLRR_UART2 (0x04)
  835 +#define MCF_GPIO_PCLRR_UART_PCLRR_UART3 (0x08)
  836 +#define MCF_GPIO_PCLRR_UART_PCLRR_UART4 (0x10)
  837 +#define MCF_GPIO_PCLRR_UART_PCLRR_UART5 (0x20)
  838 +#define MCF_GPIO_PCLRR_UART_PCLRR_UART6 (0x40)
  839 +#define MCF_GPIO_PCLRR_UART_PCLRR_UART7 (0x80)
  840 +
  841 +/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */
  842 +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01)
  843 +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02)
  844 +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04)
  845 +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08)
  846 +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10)
  847 +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5 (0x20)
  848 +
  849 +/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */
  850 +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01)
  851 +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02)
  852 +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04)
  853 +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08)
  854 +
  855 +/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */
  856 +#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0 (0x01)
  857 +#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1 (0x02)
  858 +
  859 +/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */
  860 +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0 (0x01)
  861 +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1 (0x02)
  862 +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2 (0x04)
  863 +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3 (0x08)
  864 +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4 (0x10)
  865 +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5 (0x20)
  866 +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6 (0x40)
  867 +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7 (0x80)
  868 +
  869 +/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */
  870 +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0 (0x01)
  871 +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1 (0x02)
  872 +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2 (0x04)
  873 +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3 (0x08)
  874 +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4 (0x10)
  875 +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5 (0x20)
  876 +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6 (0x40)
  877 +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7 (0x80)
  878 +
  879 +/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */
  880 +#define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01)
  881 +
  882 +/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */
  883 +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0 (0x01)
  884 +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1 (0x02)
  885 +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2 (0x04)
  886 +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3 (0x08)
  887 +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4 (0x10)
  888 +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5 (0x20)
  889 +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6 (0x40)
  890 +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7 (0x80)
  891 +
  892 +/* Bit definitions and macros for MCF_GPIO_PAR_FEC */
  893 +#define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x) (((x)&0x03)<<0)
  894 +#define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x) (((x)&0x03)<<2)
  895 +#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO (0x00)
  896 +#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1 (0x04)
  897 +#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC (0x0C)
  898 +#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO (0x00)
  899 +#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART (0x01)
  900 +#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC (0x03)
  901 +
  902 +/* Bit definitions and macros for MCF_GPIO_PAR_PWM */
  903 +#define MCF_GPIO_PAR_PWM_PAR_PWM1(x) (((x)&0x03)<<0)
  904 +#define MCF_GPIO_PAR_PWM_PAR_PWM3(x) (((x)&0x03)<<2)
  905 +#define MCF_GPIO_PAR_PWM_PAR_PWM5 (0x10)
  906 +#define MCF_GPIO_PAR_PWM_PAR_PWM7 (0x20)
  907 +
  908 +/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */
  909 +#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x03)<<3)
  910 +#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x20)
  911 +#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x40)
  912 +#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x80)
  913 +#define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO (0x00)
  914 +#define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE (0x80)
  915 +#define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO (0x00)
  916 +#define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA (0x40)
  917 +#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO (0x00)
  918 +#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB (0x20)
  919 +#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x00)
  920 +#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0 (0x10)
  921 +#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x18)
  922 +
  923 +/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */
  924 +#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0)
  925 +#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2)
  926 +#define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x) (((x)&0x03)<<4)
  927 +#define MCF_GPIO_PAR_FECI2C_PAR_MDC(x) (((x)&0x03)<<6)
  928 +#define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO (0x00)
  929 +#define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2 (0x40)
  930 +#define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL (0x80)
  931 +#define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC (0xC0)
  932 +#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO (0x00)
  933 +#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2 (0x10)
  934 +#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA (0x20)
  935 +#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO (0x30)
  936 +#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00)
  937 +#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
  938 +#define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL (0x0C)
  939 +#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00)
  940 +#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
  941 +#define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA (0x03)
  942 +
  943 +/* Bit definitions and macros for MCF_GPIO_PAR_BE */
  944 +#define MCF_GPIO_PAR_BE_PAR_BE0 (0x01)
  945 +#define MCF_GPIO_PAR_BE_PAR_BE1 (0x02)
  946 +#define MCF_GPIO_PAR_BE_PAR_BE2 (0x04)
  947 +#define MCF_GPIO_PAR_BE_PAR_BE3 (0x08)
  948 +
  949 +/* Bit definitions and macros for MCF_GPIO_PAR_CS */
  950 +#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02)
  951 +#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04)
  952 +#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08)
  953 +#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10)
  954 +#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20)
  955 +#define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO (0x00)
  956 +#define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1 (0x01)
  957 +#define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1 (0x03)
  958 +
  959 +/* Bit definitions and macros for MCF_GPIO_PAR_SSI */
  960 +#define MCF_GPIO_PAR_SSI_PAR_MCLK (0x0080)
  961 +#define MCF_GPIO_PAR_SSI_PAR_TXD(x) (((x)&0x0003)<<8)
  962 +#define MCF_GPIO_PAR_SSI_PAR_RXD(x) (((x)&0x0003)<<10)
  963 +#define MCF_GPIO_PAR_SSI_PAR_FS(x) (((x)&0x0003)<<12)
  964 +#define MCF_GPIO_PAR_SSI_PAR_BCLK(x) (((x)&0x0003)<<14)
  965 +
  966 +/* Bit definitions and macros for MCF_GPIO_PAR_UART */
  967 +#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0001)
  968 +#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0002)
  969 +#define MCF_GPIO_PAR_UART_PAR_URTS0 (0x0004)
  970 +#define MCF_GPIO_PAR_UART_PAR_UCTS0 (0x0008)
  971 +#define MCF_GPIO_PAR_UART_PAR_UTXD1(x) (((x)&0x0003)<<4)
  972 +#define MCF_GPIO_PAR_UART_PAR_URXD1(x) (((x)&0x0003)<<6)
  973 +#define MCF_GPIO_PAR_UART_PAR_URTS1(x) (((x)&0x0003)<<8)
  974 +#define MCF_GPIO_PAR_UART_PAR_UCTS1(x) (((x)&0x0003)<<10)
  975 +#define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO (0x0000)
  976 +#define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK (0x0800)
  977 +#define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7 (0x0400)
  978 +#define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1 (0x0C00)
  979 +#define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO (0x0000)
  980 +#define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS (0x0200)
  981 +#define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6 (0x0100)
  982 +#define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1 (0x0300)
  983 +#define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO (0x0000)
  984 +#define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD (0x0080)
  985 +#define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5 (0x0040)
  986 +#define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1 (0x00C0)
  987 +#define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO (0x0000)
  988 +#define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD (0x0020)
  989 +#define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4 (0x0010)
  990 +#define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1 (0x0030)
  991 +
  992 +/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */
  993 +#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x0003)<<4)
  994 +#define MCF_GPIO_PAR_QSPI_PAR_DOUT(x) (((x)&0x0003)<<6)
  995 +#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x0003)<<8)
  996 +#define MCF_GPIO_PAR_QSPI_PAR_PCS0(x) (((x)&0x0003)<<10)
  997 +#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x0003)<<12)
  998 +#define MCF_GPIO_PAR_QSPI_PAR_PCS2(x) (((x)&0x0003)<<14)
  999 +
  1000 +/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
  1001 +#define MCF_GPIO_PAR_TIMER_PAR_TIN0(x) (((x)&0x03)<<0)
  1002 +#define MCF_GPIO_PAR_TIMER_PAR_TIN1(x) (((x)&0x03)<<2)
  1003 +#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<4)
  1004 +#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<6)
  1005 +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO (0x00)
  1006 +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3 (0x80)
  1007 +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2 (0x40)
  1008 +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3 (0xC0)
  1009 +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO (0x00)
  1010 +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2 (0x20)
  1011 +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2 (0x10)
  1012 +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2 (0x30)
  1013 +#define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO (0x00)
  1014 +#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1 (0x08)
  1015 +#define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1 (0x04)
  1016 +#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1 (0x0C)
  1017 +#define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO (0x00)
  1018 +#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0 (0x02)
  1019 +#define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0 (0x01)
  1020 +#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0 (0x03)
  1021 +
  1022 +/* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */
  1023 +#define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x) (((x)&0x03)<<0)
  1024 +#define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x) (((x)&0x03)<<2)
  1025 +#define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x) (((x)&0x03)<<4)
  1026 +#define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x) (((x)&0x03)<<6)
  1027 +
  1028 +/* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */
  1029 +#define MCF_GPIO_PAR_LCDCTL_PAR_CLS (0x0001)
  1030 +#define MCF_GPIO_PAR_LCDCTL_PAR_PS (0x0002)
  1031 +#define MCF_GPIO_PAR_LCDCTL_PAR_REV (0x0004)
  1032 +#define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR (0x0008)
  1033 +#define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST (0x0010)
  1034 +#define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK (0x0020)
  1035 +#define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC (0x0040)
  1036 +#define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC (0x0080)
  1037 +#define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE (0x0100)
  1038 +
  1039 +/* Bit definitions and macros for MCF_GPIO_PAR_IRQ */
  1040 +#define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x) (((x)&0x0003)<<4)
  1041 +#define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x) (((x)&0x0003)<<6)
  1042 +#define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x) (((x)&0x0003)<<8)
  1043 +#define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x) (((x)&0x0003)<<10)
  1044 +#define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x) (((x)&0x0003)<<12)
  1045 +
  1046 +/* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */
  1047 +#define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x) (((x)&0x03)<<0)
  1048 +#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x) (((x)&0x03)<<2)
  1049 +#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x) (((x)&0x03)<<4)
  1050 +
  1051 +/* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */
  1052 +#define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x) (((x)&0x03)<<0)
  1053 +#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x) (((x)&0x03)<<2)
  1054 +#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x) (((x)&0x03)<<4)
  1055 +
  1056 +/* Bit definitions and macros for MCF_GPIO_DSCR_I2C */
  1057 +#define MCF_GPIO_DSCR_I2C_I2C_DSE(x) (((x)&0x03)<<0)
  1058 +
  1059 +/* Bit definitions and macros for MCF_GPIO_DSCR_PWM */
  1060 +#define MCF_GPIO_DSCR_PWM_PWM_DSE(x) (((x)&0x03)<<0)
  1061 +
  1062 +/* Bit definitions and macros for MCF_GPIO_DSCR_FEC */
  1063 +#define MCF_GPIO_DSCR_FEC_FEC_DSE(x) (((x)&0x03)<<0)
  1064 +
  1065 +/* Bit definitions and macros for MCF_GPIO_DSCR_UART */
  1066 +#define MCF_GPIO_DSCR_UART_UART0_DSE(x) (((x)&0x03)<<0)
  1067 +#define MCF_GPIO_DSCR_UART_UART1_DSE(x) (((x)&0x03)<<2)
  1068 +
  1069 +/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */
  1070 +#define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x) (((x)&0x03)<<0)
  1071 +
  1072 +/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */
  1073 +#define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x) (((x)&0x03)<<0)
  1074 +
  1075 +/* Bit definitions and macros for MCF_GPIO_DSCR_SSI */
  1076 +#define MCF_GPIO_DSCR_SSI_SSI_DSE(x) (((x)&0x03)<<0)
  1077 +
  1078 +/* Bit definitions and macros for MCF_GPIO_DSCR_LCD */
  1079 +#define MCF_GPIO_DSCR_LCD_LCD_DSE(x) (((x)&0x03)<<0)
  1080 +
  1081 +/* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */
  1082 +#define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x) (((x)&0x03)<<0)
  1083 +
  1084 +/* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */
  1085 +#define MCF_GPIO_DSCR_CLKRST_CLKRST_DSE(x) (((x)&0x03)<<0)
  1086 +
  1087 +/* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */
  1088 +#define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0)
  1089 +
  1090 +/*
  1091 + * Generic GPIO support
  1092 + */
  1093 +#define MCFGPIO_PODR MCFGPIO_PODR_FECH
  1094 +#define MCFGPIO_PDDR MCFGPIO_PDDR_FECH
  1095 +#define MCFGPIO_PPDR MCFGPIO_PPDSDR_FECH
  1096 +#define MCFGPIO_SETR MCFGPIO_PPDSDR_FECH
  1097 +#define MCFGPIO_CLRR MCFGPIO_PCLRR_FECH
  1098 +
  1099 +#define MCFGPIO_PIN_MAX 136
  1100 +#define MCFGPIO_IRQ_MAX 8
  1101 +#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
  1102 +
  1103 +/*********************************************************************
  1104 + *
  1105 + * Phase Locked Loop (PLL)
  1106 + *
  1107 + *********************************************************************/
  1108 +
  1109 +/* Register read/write macros */
  1110 +#define MCF_PLL_PODR 0xFC0C0000
  1111 +#define MCF_PLL_PLLCR 0xFC0C0004
  1112 +#define MCF_PLL_PMDR 0xFC0C0008
  1113 +#define MCF_PLL_PFDR 0xFC0C000C
  1114 +
  1115 +/* Bit definitions and macros for MCF_PLL_PODR */
  1116 +#define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0)
  1117 +#define MCF_PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4)
  1118 +
  1119 +/* Bit definitions and macros for MCF_PLL_PLLCR */
  1120 +#define MCF_PLL_PLLCR_DITHDEV(x) (((x)&0x07)<<0)
  1121 +#define MCF_PLL_PLLCR_DITHEN (0x80)
  1122 +
  1123 +/* Bit definitions and macros for MCF_PLL_PMDR */
  1124 +#define MCF_PLL_PMDR_MODDIV(x) (((x)&0xFF)<<0)
  1125 +
  1126 +/* Bit definitions and macros for MCF_PLL_PFDR */
  1127 +#define MCF_PLL_PFDR_MFD(x) (((x)&0xFF)<<0)
  1128 +
  1129 +/*********************************************************************
  1130 + *
  1131 + * System Control Module Registers (SCM)
  1132 + *
  1133 + *********************************************************************/
  1134 +
  1135 +/* Register read/write macros */
  1136 +#define MCF_SCM_MPR 0xFC000000
  1137 +#define MCF_SCM_PACRA 0xFC000020
  1138 +#define MCF_SCM_PACRB 0xFC000024
  1139 +#define MCF_SCM_PACRC 0xFC000028
  1140 +#define MCF_SCM_PACRD 0xFC00002C
  1141 +#define MCF_SCM_PACRE 0xFC000040
  1142 +#define MCF_SCM_PACRF 0xFC000044
  1143 +
  1144 +#define MCF_SCM_BCR 0xFC040024
  1145 +
  1146 +/*********************************************************************
  1147 + *
  1148 + * SDRAM Controller (SDRAMC)
  1149 + *
  1150 + *********************************************************************/
  1151 +
  1152 +/* Register read/write macros */
  1153 +#define MCF_SDRAMC_SDMR 0xFC0B8000
  1154 +#define MCF_SDRAMC_SDCR 0xFC0B8004
  1155 +#define MCF_SDRAMC_SDCFG1 0xFC0B8008
  1156 +#define MCF_SDRAMC_SDCFG2 0xFC0B800C
  1157 +#define MCF_SDRAMC_LIMP_FIX 0xFC0B8080
  1158 +#define MCF_SDRAMC_SDDS 0xFC0B8100
  1159 +#define MCF_SDRAMC_SDCS0 0xFC0B8110
  1160 +#define MCF_SDRAMC_SDCS1 0xFC0B8114
  1161 +#define MCF_SDRAMC_SDCS2 0xFC0B8118
  1162 +#define MCF_SDRAMC_SDCS3 0xFC0B811C
  1163 +
  1164 +/* Bit definitions and macros for MCF_SDRAMC_SDMR */
  1165 +#define MCF_SDRAMC_SDMR_CMD (0x00010000)
  1166 +#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
  1167 +#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30)
  1168 +#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000)
  1169 +#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
  1170 +
  1171 +/* Bit definitions and macros for MCF_SDRAMC_SDCR */
  1172 +#define MCF_SDRAMC_SDCR_IPALL (0x00000002)
  1173 +#define MCF_SDRAMC_SDCR_IREF (0x00000004)
  1174 +#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8)
  1175 +#define MCF_SDRAMC_SDCR_PS(x) (((x)&0x00000003)<<12)
  1176 +#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
  1177 +#define MCF_SDRAMC_SDCR_OE_RULE (0x00400000)
  1178 +#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
  1179 +#define MCF_SDRAMC_SDCR_REF (0x10000000)
  1180 +#define MCF_SDRAMC_SDCR_DDR (0x20000000)
  1181 +#define MCF_SDRAMC_SDCR_CKE (0x40000000)
  1182 +#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
  1183 +#define MCF_SDRAMC_SDCR_PS_16 (0x00002000)
  1184 +#define MCF_SDRAMC_SDCR_PS_32 (0x00000000)
  1185 +
  1186 +/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
  1187 +#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
  1188 +#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
  1189 +#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
  1190 +#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
  1191 +#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
  1192 +#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
  1193 +#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
  1194 +
  1195 +/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
  1196 +#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
  1197 +#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
  1198 +#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
  1199 +#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
  1200 +
  1201 +/* Device Errata - LIMP mode work around */
  1202 +#define MCF_SDRAMC_REFRESH (0x40000000)
  1203 +
  1204 +/* Bit definitions and macros for MCF_SDRAMC_SDDS */
  1205 +#define MCF_SDRAMC_SDDS_SB_D(x) (((x)&0x00000003)<<0)
  1206 +#define MCF_SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2)
  1207 +#define MCF_SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4)
  1208 +#define MCF_SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6)
  1209 +#define MCF_SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8)
  1210 +
  1211 +/* Bit definitions and macros for MCF_SDRAMC_SDCS */
  1212 +#define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)<<0)
  1213 +#define MCF_SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20)
  1214 +#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
  1215 +#define MCF_SDRAMC_SDCS_CSSZ_DIABLE (0x00000000)
  1216 +#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
  1217 +#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
  1218 +#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
  1219 +#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
  1220 +#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
  1221 +#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
  1222 +#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
  1223 +#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
  1224 +#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
  1225 +#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
  1226 +#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
  1227 +#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
  1228 +#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
  1229 +
  1230 +/*
  1231 + * Edge Port Module (EPORT)
  1232 + */
  1233 +#define MCFEPORT_EPPAR (0xFC094000)
  1234 +#define MCFEPORT_EPDDR (0xFC094002)
  1235 +#define MCFEPORT_EPIER (0xFC094003)
  1236 +#define MCFEPORT_EPDR (0xFC094004)
  1237 +#define MCFEPORT_EPPDR (0xFC094005)
  1238 +#define MCFEPORT_EPFR (0xFC094006)
  1239 +
  1240 +/********************************************************************/
  1241 +#endif /* m53xxsim_h */
arch/m68k/include/asm/m54xxacr.h
Diff comments   View file @ 977b58e
... ... @@ -96,8 +96,13 @@
96 96 */
97 97 #define ACR0_MODE (ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \
98 98 ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP)
  99 +#if defined(CONFIG_CACHE_COPYBACK)
99 100 #define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
100   - ACR_ENABLE+ACR_SUPER+ACR_SP)
  101 + ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_CP)
  102 +#else
  103 +#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
  104 + ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_WT)
  105 +#endif
101 106 #define ACR2_MODE 0
102 107 #define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
103 108 ACR_ENABLE+ACR_SUPER+ACR_SP)
arch/m68k/include/asm/mcfgpio.h
Diff comments   View file @ 977b58e
... ... @@ -104,7 +104,7 @@
104 104 #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
105 105 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
106 106 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
107   - defined(CONFIG_M532x) || defined(CONFIG_M54xx) || \
  107 + defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
108 108 defined(CONFIG_M5441x)
109 109  
110 110 /* These parts have GPIO organized by 8 bit ports */
... ... @@ -139,7 +139,7 @@
139 139  
140 140 #if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
141 141 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
142   - defined(CONFIG_M532x) || defined(CONFIG_M5441x)
  142 + defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
143 143 /*
144 144 * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
145 145 * read-modify-write to change an output and a GPIO module which has separate
... ... @@ -195,7 +195,7 @@
195 195 return MCFSIM2_GPIO1READ;
196 196 #elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
197 197 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
198   - defined(CONFIG_M532x) || defined(CONFIG_M5441x)
  198 + defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
199 199 #if !defined(CONFIG_M5441x)
200 200 if (gpio < 8)
201 201 return MCFEPORT_EPPDR;
... ... @@ -237,7 +237,7 @@
237 237 return MCFSIM2_GPIO1WRITE;
238 238 #elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
239 239 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
240   - defined(CONFIG_M532x) || defined(CONFIG_M5441x)
  240 + defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
241 241 #if !defined(CONFIG_M5441x)
242 242 if (gpio < 8)
243 243 return MCFEPORT_EPDR;
... ... @@ -279,7 +279,7 @@
279 279 return MCFSIM2_GPIO1ENABLE;
280 280 #elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
281 281 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
282   - defined(CONFIG_M532x) || defined(CONFIG_M5441x)
  282 + defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
283 283 #if !defined(CONFIG_M5441x)
284 284 if (gpio < 8)
285 285 return MCFEPORT_EPDDR;
arch/m68k/include/asm/mcfsim.h
Diff comments   View file @ 977b58e
... ... @@ -36,8 +36,8 @@
36 36 #elif defined(CONFIG_M5307)
37 37 #include <asm/m5307sim.h>
38 38 #include <asm/mcfintc.h>
39   -#elif defined(CONFIG_M532x)
40   -#include <asm/m532xsim.h>
  39 +#elif defined(CONFIG_M53xx)
  40 +#include <asm/m53xxsim.h>
41 41 #elif defined(CONFIG_M5407)
42 42 #include <asm/m5407sim.h>
43 43 #include <asm/mcfintc.h>
arch/m68k/include/asm/mcftimer.h
Diff comments   View file @ 977b58e
... ... @@ -19,7 +19,7 @@
19 19 #define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */
20 20 #define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */
21 21 #define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */
22   -#if defined(CONFIG_M532x) || defined(CONFIG_M5441x)
  22 +#if defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
23 23 #define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */
24 24 #else
25 25 #define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
arch/m68k/platform/coldfire/Makefile
Diff comments   View file @ 977b58e
... ... @@ -25,7 +25,7 @@
25 25 obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o
26 26 obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o
27 27 obj-$(CONFIG_M5307) += m5307.o timers.o intc.o reset.o
28   -obj-$(CONFIG_M532x) += m532x.o timers.o intc-simr.o reset.o
  28 +obj-$(CONFIG_M53xx) += m53xx.o timers.o intc-simr.o reset.o
29 29 obj-$(CONFIG_M5407) += m5407.o timers.o intc.o reset.o
30 30 obj-$(CONFIG_M54xx) += m54xx.o sltimers.o intc-2.o
31 31 obj-$(CONFIG_M5441x) += m5441x.o pit.o intc-simr.o reset.o
arch/m68k/platform/coldfire/m532x.c
View file @ 977b58e
1   -/***************************************************************************/
2   -
3   -/*
4   - * linux/arch/m68knommu/platform/532x/config.c
5   - *
6   - * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7   - * Copyright (C) 2000, Lineo (www.lineo.com)
8   - * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
9   - * Copyright Freescale Semiconductor, Inc 2006
10   - * Copyright (c) 2006, emlix, Sebastian Hess <shess@hessware.de>
11   - *
12   - * This program is free software; you can redistribute it and/or modify
13   - * it under the terms of the GNU General Public License as published by
14   - * the Free Software Foundation; either version 2 of the License, or
15   - * (at your option) any later version.
16   - */
17   -
18   -/***************************************************************************/
19   -
20   -#include <linux/kernel.h>
21   -#include <linux/param.h>
22   -#include <linux/init.h>
23   -#include <linux/io.h>
24   -#include <asm/machdep.h>
25   -#include <asm/coldfire.h>
26   -#include <asm/mcfsim.h>
27   -#include <asm/mcfuart.h>
28   -#include <asm/mcfdma.h>
29   -#include <asm/mcfwdebug.h>
30   -#include <asm/mcfclk.h>
31   -
32   -/***************************************************************************/
33   -
34   -DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
35   -DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
36   -DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
37   -DEFINE_CLK(0, "edma", 17, MCF_CLK);
38   -DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
39   -DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
40   -DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
41   -DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
42   -DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
43   -DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
44   -DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
45   -DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
46   -DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
47   -DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
48   -DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
49   -DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
50   -
51   -DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
52   -DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
53   -DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK);
54   -DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK);
55   -DEFINE_CLK(0, "mcfpwm.0", 36, MCF_CLK);
56   -DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK);
57   -DEFINE_CLK(0, "mcfwdt.0", 38, MCF_CLK);
58   -DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
59   -DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
60   -DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK);
61   -DEFINE_CLK(0, "mcflcd.0", 43, MCF_CLK);
62   -DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
63   -DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
64   -DEFINE_CLK(0, "sdram.0", 46, MCF_CLK);
65   -DEFINE_CLK(0, "ssi.0", 47, MCF_CLK);
66   -DEFINE_CLK(0, "pll.0", 48, MCF_CLK);
67   -
68   -DEFINE_CLK(1, "mdha.0", 32, MCF_CLK);
69   -DEFINE_CLK(1, "skha.0", 33, MCF_CLK);
70   -DEFINE_CLK(1, "rng.0", 34, MCF_CLK);
71   -
72   -struct clk *mcf_clks[] = {
73   - &__clk_0_2, /* flexbus */
74   - &__clk_0_8, /* mcfcan.0 */
75   - &__clk_0_12, /* fec.0 */
76   - &__clk_0_17, /* edma */
77   - &__clk_0_18, /* intc.0 */
78   - &__clk_0_19, /* intc.1 */
79   - &__clk_0_21, /* iack.0 */
80   - &__clk_0_22, /* mcfi2c.0 */
81   - &__clk_0_23, /* mcfqspi.0 */
82   - &__clk_0_24, /* mcfuart.0 */
83   - &__clk_0_25, /* mcfuart.1 */
84   - &__clk_0_26, /* mcfuart.2 */
85   - &__clk_0_28, /* mcftmr.0 */
86   - &__clk_0_29, /* mcftmr.1 */
87   - &__clk_0_30, /* mcftmr.2 */
88   - &__clk_0_31, /* mcftmr.3 */
89   -
90   - &__clk_0_32, /* mcfpit.0 */
91   - &__clk_0_33, /* mcfpit.1 */
92   - &__clk_0_34, /* mcfpit.2 */
93   - &__clk_0_35, /* mcfpit.3 */
94   - &__clk_0_36, /* mcfpwm.0 */
95   - &__clk_0_37, /* mcfeport.0 */
96   - &__clk_0_38, /* mcfwdt.0 */
97   - &__clk_0_40, /* sys.0 */
98   - &__clk_0_41, /* gpio.0 */
99   - &__clk_0_42, /* mcfrtc.0 */
100   - &__clk_0_43, /* mcflcd.0 */
101   - &__clk_0_44, /* mcfusb-otg.0 */
102   - &__clk_0_45, /* mcfusb-host.0 */
103   - &__clk_0_46, /* sdram.0 */
104   - &__clk_0_47, /* ssi.0 */
105   - &__clk_0_48, /* pll.0 */
106   -
107   - &__clk_1_32, /* mdha.0 */
108   - &__clk_1_33, /* skha.0 */
109   - &__clk_1_34, /* rng.0 */
110   - NULL,
111   -};
112   -
113   -static struct clk * const enable_clks[] __initconst = {
114   - &__clk_0_2, /* flexbus */
115   - &__clk_0_18, /* intc.0 */
116   - &__clk_0_19, /* intc.1 */
117   - &__clk_0_21, /* iack.0 */
118   - &__clk_0_24, /* mcfuart.0 */
119   - &__clk_0_25, /* mcfuart.1 */
120   - &__clk_0_26, /* mcfuart.2 */
121   -
122   - &__clk_0_32, /* mcfpit.0 */
123   - &__clk_0_33, /* mcfpit.1 */
124   - &__clk_0_37, /* mcfeport.0 */
125   - &__clk_0_40, /* sys.0 */
126   - &__clk_0_41, /* gpio.0 */
127   - &__clk_0_46, /* sdram.0 */
128   - &__clk_0_48, /* pll.0 */
129   -};
130   -
131   -static struct clk * const disable_clks[] __initconst = {
132   - &__clk_0_8, /* mcfcan.0 */
133   - &__clk_0_12, /* fec.0 */
134   - &__clk_0_17, /* edma */
135   - &__clk_0_22, /* mcfi2c.0 */
136   - &__clk_0_23, /* mcfqspi.0 */
137   - &__clk_0_28, /* mcftmr.0 */
138   - &__clk_0_29, /* mcftmr.1 */
139   - &__clk_0_30, /* mcftmr.2 */
140   - &__clk_0_31, /* mcftmr.3 */
141   - &__clk_0_34, /* mcfpit.2 */
142   - &__clk_0_35, /* mcfpit.3 */
143   - &__clk_0_36, /* mcfpwm.0 */
144   - &__clk_0_38, /* mcfwdt.0 */
145   - &__clk_0_42, /* mcfrtc.0 */
146   - &__clk_0_43, /* mcflcd.0 */
147   - &__clk_0_44, /* mcfusb-otg.0 */
148   - &__clk_0_45, /* mcfusb-host.0 */
149   - &__clk_0_47, /* ssi.0 */
150   - &__clk_1_32, /* mdha.0 */
151   - &__clk_1_33, /* skha.0 */
152   - &__clk_1_34, /* rng.0 */
153   -};
154   -
155   -
156   -static void __init m532x_clk_init(void)
157   -{
158   - unsigned i;
159   -
160   - /* make sure these clocks are enabled */
161   - for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
162   - __clk_init_enabled(enable_clks[i]);
163   - /* make sure these clocks are disabled */
164   - for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
165   - __clk_init_disabled(disable_clks[i]);
166   -}
167   -
168   -/***************************************************************************/
169   -
170   -#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
171   -
172   -static void __init m532x_qspi_init(void)
173   -{
174   - /* setup QSPS pins for QSPI with gpio CS control */
175   - writew(0x01f0, MCFGPIO_PAR_QSPI);
176   -}
177   -
178   -#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
179   -
180   -/***************************************************************************/
181   -
182   -static void __init m532x_uarts_init(void)
183   -{
184   - /* UART GPIO initialization */
185   - writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART);
186   -}
187   -
188   -/***************************************************************************/
189   -
190   -static void __init m532x_fec_init(void)
191   -{
192   - u8 v;
193   -
194   - /* Set multi-function pins to ethernet mode for fec0 */
195   - v = readb(MCFGPIO_PAR_FECI2C);
196   - v |= MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
197   - MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO;
198   - writeb(v, MCFGPIO_PAR_FECI2C);
199   -
200   - v = readb(MCFGPIO_PAR_FEC);
201   - v = MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC;
202   - writeb(v, MCFGPIO_PAR_FEC);
203   -}
204   -
205   -/***************************************************************************/
206   -
207   -void __init config_BSP(char *commandp, int size)
208   -{
209   -#if !defined(CONFIG_BOOTPARAM)
210   - /* Copy command line from FLASH to local buffer... */
211   - memcpy(commandp, (char *) 0x4000, 4);
212   - if(strncmp(commandp, "kcl ", 4) == 0){
213   - memcpy(commandp, (char *) 0x4004, size);
214   - commandp[size-1] = 0;
215   - } else {
216   - memset(commandp, 0, size);
217   - }
218   -#endif
219   - mach_sched_init = hw_timer_init;
220   - m532x_clk_init();
221   - m532x_uarts_init();
222   - m532x_fec_init();
223   -#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
224   - m532x_qspi_init();
225   -#endif
226   -
227   -#ifdef CONFIG_BDM_DISABLE
228   - /*
229   - * Disable the BDM clocking. This also turns off most of the rest of
230   - * the BDM device. This is good for EMC reasons. This option is not
231   - * incompatible with the memory protection option.
232   - */
233   - wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
234   -#endif
235   -}
236   -
237   -/***************************************************************************/
238   -/* Board initialization */
239   -/***************************************************************************/
240   -/*
241   - * PLL min/max specifications
242   - */
243   -#define MAX_FVCO 500000 /* KHz */
244   -#define MAX_FSYS 80000 /* KHz */
245   -#define MIN_FSYS 58333 /* KHz */
246   -#define FREF 16000 /* KHz */
247   -
248   -
249   -#define MAX_MFD 135 /* Multiplier */
250   -#define MIN_MFD 88 /* Multiplier */
251   -#define BUSDIV 6 /* Divider */
252   -
253   -/*
254   - * Low Power Divider specifications
255   - */
256   -#define MIN_LPD (1 << 0) /* Divider (not encoded) */
257   -#define MAX_LPD (1 << 15) /* Divider (not encoded) */
258   -#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
259   -
260   -#define SYS_CLK_KHZ 80000
261   -#define SYSTEM_PERIOD 12.5
262   -/*
263   - * SDRAM Timing Parameters
264   - */
265   -#define SDRAM_BL 8 /* # of beats in a burst */
266   -#define SDRAM_TWR 2 /* in clocks */
267   -#define SDRAM_CASL 2.5 /* CASL in clocks */
268   -#define SDRAM_TRCD 2 /* in clocks */
269   -#define SDRAM_TRP 2 /* in clocks */
270   -#define SDRAM_TRFC 7 /* in clocks */
271   -#define SDRAM_TREFI 7800 /* in ns */
272   -
273   -#define EXT_SRAM_ADDRESS (0xC0000000)
274   -#define FLASH_ADDRESS (0x00000000)
275   -#define SDRAM_ADDRESS (0x40000000)
276   -
277   -#define NAND_FLASH_ADDRESS (0xD0000000)
278   -
279   -int sys_clk_khz = 0;
280   -int sys_clk_mhz = 0;
281   -
282   -void wtm_init(void);
283   -void scm_init(void);
284   -void gpio_init(void);
285   -void fbcs_init(void);
286   -void sdramc_init(void);
287   -int clock_pll (int fsys, int flags);
288   -int clock_limp (int);
289   -int clock_exit_limp (void);
290   -int get_sys_clock (void);
291   -
292   -asmlinkage void __init sysinit(void)
293   -{
294   - sys_clk_khz = clock_pll(0, 0);
295   - sys_clk_mhz = sys_clk_khz/1000;
296   -
297   - wtm_init();
298   - scm_init();
299   - gpio_init();
300   - fbcs_init();
301   - sdramc_init();
302   -}
303   -
304   -void wtm_init(void)
305   -{
306   - /* Disable watchdog timer */
307   - writew(0, MCF_WTM_WCR);
308   -}
309   -
310   -#define MCF_SCM_BCR_GBW (0x00000100)
311   -#define MCF_SCM_BCR_GBR (0x00000200)
312   -
313   -void scm_init(void)
314   -{
315   - /* All masters are trusted */
316   - writel(0x77777777, MCF_SCM_MPR);
317   -
318   - /* Allow supervisor/user, read/write, and trusted/untrusted
319   - access to all slaves */
320   - writel(0, MCF_SCM_PACRA);
321   - writel(0, MCF_SCM_PACRB);
322   - writel(0, MCF_SCM_PACRC);
323   - writel(0, MCF_SCM_PACRD);
324   - writel(0, MCF_SCM_PACRE);
325   - writel(0, MCF_SCM_PACRF);
326   -
327   - /* Enable bursts */
328   - writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR);
329   -}
330   -
331   -
332   -void fbcs_init(void)
333   -{
334   - writeb(0x3E, MCFGPIO_PAR_CS);
335   -
336   - /* Latch chip select */
337   - writel(0x10080000, MCF_FBCS1_CSAR);
338   -
339   - writel(0x002A3780, MCF_FBCS1_CSCR);
340   - writel(MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
341   -
342   - /* Initialize latch to drive signals to inactive states */
343   - writew(0xffff, 0x10080000);
344   -
345   - /* External SRAM */
346   - writel(EXT_SRAM_ADDRESS, MCF_FBCS1_CSAR);
347   - writel(MCF_FBCS_CSCR_PS_16 |
348   - MCF_FBCS_CSCR_AA |
349   - MCF_FBCS_CSCR_SBM |
350   - MCF_FBCS_CSCR_WS(1),
351   - MCF_FBCS1_CSCR);
352   - writel(MCF_FBCS_CSMR_BAM_512K | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
353   -
354   - /* Boot Flash connected to FBCS0 */
355   - writel(FLASH_ADDRESS, MCF_FBCS0_CSAR);
356   - writel(MCF_FBCS_CSCR_PS_16 |
357   - MCF_FBCS_CSCR_BEM |
358   - MCF_FBCS_CSCR_AA |
359   - MCF_FBCS_CSCR_SBM |
360   - MCF_FBCS_CSCR_WS(7),
361   - MCF_FBCS0_CSCR);
362   - writel(MCF_FBCS_CSMR_BAM_32M | MCF_FBCS_CSMR_V, MCF_FBCS0_CSMR);
363   -}
364   -
365   -void sdramc_init(void)
366   -{
367   - /*
368   - * Check to see if the SDRAM has already been initialized
369   - * by a run control tool
370   - */
371   - if (!(readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)) {
372   - /* SDRAM chip select initialization */
373   -
374   - /* Initialize SDRAM chip select */
375   - writel(MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) |
376   - MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE),
377   - MCF_SDRAMC_SDCS0);
378   -
379   - /*
380   - * Basic configuration and initialization
381   - */
382   - writel(MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5)) |
383   - MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1) |
384   - MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL * 2) + 2)) |
385   - MCF_SDRAMC_SDCFG1_ACT2RW((int)(SDRAM_TRCD + 0.5)) |
386   - MCF_SDRAMC_SDCFG1_PRE2ACT((int)(SDRAM_TRP + 0.5)) |
387   - MCF_SDRAMC_SDCFG1_REF2ACT((int)(SDRAM_TRFC + 0.5)) |
388   - MCF_SDRAMC_SDCFG1_WTLAT(3),
389   - MCF_SDRAMC_SDCFG1);
390   - writel(MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL / 2 + 1) |
391   - MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL / 2 + SDRAM_TWR) |
392   - MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL + SDRAM_BL / 2 - 1.0) + 0.5)) |
393   - MCF_SDRAMC_SDCFG2_BL(SDRAM_BL - 1),
394   - MCF_SDRAMC_SDCFG2);
395   -
396   -
397   - /*
398   - * Precharge and enable write to SDMR
399   - */
400   - writel(MCF_SDRAMC_SDCR_MODE_EN |
401   - MCF_SDRAMC_SDCR_CKE |
402   - MCF_SDRAMC_SDCR_DDR |
403   - MCF_SDRAMC_SDCR_MUX(1) |
404   - MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI / (SYSTEM_PERIOD * 64)) - 1) + 0.5)) |
405   - MCF_SDRAMC_SDCR_PS_16 |
406   - MCF_SDRAMC_SDCR_IPALL,
407   - MCF_SDRAMC_SDCR);
408   -
409   - /*
410   - * Write extended mode register
411   - */
412   - writel(MCF_SDRAMC_SDMR_BNKAD_LEMR |
413   - MCF_SDRAMC_SDMR_AD(0x0) |
414   - MCF_SDRAMC_SDMR_CMD,
415   - MCF_SDRAMC_SDMR);
416   -
417   - /*
418   - * Write mode register and reset DLL
419   - */
420   - writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
421   - MCF_SDRAMC_SDMR_AD(0x163) |
422   - MCF_SDRAMC_SDMR_CMD,
423   - MCF_SDRAMC_SDMR);
424   -
425   - /*
426   - * Execute a PALL command
427   - */
428   - writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR);
429   -
430   - /*
431   - * Perform two REF cycles
432   - */
433   - writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
434   - writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
435   -
436   - /*
437   - * Write mode register and clear reset DLL
438   - */
439   - writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
440   - MCF_SDRAMC_SDMR_AD(0x063) |
441   - MCF_SDRAMC_SDMR_CMD,
442   - MCF_SDRAMC_SDMR);
443   -
444   - /*
445   - * Enable auto refresh and lock SDMR
446   - */
447   - writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN,
448   - MCF_SDRAMC_SDCR);
449   - writel(MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_DQS_OE(0xC),
450   - MCF_SDRAMC_SDCR);
451   - }
452   -}
453   -
454   -void gpio_init(void)
455   -{
456   - /* Enable UART0 pins */
457   - writew(MCF_GPIO_PAR_UART_PAR_URXD0 | MCF_GPIO_PAR_UART_PAR_UTXD0,
458   - MCFGPIO_PAR_UART);
459   -
460   - /*
461   - * Initialize TIN3 as a GPIO output to enable the write
462   - * half of the latch.
463   - */
464   - writeb(0x00, MCFGPIO_PAR_TIMER);
465   - writeb(0x08, MCFGPIO_PDDR_TIMER);
466   - writeb(0x00, MCFGPIO_PCLRR_TIMER);
467   -}
468   -
469   -int clock_pll(int fsys, int flags)
470   -{
471   - int fref, temp, fout, mfd;
472   - u32 i;
473   -
474   - fref = FREF;
475   -
476   - if (fsys == 0) {
477   - /* Return current PLL output */
478   - mfd = readb(MCF_PLL_PFDR);
479   -
480   - return (fref * mfd / (BUSDIV * 4));
481   - }
482   -
483   - /* Check bounds of requested system clock */
484   - if (fsys > MAX_FSYS)
485   - fsys = MAX_FSYS;
486   - if (fsys < MIN_FSYS)
487   - fsys = MIN_FSYS;
488   -
489   - /* Multiplying by 100 when calculating the temp value,
490   - and then dividing by 100 to calculate the mfd allows
491   - for exact values without needing to include floating
492   - point libraries. */
493   - temp = 100 * fsys / fref;
494   - mfd = 4 * BUSDIV * temp / 100;
495   -
496   - /* Determine the output frequency for selected values */
497   - fout = (fref * mfd / (BUSDIV * 4));
498   -
499   - /*
500   - * Check to see if the SDRAM has already been initialized.
501   - * If it has then the SDRAM needs to be put into self refresh
502   - * mode before reprogramming the PLL.
503   - */
504   - if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
505   - /* Put SDRAM into self refresh mode */
506   - writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE,
507   - MCF_SDRAMC_SDCR);
508   -
509   - /*
510   - * Initialize the PLL to generate the new system clock frequency.
511   - * The device must be put into LIMP mode to reprogram the PLL.
512   - */
513   -
514   - /* Enter LIMP mode */
515   - clock_limp(DEFAULT_LPD);
516   -
517   - /* Reprogram PLL for desired fsys */
518   - writeb(MCF_PLL_PODR_CPUDIV(BUSDIV/3) | MCF_PLL_PODR_BUSDIV(BUSDIV),
519   - MCF_PLL_PODR);
520   -
521   - writeb(mfd, MCF_PLL_PFDR);
522   -
523   - /* Exit LIMP mode */
524   - clock_exit_limp();
525   -
526   - /*
527   - * Return the SDRAM to normal operation if it is in use.
528   - */
529   - if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
530   - /* Exit self refresh mode */
531   - writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE,
532   - MCF_SDRAMC_SDCR);
533   -
534   - /* Errata - workaround for SDRAM opeartion after exiting LIMP mode */
535   - writel(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX);
536   -
537   - /* wait for DQS logic to relock */
538   - for (i = 0; i < 0x200; i++)
539   - ;
540   -
541   - return fout;
542   -}
543   -
544   -int clock_limp(int div)
545   -{
546   - u32 temp;
547   -
548   - /* Check bounds of divider */
549   - if (div < MIN_LPD)
550   - div = MIN_LPD;
551   - if (div > MAX_LPD)
552   - div = MAX_LPD;
553   -
554   - /* Save of the current value of the SSIDIV so we don't
555   - overwrite the value*/
556   - temp = readw(MCF_CCM_CDR) & MCF_CCM_CDR_SSIDIV(0xF);
557   -
558   - /* Apply the divider to the system clock */
559   - writew(MCF_CCM_CDR_LPDIV(div) | MCF_CCM_CDR_SSIDIV(temp), MCF_CCM_CDR);
560   -
561   - writew(readw(MCF_CCM_MISCCR) | MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
562   -
563   - return (FREF/(3*(1 << div)));
564   -}
565   -
566   -int clock_exit_limp(void)
567   -{
568   - int fout;
569   -
570   - /* Exit LIMP mode */
571   - writew(readw(MCF_CCM_MISCCR) & ~MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
572   -
573   - /* Wait for PLL to lock */
574   - while (!(readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_PLL_LOCK))
575   - ;
576   -
577   - fout = get_sys_clock();
578   -
579   - return fout;
580   -}
581   -
582   -int get_sys_clock(void)
583   -{
584   - int divider;
585   -
586   - /* Test to see if device is in LIMP mode */
587   - if (readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_LIMP) {
588   - divider = readw(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF);
589   - return (FREF/(2 << divider));
590   - }
591   - else
592   - return (FREF * readb(MCF_PLL_PFDR)) / (BUSDIV * 4);
593   -}
arch/m68k/platform/coldfire/m53xx.c
Diff comments   View file @ 977b58e
  1 +/***************************************************************************/
  2 +
  3 +/*
  4 + * m53xx.c -- platform support for ColdFire 53xx based boards
  5 + *
  6 + * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
  7 + * Copyright (C) 2000, Lineo (www.lineo.com)
  8 + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
  9 + * Copyright Freescale Semiconductor, Inc 2006
  10 + * Copyright (c) 2006, emlix, Sebastian Hess <shess@hessware.de>
  11 + *
  12 + * This program is free software; you can redistribute it and/or modify
  13 + * it under the terms of the GNU General Public License as published by
  14 + * the Free Software Foundation; either version 2 of the License, or
  15 + * (at your option) any later version.
  16 + */
  17 +
  18 +/***************************************************************************/
  19 +
  20 +#include <linux/kernel.h>
  21 +#include <linux/param.h>
  22 +#include <linux/init.h>
  23 +#include <linux/io.h>
  24 +#include <asm/machdep.h>
  25 +#include <asm/coldfire.h>
  26 +#include <asm/mcfsim.h>
  27 +#include <asm/mcfuart.h>
  28 +#include <asm/mcfdma.h>
  29 +#include <asm/mcfwdebug.h>
  30 +#include <asm/mcfclk.h>
  31 +
  32 +/***************************************************************************/
  33 +
  34 +DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
  35 +DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
  36 +DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
  37 +DEFINE_CLK(0, "edma", 17, MCF_CLK);
  38 +DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
  39 +DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
  40 +DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
  41 +DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
  42 +DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
  43 +DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
  44 +DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
  45 +DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
  46 +DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
  47 +DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
  48 +DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
  49 +DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
  50 +
  51 +DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
  52 +DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
  53 +DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK);
  54 +DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK);
  55 +DEFINE_CLK(0, "mcfpwm.0", 36, MCF_CLK);
  56 +DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK);
  57 +DEFINE_CLK(0, "mcfwdt.0", 38, MCF_CLK);
  58 +DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
  59 +DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
  60 +DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK);
  61 +DEFINE_CLK(0, "mcflcd.0", 43, MCF_CLK);
  62 +DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
  63 +DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
  64 +DEFINE_CLK(0, "sdram.0", 46, MCF_CLK);
  65 +DEFINE_CLK(0, "ssi.0", 47, MCF_CLK);
  66 +DEFINE_CLK(0, "pll.0", 48, MCF_CLK);
  67 +
  68 +DEFINE_CLK(1, "mdha.0", 32, MCF_CLK);
  69 +DEFINE_CLK(1, "skha.0", 33, MCF_CLK);
  70 +DEFINE_CLK(1, "rng.0", 34, MCF_CLK);
  71 +
  72 +struct clk *mcf_clks[] = {
  73 + &__clk_0_2, /* flexbus */
  74 + &__clk_0_8, /* mcfcan.0 */
  75 + &__clk_0_12, /* fec.0 */
  76 + &__clk_0_17, /* edma */
  77 + &__clk_0_18, /* intc.0 */
  78 + &__clk_0_19, /* intc.1 */
  79 + &__clk_0_21, /* iack.0 */
  80 + &__clk_0_22, /* mcfi2c.0 */
  81 + &__clk_0_23, /* mcfqspi.0 */
  82 + &__clk_0_24, /* mcfuart.0 */
  83 + &__clk_0_25, /* mcfuart.1 */
  84 + &__clk_0_26, /* mcfuart.2 */
  85 + &__clk_0_28, /* mcftmr.0 */
  86 + &__clk_0_29, /* mcftmr.1 */
  87 + &__clk_0_30, /* mcftmr.2 */
  88 + &__clk_0_31, /* mcftmr.3 */
  89 +
  90 + &__clk_0_32, /* mcfpit.0 */
  91 + &__clk_0_33, /* mcfpit.1 */
  92 + &__clk_0_34, /* mcfpit.2 */
  93 + &__clk_0_35, /* mcfpit.3 */
  94 + &__clk_0_36, /* mcfpwm.0 */
  95 + &__clk_0_37, /* mcfeport.0 */
  96 + &__clk_0_38, /* mcfwdt.0 */
  97 + &__clk_0_40, /* sys.0 */
  98 + &__clk_0_41, /* gpio.0 */
  99 + &__clk_0_42, /* mcfrtc.0 */
  100 + &__clk_0_43, /* mcflcd.0 */
  101 + &__clk_0_44, /* mcfusb-otg.0 */
  102 + &__clk_0_45, /* mcfusb-host.0 */
  103 + &__clk_0_46, /* sdram.0 */
  104 + &__clk_0_47, /* ssi.0 */
  105 + &__clk_0_48, /* pll.0 */
  106 +
  107 + &__clk_1_32, /* mdha.0 */
  108 + &__clk_1_33, /* skha.0 */
  109 + &__clk_1_34, /* rng.0 */
  110 + NULL,
  111 +};
  112 +
  113 +static struct clk * const enable_clks[] __initconst = {
  114 + &__clk_0_2, /* flexbus */
  115 + &__clk_0_18, /* intc.0 */
  116 + &__clk_0_19, /* intc.1 */
  117 + &__clk_0_21, /* iack.0 */
  118 + &__clk_0_24, /* mcfuart.0 */
  119 + &__clk_0_25, /* mcfuart.1 */
  120 + &__clk_0_26, /* mcfuart.2 */
  121 + &__clk_0_28, /* mcftmr.0 */
  122 + &__clk_0_29, /* mcftmr.1 */
  123 + &__clk_0_32, /* mcfpit.0 */
  124 + &__clk_0_33, /* mcfpit.1 */
  125 + &__clk_0_37, /* mcfeport.0 */
  126 + &__clk_0_40, /* sys.0 */
  127 + &__clk_0_41, /* gpio.0 */
  128 + &__clk_0_46, /* sdram.0 */
  129 + &__clk_0_48, /* pll.0 */
  130 +};
  131 +
  132 +static struct clk * const disable_clks[] __initconst = {
  133 + &__clk_0_8, /* mcfcan.0 */
  134 + &__clk_0_12, /* fec.0 */
  135 + &__clk_0_17, /* edma */
  136 + &__clk_0_22, /* mcfi2c.0 */
  137 + &__clk_0_23, /* mcfqspi.0 */
  138 + &__clk_0_30, /* mcftmr.2 */
  139 + &__clk_0_31, /* mcftmr.3 */
  140 + &__clk_0_34, /* mcfpit.2 */
  141 + &__clk_0_35, /* mcfpit.3 */
  142 + &__clk_0_36, /* mcfpwm.0 */
  143 + &__clk_0_38, /* mcfwdt.0 */
  144 + &__clk_0_42, /* mcfrtc.0 */
  145 + &__clk_0_43, /* mcflcd.0 */
  146 + &__clk_0_44, /* mcfusb-otg.0 */
  147 + &__clk_0_45, /* mcfusb-host.0 */
  148 + &__clk_0_47, /* ssi.0 */
  149 + &__clk_1_32, /* mdha.0 */
  150 + &__clk_1_33, /* skha.0 */
  151 + &__clk_1_34, /* rng.0 */
  152 +};
  153 +
  154 +
  155 +static void __init m53xx_clk_init(void)
  156 +{
  157 + unsigned i;
  158 +
  159 + /* make sure these clocks are enabled */
  160 + for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
  161 + __clk_init_enabled(enable_clks[i]);
  162 + /* make sure these clocks are disabled */
  163 + for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
  164 + __clk_init_disabled(disable_clks[i]);
  165 +}
  166 +
  167 +/***************************************************************************/
  168 +
  169 +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
  170 +
  171 +static void __init m53xx_qspi_init(void)
  172 +{
  173 + /* setup QSPS pins for QSPI with gpio CS control */
  174 + writew(0x01f0, MCFGPIO_PAR_QSPI);
  175 +}
  176 +
  177 +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
  178 +
  179 +/***************************************************************************/
  180 +
  181 +static void __init m53xx_uarts_init(void)
  182 +{
  183 + /* UART GPIO initialization */
  184 + writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART);
  185 +}
  186 +
  187 +/***************************************************************************/
  188 +
  189 +static void __init m53xx_fec_init(void)
  190 +{
  191 + u8 v;
  192 +
  193 + /* Set multi-function pins to ethernet mode for fec0 */
  194 + v = readb(MCFGPIO_PAR_FECI2C);
  195 + v |= MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
  196 + MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO;
  197 + writeb(v, MCFGPIO_PAR_FECI2C);
  198 +
  199 + v = readb(MCFGPIO_PAR_FEC);
  200 + v = MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC;
  201 + writeb(v, MCFGPIO_PAR_FEC);
  202 +}
  203 +
  204 +/***************************************************************************/
  205 +
  206 +void __init config_BSP(char *commandp, int size)
  207 +{
  208 +#if !defined(CONFIG_BOOTPARAM)
  209 + /* Copy command line from FLASH to local buffer... */
  210 + memcpy(commandp, (char *) 0x4000, 4);
  211 + if(strncmp(commandp, "kcl ", 4) == 0){
  212 + memcpy(commandp, (char *) 0x4004, size);
  213 + commandp[size-1] = 0;
  214 + } else {
  215 + memset(commandp, 0, size);
  216 + }
  217 +#endif
  218 + mach_sched_init = hw_timer_init;
  219 + m53xx_clk_init();
  220 + m53xx_uarts_init();
  221 + m53xx_fec_init();
  222 +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
  223 + m53xx_qspi_init();
  224 +#endif
  225 +
  226 +#ifdef CONFIG_BDM_DISABLE
  227 + /*
  228 + * Disable the BDM clocking. This also turns off most of the rest of
  229 + * the BDM device. This is good for EMC reasons. This option is not
  230 + * incompatible with the memory protection option.
  231 + */
  232 + wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
  233 +#endif
  234 +}
  235 +
  236 +/***************************************************************************/
  237 +/* Board initialization */
  238 +/***************************************************************************/
  239 +/*
  240 + * PLL min/max specifications
  241 + */
  242 +#define MAX_FVCO 500000 /* KHz */
  243 +#define MAX_FSYS 80000 /* KHz */
  244 +#define MIN_FSYS 58333 /* KHz */
  245 +#define FREF 16000 /* KHz */
  246 +
  247 +
  248 +#define MAX_MFD 135 /* Multiplier */
  249 +#define MIN_MFD 88 /* Multiplier */
  250 +#define BUSDIV 6 /* Divider */
  251 +
  252 +/*
  253 + * Low Power Divider specifications
  254 + */
  255 +#define MIN_LPD (1 << 0) /* Divider (not encoded) */
  256 +#define MAX_LPD (1 << 15) /* Divider (not encoded) */
  257 +#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
  258 +
  259 +#define SYS_CLK_KHZ 80000
  260 +#define SYSTEM_PERIOD 12.5
  261 +/*
  262 + * SDRAM Timing Parameters
  263 + */
  264 +#define SDRAM_BL 8 /* # of beats in a burst */
  265 +#define SDRAM_TWR 2 /* in clocks */
  266 +#define SDRAM_CASL 2.5 /* CASL in clocks */
  267 +#define SDRAM_TRCD 2 /* in clocks */
  268 +#define SDRAM_TRP 2 /* in clocks */
  269 +#define SDRAM_TRFC 7 /* in clocks */
  270 +#define SDRAM_TREFI 7800 /* in ns */
  271 +
  272 +#define EXT_SRAM_ADDRESS (0xC0000000)
  273 +#define FLASH_ADDRESS (0x00000000)
  274 +#define SDRAM_ADDRESS (0x40000000)
  275 +
  276 +#define NAND_FLASH_ADDRESS (0xD0000000)
  277 +
  278 +int sys_clk_khz = 0;
  279 +int sys_clk_mhz = 0;
  280 +
  281 +void wtm_init(void);
  282 +void scm_init(void);
  283 +void gpio_init(void);
  284 +void fbcs_init(void);
  285 +void sdramc_init(void);
  286 +int clock_pll (int fsys, int flags);
  287 +int clock_limp (int);
  288 +int clock_exit_limp (void);
  289 +int get_sys_clock (void);
  290 +
  291 +asmlinkage void __init sysinit(void)
  292 +{
  293 + sys_clk_khz = clock_pll(0, 0);
  294 + sys_clk_mhz = sys_clk_khz/1000;
  295 +
  296 + wtm_init();
  297 + scm_init();
  298 + gpio_init();
  299 + fbcs_init();
  300 + sdramc_init();
  301 +}
  302 +
  303 +void wtm_init(void)
  304 +{
  305 + /* Disable watchdog timer */
  306 + writew(0, MCF_WTM_WCR);
  307 +}
  308 +
  309 +#define MCF_SCM_BCR_GBW (0x00000100)
  310 +#define MCF_SCM_BCR_GBR (0x00000200)
  311 +
  312 +void scm_init(void)
  313 +{
  314 + /* All masters are trusted */
  315 + writel(0x77777777, MCF_SCM_MPR);
  316 +
  317 + /* Allow supervisor/user, read/write, and trusted/untrusted
  318 + access to all slaves */
  319 + writel(0, MCF_SCM_PACRA);
  320 + writel(0, MCF_SCM_PACRB);
  321 + writel(0, MCF_SCM_PACRC);
  322 + writel(0, MCF_SCM_PACRD);
  323 + writel(0, MCF_SCM_PACRE);
  324 + writel(0, MCF_SCM_PACRF);
  325 +
  326 + /* Enable bursts */
  327 + writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR);
  328 +}
  329 +
  330 +
  331 +void fbcs_init(void)
  332 +{
  333 + writeb(0x3E, MCFGPIO_PAR_CS);
  334 +
  335 + /* Latch chip select */
  336 + writel(0x10080000, MCF_FBCS1_CSAR);
  337 +
  338 + writel(0x002A3780, MCF_FBCS1_CSCR);
  339 + writel(MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
  340 +
  341 + /* Initialize latch to drive signals to inactive states */
  342 + writew(0xffff, 0x10080000);
  343 +
  344 + /* External SRAM */
  345 + writel(EXT_SRAM_ADDRESS, MCF_FBCS1_CSAR);
  346 + writel(MCF_FBCS_CSCR_PS_16 |
  347 + MCF_FBCS_CSCR_AA |
  348 + MCF_FBCS_CSCR_SBM |
  349 + MCF_FBCS_CSCR_WS(1),
  350 + MCF_FBCS1_CSCR);
  351 + writel(MCF_FBCS_CSMR_BAM_512K | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
  352 +
  353 + /* Boot Flash connected to FBCS0 */
  354 + writel(FLASH_ADDRESS, MCF_FBCS0_CSAR);
  355 + writel(MCF_FBCS_CSCR_PS_16 |
  356 + MCF_FBCS_CSCR_BEM |
  357 + MCF_FBCS_CSCR_AA |
  358 + MCF_FBCS_CSCR_SBM |
  359 + MCF_FBCS_CSCR_WS(7),
  360 + MCF_FBCS0_CSCR);
  361 + writel(MCF_FBCS_CSMR_BAM_32M | MCF_FBCS_CSMR_V, MCF_FBCS0_CSMR);
  362 +}
  363 +
  364 +void sdramc_init(void)
  365 +{
  366 + /*
  367 + * Check to see if the SDRAM has already been initialized
  368 + * by a run control tool
  369 + */
  370 + if (!(readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)) {
  371 + /* SDRAM chip select initialization */
  372 +
  373 + /* Initialize SDRAM chip select */
  374 + writel(MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) |
  375 + MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE),
  376 + MCF_SDRAMC_SDCS0);
  377 +
  378 + /*
  379 + * Basic configuration and initialization
  380 + */
  381 + writel(MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5)) |
  382 + MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1) |
  383 + MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL * 2) + 2)) |
  384 + MCF_SDRAMC_SDCFG1_ACT2RW((int)(SDRAM_TRCD + 0.5)) |
  385 + MCF_SDRAMC_SDCFG1_PRE2ACT((int)(SDRAM_TRP + 0.5)) |
  386 + MCF_SDRAMC_SDCFG1_REF2ACT((int)(SDRAM_TRFC + 0.5)) |
  387 + MCF_SDRAMC_SDCFG1_WTLAT(3),
  388 + MCF_SDRAMC_SDCFG1);
  389 + writel(MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL / 2 + 1) |
  390 + MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL / 2 + SDRAM_TWR) |
  391 + MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL + SDRAM_BL / 2 - 1.0) + 0.5)) |
  392 + MCF_SDRAMC_SDCFG2_BL(SDRAM_BL - 1),
  393 + MCF_SDRAMC_SDCFG2);
  394 +
  395 +
  396 + /*
  397 + * Precharge and enable write to SDMR
  398 + */
  399 + writel(MCF_SDRAMC_SDCR_MODE_EN |
  400 + MCF_SDRAMC_SDCR_CKE |
  401 + MCF_SDRAMC_SDCR_DDR |
  402 + MCF_SDRAMC_SDCR_MUX(1) |
  403 + MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI / (SYSTEM_PERIOD * 64)) - 1) + 0.5)) |
  404 + MCF_SDRAMC_SDCR_PS_16 |
  405 + MCF_SDRAMC_SDCR_IPALL,
  406 + MCF_SDRAMC_SDCR);
  407 +
  408 + /*
  409 + * Write extended mode register
  410 + */
  411 + writel(MCF_SDRAMC_SDMR_BNKAD_LEMR |
  412 + MCF_SDRAMC_SDMR_AD(0x0) |
  413 + MCF_SDRAMC_SDMR_CMD,
  414 + MCF_SDRAMC_SDMR);
  415 +
  416 + /*
  417 + * Write mode register and reset DLL
  418 + */
  419 + writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
  420 + MCF_SDRAMC_SDMR_AD(0x163) |
  421 + MCF_SDRAMC_SDMR_CMD,
  422 + MCF_SDRAMC_SDMR);
  423 +
  424 + /*
  425 + * Execute a PALL command
  426 + */
  427 + writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR);
  428 +
  429 + /*
  430 + * Perform two REF cycles
  431 + */
  432 + writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
  433 + writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
  434 +
  435 + /*
  436 + * Write mode register and clear reset DLL
  437 + */
  438 + writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
  439 + MCF_SDRAMC_SDMR_AD(0x063) |
  440 + MCF_SDRAMC_SDMR_CMD,
  441 + MCF_SDRAMC_SDMR);
  442 +
  443 + /*
  444 + * Enable auto refresh and lock SDMR
  445 + */
  446 + writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN,
  447 + MCF_SDRAMC_SDCR);
  448 + writel(MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_DQS_OE(0xC),
  449 + MCF_SDRAMC_SDCR);
  450 + }
  451 +}
  452 +
  453 +void gpio_init(void)
  454 +{
  455 + /* Enable UART0 pins */
  456 + writew(MCF_GPIO_PAR_UART_PAR_URXD0 | MCF_GPIO_PAR_UART_PAR_UTXD0,
  457 + MCFGPIO_PAR_UART);
  458 +
  459 + /*
  460 + * Initialize TIN3 as a GPIO output to enable the write
  461 + * half of the latch.
  462 + */
  463 + writeb(0x00, MCFGPIO_PAR_TIMER);
  464 + writeb(0x08, MCFGPIO_PDDR_TIMER);
  465 + writeb(0x00, MCFGPIO_PCLRR_TIMER);
  466 +}
  467 +
  468 +int clock_pll(int fsys, int flags)
  469 +{
  470 + int fref, temp, fout, mfd;
  471 + u32 i;
  472 +
  473 + fref = FREF;
  474 +
  475 + if (fsys == 0) {
  476 + /* Return current PLL output */
  477 + mfd = readb(MCF_PLL_PFDR);
  478 +
  479 + return (fref * mfd / (BUSDIV * 4));
  480 + }
  481 +
  482 + /* Check bounds of requested system clock */
  483 + if (fsys > MAX_FSYS)
  484 + fsys = MAX_FSYS;
  485 + if (fsys < MIN_FSYS)
  486 + fsys = MIN_FSYS;
  487 +
  488 + /* Multiplying by 100 when calculating the temp value,
  489 + and then dividing by 100 to calculate the mfd allows
  490 + for exact values without needing to include floating
  491 + point libraries. */
  492 + temp = 100 * fsys / fref;
  493 + mfd = 4 * BUSDIV * temp / 100;
  494 +
  495 + /* Determine the output frequency for selected values */
  496 + fout = (fref * mfd / (BUSDIV * 4));
  497 +
  498 + /*
  499 + * Check to see if the SDRAM has already been initialized.
  500 + * If it has then the SDRAM needs to be put into self refresh
  501 + * mode before reprogramming the PLL.
  502 + */
  503 + if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
  504 + /* Put SDRAM into self refresh mode */
  505 + writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE,
  506 + MCF_SDRAMC_SDCR);
  507 +
  508 + /*
  509 + * Initialize the PLL to generate the new system clock frequency.
  510 + * The device must be put into LIMP mode to reprogram the PLL.
  511 + */
  512 +
  513 + /* Enter LIMP mode */
  514 + clock_limp(DEFAULT_LPD);
  515 +
  516 + /* Reprogram PLL for desired fsys */
  517 + writeb(MCF_PLL_PODR_CPUDIV(BUSDIV/3) | MCF_PLL_PODR_BUSDIV(BUSDIV),
  518 + MCF_PLL_PODR);
  519 +
  520 + writeb(mfd, MCF_PLL_PFDR);
  521 +
  522 + /* Exit LIMP mode */
  523 + clock_exit_limp();
  524 +
  525 + /*
  526 + * Return the SDRAM to normal operation if it is in use.
  527 + */
  528 + if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
  529 + /* Exit self refresh mode */
  530 + writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE,
  531 + MCF_SDRAMC_SDCR);
  532 +
  533 + /* Errata - workaround for SDRAM opeartion after exiting LIMP mode */
  534 + writel(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX);
  535 +
  536 + /* wait for DQS logic to relock */
  537 + for (i = 0; i < 0x200; i++)
  538 + ;
  539 +
  540 + return fout;
  541 +}
  542 +
  543 +int clock_limp(int div)
  544 +{
  545 + u32 temp;
  546 +
  547 + /* Check bounds of divider */
  548 + if (div < MIN_LPD)
  549 + div = MIN_LPD;
  550 + if (div > MAX_LPD)
  551 + div = MAX_LPD;
  552 +
  553 + /* Save of the current value of the SSIDIV so we don't
  554 + overwrite the value*/
  555 + temp = readw(MCF_CCM_CDR) & MCF_CCM_CDR_SSIDIV(0xF);
  556 +
  557 + /* Apply the divider to the system clock */
  558 + writew(MCF_CCM_CDR_LPDIV(div) | MCF_CCM_CDR_SSIDIV(temp), MCF_CCM_CDR);
  559 +
  560 + writew(readw(MCF_CCM_MISCCR) | MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
  561 +
  562 + return (FREF/(3*(1 << div)));
  563 +}
  564 +
  565 +int clock_exit_limp(void)
  566 +{
  567 + int fout;
  568 +
  569 + /* Exit LIMP mode */
  570 + writew(readw(MCF_CCM_MISCCR) & ~MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
  571 +
  572 + /* Wait for PLL to lock */
  573 + while (!(readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_PLL_LOCK))
  574 + ;
  575 +
  576 + fout = get_sys_clock();
  577 +
  578 + return fout;
  579 +}
  580 +
  581 +int get_sys_clock(void)
  582 +{
  583 + int divider;
  584 +
  585 + /* Test to see if device is in LIMP mode */
  586 + if (readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_LIMP) {
  587 + divider = readw(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF);
  588 + return (FREF/(2 << divider));
  589 + }
  590 + else
  591 + return (FREF * readb(MCF_PLL_PFDR)) / (BUSDIV * 4);
  592 +}
arch/m68k/platform/coldfire/timers.c
Diff comments   View file @ 977b58e
... ... @@ -36,7 +36,7 @@
36 36 */
37 37 void coldfire_profile_init(void);
38 38  
39   -#if defined(CONFIG_M532x) || defined(CONFIG_M5441x)
  39 +#if defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
40 40 #define __raw_readtrr __raw_readl
41 41 #define __raw_writetrr __raw_writel
42 42 #else
drivers/tty/serial/68328serial.c
Diff comments   View file @ 977b58e
... ... @@ -14,7 +14,6 @@
14 14 * 2.4/2.5 port David McCullough
15 15 */
16 16  
17   -#include <asm/dbg.h>
18 17 #include <linux/module.h>
19 18 #include <linux/errno.h>
20 19 #include <linux/serial.h>
fs/romfs/mmap-nommu.c
Diff comments   View file @ 977b58e
... ... @@ -49,8 +49,11 @@
49 49 return (unsigned long) -EINVAL;
50 50  
51 51 offset += ROMFS_I(inode)->i_dataoffset;
52   - if (offset > mtd->size - len)
  52 + if (offset >= mtd->size)
53 53 return (unsigned long) -EINVAL;
  54 + /* the mapping mustn't extend beyond the EOF */
  55 + if ((offset + len) > mtd->size)
  56 + len = mtd->size - offset;
54 57  
55 58 ret = mtd_get_unmapped_area(mtd, len, offset, flags);
56 59 if (ret == -EOPNOTSUPP)