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Commit 9975a5f22a4fcc8d08035c65439900a983f891ad

Authored by Borislav Petkov
1 parent f4347553b3
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

amd64_edac: Fix DCT base address selector 

The correct check is to verify whether in high range we're below 4GB
and not to extract the DctSelBaseAddr again. See "2.8.5 Routing DRAM
Requests" in the F10h BKDG.

Cc: <stable@kernel.org> # .32.x .33.x .34.x
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Acked-by: Doug Thompson <dougthompson@xmission.com>

Showing 1 changed file with 1 additions and 1 deletions Side-by-side Diff

drivers/edac/amd64_edac.c
Diff comments   View file @ 9975a5f
... ... @@ -1435,7 +1435,7 @@
1435 1435 u64 chan_off;
1436 1436  
1437 1437 if (hi_range_sel) {
1438   - if (!(dct_sel_base_addr & 0xFFFFF800) &&
  1438 + if (!(dct_sel_base_addr & 0xFFFF0000) &&
1439 1439 hole_valid && (sys_addr >= 0x100000000ULL))
1440 1440 chan_off = hole_off << 16;
1441 1441 else