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Commit 9bac624b0fe0e51a7d5d2519634ed06ceeceb775

Authored by Ganesan Ramalingam
Committed by Ralf Baechle
1 parent 77c8da014a
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

MIPS: Netlogic: XLP PCIe controller support. 

Adds support for the XLP on-chip PCIe controller. On XLP, the
on-chip devices(including the 4 PCIe links) appear in the PCIe
configuration space of the XLP as PCI devices.

The changes are to initialize and register the PCIe controller,
enable hardware byte swap in the PCIe IO and MEM space, and to
enable PCIe interrupts.

Signed-off-by: Ganesan Ramalingam <ganesanr@netlogicmicro.com>
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3760/
Patchwork: https://patchwork.linux-mips.org/patch/4104/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Showing 7 changed files with 350 additions and 3 deletions Side-by-side Diff

... ... @@ -801,7 +801,6 @@
801 801 select SYS_HAS_CPU_XLP
802 802 select SYS_SUPPORTS_SMP
803 803 select HW_HAS_PCI
804   - select SWAP_IO_SPACE
805 804 select SYS_SUPPORTS_32BIT_KERNEL
806 805 select SYS_SUPPORTS_64BIT_KERNEL
807 806 select 64BIT_PHYS_ADDR
arch/mips/include/asm/netlogic/xlp-hal/iomap.h
Diff comments   View file @ 9bac624
... ... @@ -36,6 +36,9 @@
36 36 #define __NLM_HAL_IOMAP_H__
37 37  
38 38 #define XLP_DEFAULT_IO_BASE 0x18000000
  39 +#define XLP_DEFAULT_PCI_ECFG_BASE XLP_DEFAULT_IO_BASE
  40 +#define XLP_DEFAULT_PCI_CFG_BASE 0x1c000000
  41 +
39 42 #define NMI_BASE 0xbfc00000
40 43 #define XLP_IO_CLK 133333333
41 44  
arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
Diff comments   View file @ 9bac624
  1 +/*
  2 + * Copyright (c) 2003-2012 Broadcom Corporation
  3 + * All Rights Reserved
  4 + *
  5 + * This software is available to you under a choice of one of two
  6 + * licenses. You may choose to be licensed under the terms of the GNU
  7 + * General Public License (GPL) Version 2, available from the file
  8 + * COPYING in the main directory of this source tree, or the Broadcom
  9 + * license below:
  10 + *
  11 + * Redistribution and use in source and binary forms, with or without
  12 + * modification, are permitted provided that the following conditions
  13 + * are met:
  14 + *
  15 + * 1. Redistributions of source code must retain the above copyright
  16 + * notice, this list of conditions and the following disclaimer.
  17 + * 2. Redistributions in binary form must reproduce the above copyright
  18 + * notice, this list of conditions and the following disclaimer in
  19 + * the documentation and/or other materials provided with the
  20 + * distribution.
  21 + *
  22 + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
  23 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25 + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
  26 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29 + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30 + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31 + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32 + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33 + */
  34 +
  35 +#ifndef __NLM_HAL_PCIBUS_H__
  36 +#define __NLM_HAL_PCIBUS_H__
  37 +
  38 +/* PCIE Memory and IO regions */
  39 +#define PCIE_MEM_BASE 0xd0000000ULL
  40 +#define PCIE_MEM_LIMIT 0xdfffffffULL
  41 +#define PCIE_IO_BASE 0x14000000ULL
  42 +#define PCIE_IO_LIMIT 0x15ffffffULL
  43 +
  44 +#define PCIE_BRIDGE_CMD 0x1
  45 +#define PCIE_BRIDGE_MSI_CAP 0x14
  46 +#define PCIE_BRIDGE_MSI_ADDRL 0x15
  47 +#define PCIE_BRIDGE_MSI_ADDRH 0x16
  48 +#define PCIE_BRIDGE_MSI_DATA 0x17
  49 +
  50 +/* XLP Global PCIE configuration space registers */
  51 +#define PCIE_BYTE_SWAP_MEM_BASE 0x247
  52 +#define PCIE_BYTE_SWAP_MEM_LIM 0x248
  53 +#define PCIE_BYTE_SWAP_IO_BASE 0x249
  54 +#define PCIE_BYTE_SWAP_IO_LIM 0x24A
  55 +#define PCIE_MSI_STATUS 0x25A
  56 +#define PCIE_MSI_EN 0x25B
  57 +#define PCIE_INT_EN0 0x261
  58 +
  59 +/* PCIE_MSI_EN */
  60 +#define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF
  61 +
  62 +/* PCIE_INT_EN0 */
  63 +#define PCIE_MSI_INT_EN (1 << 9)
  64 +
  65 +#ifndef __ASSEMBLY__
  66 +
  67 +#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r)
  68 +#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v)
  69 +#define nlm_get_pcie_base(node, inst) \
  70 + nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst))
  71 +#define nlm_get_pcie_regbase(node, inst) \
  72 + (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ)
  73 +
  74 +int xlp_pcie_link_irt(int link);
  75 +#endif
  76 +#endif /* __NLM_HAL_PCIBUS_H__ */
arch/mips/include/asm/netlogic/xlp-hal/xlp.h
Diff comments   View file @ 9bac624
... ... @@ -35,8 +35,12 @@
35 35 #ifndef _NLM_HAL_XLP_H
36 36 #define _NLM_HAL_XLP_H
37 37  
38   -#define PIC_UART_0_IRQ 17
39   -#define PIC_UART_1_IRQ 18
  38 +#define PIC_UART_0_IRQ 17
  39 +#define PIC_UART_1_IRQ 18
  40 +#define PIC_PCIE_LINK_0_IRQ 19
  41 +#define PIC_PCIE_LINK_1_IRQ 20
  42 +#define PIC_PCIE_LINK_2_IRQ 21
  43 +#define PIC_PCIE_LINK_3_IRQ 22
40 44  
41 45 #ifndef __ASSEMBLY__
42 46  
arch/mips/netlogic/xlp/nlm_hal.c
Diff comments   View file @ 9bac624
... ... @@ -69,6 +69,14 @@
69 69 return PIC_IRT_UART_0_INDEX;
70 70 case PIC_UART_1_IRQ:
71 71 return PIC_IRT_UART_1_INDEX;
  72 + case PIC_PCIE_LINK_0_IRQ:
  73 + return PIC_IRT_PCIE_LINK_0_INDEX;
  74 + case PIC_PCIE_LINK_1_IRQ:
  75 + return PIC_IRT_PCIE_LINK_1_INDEX;
  76 + case PIC_PCIE_LINK_2_IRQ:
  77 + return PIC_IRT_PCIE_LINK_2_INDEX;
  78 + case PIC_PCIE_LINK_3_IRQ:
  79 + return PIC_IRT_PCIE_LINK_3_INDEX;
72 80 default:
73 81 return -1;
74 82 }
... ... @@ -81,6 +89,14 @@
81 89 return PIC_UART_0_IRQ;
82 90 case PIC_IRT_UART_1_INDEX:
83 91 return PIC_UART_1_IRQ;
  92 + case PIC_IRT_PCIE_LINK_0_INDEX:
  93 + return PIC_PCIE_LINK_0_IRQ;
  94 + case PIC_IRT_PCIE_LINK_1_INDEX:
  95 + return PIC_PCIE_LINK_1_IRQ;
  96 + case PIC_IRT_PCIE_LINK_2_INDEX:
  97 + return PIC_PCIE_LINK_2_IRQ;
  98 + case PIC_IRT_PCIE_LINK_3_INDEX:
  99 + return PIC_PCIE_LINK_3_IRQ;
84 100 default:
85 101 return -1;
86 102 }
arch/mips/pci/Makefile
Diff comments   View file @ 9bac624
... ... @@ -59,6 +59,7 @@
59 59 obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
60 60 obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
61 61 obj-$(CONFIG_CPU_XLR) += pci-xlr.o
  62 +obj-$(CONFIG_CPU_XLP) += pci-xlp.o
62 63  
63 64 ifdef CONFIG_PCI_MSI
64 65 obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
arch/mips/pci/pci-xlp.c
Diff comments   View file @ 9bac624
  1 +/*
  2 + * Copyright (c) 2003-2012 Broadcom Corporation
  3 + * All Rights Reserved
  4 + *
  5 + * This software is available to you under a choice of one of two
  6 + * licenses. You may choose to be licensed under the terms of the GNU
  7 + * General Public License (GPL) Version 2, available from the file
  8 + * COPYING in the main directory of this source tree, or the Broadcom
  9 + * license below:
  10 + *
  11 + * Redistribution and use in source and binary forms, with or without
  12 + * modification, are permitted provided that the following conditions
  13 + * are met:
  14 + *
  15 + * 1. Redistributions of source code must retain the above copyright
  16 + * notice, this list of conditions and the following disclaimer.
  17 + * 2. Redistributions in binary form must reproduce the above copyright
  18 + * notice, this list of conditions and the following disclaimer in
  19 + * the documentation and/or other materials provided with the
  20 + * distribution.
  21 + *
  22 + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
  23 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25 + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
  26 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29 + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30 + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31 + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32 + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33 + */
  34 +
  35 +#include <linux/types.h>
  36 +#include <linux/pci.h>
  37 +#include <linux/kernel.h>
  38 +#include <linux/init.h>
  39 +#include <linux/msi.h>
  40 +#include <linux/mm.h>
  41 +#include <linux/irq.h>
  42 +#include <linux/irqdesc.h>
  43 +#include <linux/console.h>
  44 +
  45 +#include <asm/io.h>
  46 +
  47 +#include <asm/netlogic/interrupt.h>
  48 +#include <asm/netlogic/haldefs.h>
  49 +
  50 +#include <asm/netlogic/xlp-hal/iomap.h>
  51 +#include <asm/netlogic/xlp-hal/pic.h>
  52 +#include <asm/netlogic/xlp-hal/xlp.h>
  53 +#include <asm/netlogic/xlp-hal/pcibus.h>
  54 +#include <asm/netlogic/xlp-hal/bridge.h>
  55 +
  56 +static void *pci_config_base;
  57 +
  58 +#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
  59 +
  60 +/* PCI ops */
  61 +static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
  62 + int where)
  63 +{
  64 + u32 data;
  65 + u32 *cfgaddr;
  66 +
  67 + cfgaddr = (u32 *)(pci_config_base +
  68 + pci_cfg_addr(bus->number, devfn, where & ~3));
  69 + data = *cfgaddr;
  70 + return data;
  71 +}
  72 +
  73 +static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
  74 + int where, u32 data)
  75 +{
  76 + u32 *cfgaddr;
  77 +
  78 + cfgaddr = (u32 *)(pci_config_base +
  79 + pci_cfg_addr(bus->number, devfn, where & ~3));
  80 + *cfgaddr = data;
  81 +}
  82 +
  83 +static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
  84 + int where, int size, u32 *val)
  85 +{
  86 + u32 data;
  87 +
  88 + if ((size == 2) && (where & 1))
  89 + return PCIBIOS_BAD_REGISTER_NUMBER;
  90 + else if ((size == 4) && (where & 3))
  91 + return PCIBIOS_BAD_REGISTER_NUMBER;
  92 +
  93 + data = pci_cfg_read_32bit(bus, devfn, where);
  94 +
  95 + if (size == 1)
  96 + *val = (data >> ((where & 3) << 3)) & 0xff;
  97 + else if (size == 2)
  98 + *val = (data >> ((where & 3) << 3)) & 0xffff;
  99 + else
  100 + *val = data;
  101 +
  102 + return PCIBIOS_SUCCESSFUL;
  103 +}
  104 +
  105 +
  106 +static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
  107 + int where, int size, u32 val)
  108 +{
  109 + u32 data;
  110 +
  111 + if ((size == 2) && (where & 1))
  112 + return PCIBIOS_BAD_REGISTER_NUMBER;
  113 + else if ((size == 4) && (where & 3))
  114 + return PCIBIOS_BAD_REGISTER_NUMBER;
  115 +
  116 + data = pci_cfg_read_32bit(bus, devfn, where);
  117 +
  118 + if (size == 1)
  119 + data = (data & ~(0xff << ((where & 3) << 3))) |
  120 + (val << ((where & 3) << 3));
  121 + else if (size == 2)
  122 + data = (data & ~(0xffff << ((where & 3) << 3))) |
  123 + (val << ((where & 3) << 3));
  124 + else
  125 + data = val;
  126 +
  127 + pci_cfg_write_32bit(bus, devfn, where, data);
  128 +
  129 + return PCIBIOS_SUCCESSFUL;
  130 +}
  131 +
  132 +struct pci_ops nlm_pci_ops = {
  133 + .read = nlm_pcibios_read,
  134 + .write = nlm_pcibios_write
  135 +};
  136 +
  137 +static struct resource nlm_pci_mem_resource = {
  138 + .name = "XLP PCI MEM",
  139 + .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
  140 + .end = 0xdfffffffUL,
  141 + .flags = IORESOURCE_MEM,
  142 +};
  143 +
  144 +static struct resource nlm_pci_io_resource = {
  145 + .name = "XLP IO MEM",
  146 + .start = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */
  147 + .end = 0x17ffffffUL,
  148 + .flags = IORESOURCE_IO,
  149 +};
  150 +
  151 +struct pci_controller nlm_pci_controller = {
  152 + .index = 0,
  153 + .pci_ops = &nlm_pci_ops,
  154 + .mem_resource = &nlm_pci_mem_resource,
  155 + .mem_offset = 0x00000000UL,
  156 + .io_resource = &nlm_pci_io_resource,
  157 + .io_offset = 0x00000000UL,
  158 +};
  159 +
  160 +static int get_irq_vector(const struct pci_dev *dev)
  161 +{
  162 + /*
  163 + * For XLP PCIe, there is an IRQ per Link, find out which
  164 + * link the device is on to assign interrupts
  165 + */
  166 + if (dev->bus->self == NULL)
  167 + return 0;
  168 +
  169 + switch (dev->bus->self->devfn) {
  170 + case 0x8:
  171 + return PIC_PCIE_LINK_0_IRQ;
  172 + case 0x9:
  173 + return PIC_PCIE_LINK_1_IRQ;
  174 + case 0xa:
  175 + return PIC_PCIE_LINK_2_IRQ;
  176 + case 0xb:
  177 + return PIC_PCIE_LINK_3_IRQ;
  178 + }
  179 + WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn);
  180 + return 0;
  181 +}
  182 +
  183 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  184 +{
  185 + return get_irq_vector(dev);
  186 +}
  187 +
  188 +/* Do platform specific device initialization at pci_enable_device() time */
  189 +int pcibios_plat_dev_init(struct pci_dev *dev)
  190 +{
  191 + return 0;
  192 +}
  193 +
  194 +static int xlp_enable_pci_bswap(void)
  195 +{
  196 + uint64_t pciebase, sysbase;
  197 + int node, i;
  198 + u32 reg;
  199 +
  200 + /* Chip-0 so node set to 0 */
  201 + node = 0;
  202 + sysbase = nlm_get_bridge_regbase(node);
  203 + /*
  204 + * Enable byte swap in hardware. Program each link's PCIe SWAP regions
  205 + * from the link's address ranges.
  206 + */
  207 + for (i = 0; i < 4; i++) {
  208 + pciebase = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, i));
  209 + if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
  210 + continue;
  211 +
  212 + reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_BASE0 + i);
  213 + nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_BASE, reg);
  214 +
  215 + reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_LIMIT0 + i);
  216 + nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_LIM,
  217 + reg | 0xfff);
  218 +
  219 + reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_BASE0 + i);
  220 + nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_BASE, reg);
  221 +
  222 + reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i);
  223 + nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
  224 + }
  225 + return 0;
  226 +}
  227 +
  228 +static int __init pcibios_init(void)
  229 +{
  230 + /* Firmware assigns PCI resources */
  231 + pci_set_flags(PCI_PROBE_ONLY);
  232 + pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);
  233 +
  234 + /* Extend IO port for memory mapped io */
  235 + ioport_resource.start = 0;
  236 + ioport_resource.end = ~0;
  237 +
  238 + xlp_enable_pci_bswap();
  239 + set_io_port_base(CKSEG1);
  240 + nlm_pci_controller.io_map_base = CKSEG1;
  241 +
  242 + register_pci_controller(&nlm_pci_controller);
  243 + pr_info("XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource,
  244 + &nlm_pci_mem_resource);
  245 +
  246 + return 0;
  247 +}
  248 +arch_initcall(pcibios_init);