Commit 9bbad7da76b3dd578fb55c862624366a8c9ccd22

Authored by Alexandre Bounine
Committed by Linus Torvalds
1 parent fbfa0748d8

rapidio/tsi721: fix bug in register offset definitions

Fix indexed register offset definitions that use decimal (wrong) instead
of hexadecimal (correct) notation for indexing multipliers.

Incorrect definitions do not affect Tsi721 driver in its current default
configuration because it uses only IDB queue 0.  Loss of inbound
doorbell functionality should be observed if queue other than 0 is used.

Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com>
Cc: Matt Porter <mporter@kernel.crashing.org>
Cc: Chul Kim <chul.kim@idt.com>
Cc: <stable@vger.kernel.org>		[3.2+]
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Showing 1 changed file with 15 additions and 15 deletions Side-by-side Diff

drivers/rapidio/devices/tsi721.h
... ... @@ -118,34 +118,34 @@
118 118  
119 119 #define TSI721_IDB_ENTRY_SIZE 64
120 120  
121   -#define TSI721_IDQ_CTL(x) (0x20000 + (x) * 1000)
  121 +#define TSI721_IDQ_CTL(x) (0x20000 + (x) * 0x1000)
122 122 #define TSI721_IDQ_SUSPEND 0x00000002
123 123 #define TSI721_IDQ_INIT 0x00000001
124 124  
125   -#define TSI721_IDQ_STS(x) (0x20004 + (x) * 1000)
  125 +#define TSI721_IDQ_STS(x) (0x20004 + (x) * 0x1000)
126 126 #define TSI721_IDQ_RUN 0x00200000
127 127  
128   -#define TSI721_IDQ_MASK(x) (0x20008 + (x) * 1000)
  128 +#define TSI721_IDQ_MASK(x) (0x20008 + (x) * 0x1000)
129 129 #define TSI721_IDQ_MASK_MASK 0xffff0000
130 130 #define TSI721_IDQ_MASK_PATT 0x0000ffff
131 131  
132   -#define TSI721_IDQ_RP(x) (0x2000c + (x) * 1000)
  132 +#define TSI721_IDQ_RP(x) (0x2000c + (x) * 0x1000)
133 133 #define TSI721_IDQ_RP_PTR 0x0007ffff
134 134  
135   -#define TSI721_IDQ_WP(x) (0x20010 + (x) * 1000)
  135 +#define TSI721_IDQ_WP(x) (0x20010 + (x) * 0x1000)
136 136 #define TSI721_IDQ_WP_PTR 0x0007ffff
137 137  
138   -#define TSI721_IDQ_BASEL(x) (0x20014 + (x) * 1000)
  138 +#define TSI721_IDQ_BASEL(x) (0x20014 + (x) * 0x1000)
139 139 #define TSI721_IDQ_BASEL_ADDR 0xffffffc0
140   -#define TSI721_IDQ_BASEU(x) (0x20018 + (x) * 1000)
141   -#define TSI721_IDQ_SIZE(x) (0x2001c + (x) * 1000)
  140 +#define TSI721_IDQ_BASEU(x) (0x20018 + (x) * 0x1000)
  141 +#define TSI721_IDQ_SIZE(x) (0x2001c + (x) * 0x1000)
142 142 #define TSI721_IDQ_SIZE_VAL(size) (__fls(size) - 4)
143 143 #define TSI721_IDQ_SIZE_MIN 512
144 144 #define TSI721_IDQ_SIZE_MAX (512 * 1024)
145 145  
146   -#define TSI721_SR_CHINT(x) (0x20040 + (x) * 1000)
147   -#define TSI721_SR_CHINTE(x) (0x20044 + (x) * 1000)
148   -#define TSI721_SR_CHINTSET(x) (0x20048 + (x) * 1000)
  146 +#define TSI721_SR_CHINT(x) (0x20040 + (x) * 0x1000)
  147 +#define TSI721_SR_CHINTE(x) (0x20044 + (x) * 0x1000)
  148 +#define TSI721_SR_CHINTSET(x) (0x20048 + (x) * 0x1000)
149 149 #define TSI721_SR_CHINT_ODBOK 0x00000020
150 150 #define TSI721_SR_CHINT_IDBQRCV 0x00000010
151 151 #define TSI721_SR_CHINT_SUSP 0x00000008
... ... @@ -156,7 +156,7 @@
156 156  
157 157 #define TSI721_IBWIN_NUM 8
158 158  
159   -#define TSI721_IBWINLB(x) (0x29000 + (x) * 20)
  159 +#define TSI721_IBWINLB(x) (0x29000 + (x) * 0x20)
160 160 #define TSI721_IBWINLB_BA 0xfffff000
161 161 #define TSI721_IBWINLB_WEN 0x00000001
162 162  
163 163  
164 164  
... ... @@ -187,13 +187,13 @@
187 187 */
188 188 #define TSI721_OBWIN_NUM TSI721_PC2SR_WINS
189 189  
190   -#define TSI721_OBWINLB(x) (0x40000 + (x) * 20)
  190 +#define TSI721_OBWINLB(x) (0x40000 + (x) * 0x20)
191 191 #define TSI721_OBWINLB_BA 0xffff8000
192 192 #define TSI721_OBWINLB_WEN 0x00000001
193 193  
194   -#define TSI721_OBWINUB(x) (0x40004 + (x) * 20)
  194 +#define TSI721_OBWINUB(x) (0x40004 + (x) * 0x20)
195 195  
196   -#define TSI721_OBWINSZ(x) (0x40008 + (x) * 20)
  196 +#define TSI721_OBWINSZ(x) (0x40008 + (x) * 0x20)
197 197 #define TSI721_OBWINSZ_SIZE 0x00001f00
198 198 #define TSI721_OBWIN_SIZE(size) (__fls(size) - 15)
199 199