clk: new driver for efm32 SoC

This patch adds support for the clocks provided by the Clock Management Unit of Energy Micro's efm32 Giant Gecko SoCs including device tree bindings. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>

clk: new driver for efm32 SoC
This patch adds support for the clocks provided by the Clock Management Unit of Energy Micro's efm32 Giant Gecko SoCs including device tree bindings. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Uwe Kleine-König · Mike Turquette
1 parent f61027426a
Showing 4 changed files with 135 additions and 0 deletions Side-by-side Diff
Documentation/devicetree/bindings/clock/efm32-clock.txt
drivers/clk/Makefile
drivers/clk/clk-efm32gg.c
include/dt-bindings/clock/efm32-cmu.h
+* Clock bindings for Energy Micro efm32 Giant Gecko's Clock Management Unit
+
+Required properties:
+- compatible: Should be "efm32gg,cmu"
+- reg: Base address and length of the register set
+- interrupts: Interrupt used by the CMU
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock ID in
+its "clocks" phandle cell. The header efm32-clk.h contains a list of available
+IDs.
@@ -11,6 +11,7 @@
  
 # SoCs specific
 obj-$(CONFIG_ARCH_BCM2835)	+= clk-bcm2835.o
+obj-$(CONFIG_ARCH_EFM32)	+= clk-efm32gg.o
 obj-$(CONFIG_ARCH_NOMADIK)	+= clk-nomadik.o
 obj-$(CONFIG_ARCH_HIGHBANK)	+= clk-highbank.o
 obj-$(CONFIG_ARCH_NSPIRE)	+= clk-nspire.o
+/*
+ * Copyright (C) 2013 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <dt-bindings/clock/efm32-cmu.h>
+
+#define CMU_HFPERCLKEN0		0x44
+
+static struct clk *clk[37];
+static struct clk_onecell_data clk_data = {
+	.clks = clk,
+	.clk_num = ARRAY_SIZE(clk),
+};
+
+static int __init efm32gg_cmu_init(struct device_node *np)
+{
+	int i;
+	void __iomem *base;
+
+	for (i = 0; i < ARRAY_SIZE(clk); ++i)
+		clk[i] = ERR_PTR(-ENOENT);
+
+	base = of_iomap(np, 0);
+	if (!base) {
+		pr_warn("Failed to map address range for efm32gg,cmu node\n");
+		return -EADDRNOTAVAIL;
+	}
+
+	clk[clk_HFXO] = clk_register_fixed_rate(NULL, "HFXO", NULL,
+			CLK_IS_ROOT, 48000000);
+
+	clk[clk_HFPERCLKUSART0] = clk_register_gate(NULL, "HFPERCLK.USART0",
+			"HFXO", 0, base + CMU_HFPERCLKEN0, 0, 0, NULL);
+	clk[clk_HFPERCLKUSART1] = clk_register_gate(NULL, "HFPERCLK.USART1",
+			"HFXO", 0, base + CMU_HFPERCLKEN0, 1, 0, NULL);
+	clk[clk_HFPERCLKUSART2] = clk_register_gate(NULL, "HFPERCLK.USART2",
+			"HFXO", 0, base + CMU_HFPERCLKEN0, 2, 0, NULL);
+	clk[clk_HFPERCLKUART0] = clk_register_gate(NULL, "HFPERCLK.UART0",
+			"HFXO", 0, base + CMU_HFPERCLKEN0, 3, 0, NULL);
+	clk[clk_HFPERCLKUART1] = clk_register_gate(NULL, "HFPERCLK.UART1",
+			"HFXO", 0, base + CMU_HFPERCLKEN0, 4, 0, NULL);
+	clk[clk_HFPERCLKTIMER0] = clk_register_gate(NULL, "HFPERCLK.TIMER0",
+			"HFXO", 0, base + CMU_HFPERCLKEN0, 5, 0, NULL);
+	clk[clk_HFPERCLKTIMER1] = clk_register_gate(NULL, "HFPERCLK.TIMER1",
+			"HFXO", 0, base + CMU_HFPERCLKEN0, 6, 0, NULL);
+	clk[clk_HFPERCLKTIMER2] = clk_register_gate(NULL, "HFPERCLK.TIMER2",
+			"HFXO", 0, base + CMU_HFPERCLKEN0, 7, 0, NULL);
+	clk[clk_HFPERCLKTIMER3] = clk_register_gate(NULL, "HFPERCLK.TIMER3",
+			"HFXO", 0, base + CMU_HFPERCLKEN0, 8, 0, NULL);
+	clk[clk_HFPERCLKACMP0] = clk_register_gate(NULL, "HFPERCLK.ACMP0",
+			"HFXO", 0, base + CMU_HFPERCLKEN0, 9, 0, NULL);
+	clk[clk_HFPERCLKACMP1] = clk_register_gate(NULL, "HFPERCLK.ACMP1",
+			"HFXO", 0, base + CMU_HFPERCLKEN0, 10, 0, NULL);
+	clk[clk_HFPERCLKI2C0] = clk_register_gate(NULL, "HFPERCLK.I2C0",
+			"HFXO", 0, base + CMU_HFPERCLKEN0, 11, 0, NULL);
+	clk[clk_HFPERCLKI2C1] = clk_register_gate(NULL, "HFPERCLK.I2C1",
+			"HFXO", 0, base + CMU_HFPERCLKEN0, 12, 0, NULL);
+	clk[clk_HFPERCLKGPIO] = clk_register_gate(NULL, "HFPERCLK.GPIO",
+			"HFXO", 0, base + CMU_HFPERCLKEN0, 13, 0, NULL);
+	clk[clk_HFPERCLKVCMP] = clk_register_gate(NULL, "HFPERCLK.VCMP",
+			"HFXO", 0, base + CMU_HFPERCLKEN0, 14, 0, NULL);
+	clk[clk_HFPERCLKPRS] = clk_register_gate(NULL, "HFPERCLK.PRS",
+			"HFXO", 0, base + CMU_HFPERCLKEN0, 15, 0, NULL);
+	clk[clk_HFPERCLKADC0] = clk_register_gate(NULL, "HFPERCLK.ADC0",
+			"HFXO", 0, base + CMU_HFPERCLKEN0, 16, 0, NULL);
+	clk[clk_HFPERCLKDAC0] = clk_register_gate(NULL, "HFPERCLK.DAC0",
+			"HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL);
+
+	return of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init);
+#ifndef __DT_BINDINGS_CLOCK_EFM32_CMU_H
+#define __DT_BINDINGS_CLOCK_EFM32_CMU_H
+
+#define clk_HFXO		0
+#define clk_HFRCO		1
+#define clk_LFXO		2
+#define clk_LFRCO		3
+#define clk_ULFRCO		4
+#define clk_AUXHFRCO		5
+#define clk_HFCLKNODIV		6
+#define clk_HFCLK		7
+#define clk_HFPERCLK		8
+#define clk_HFCORECLK		9
+#define clk_LFACLK		10
+#define clk_LFBCLK		11
+#define clk_WDOGCLK		12
+#define clk_HFCORECLKDMA	13
+#define clk_HFCORECLKAES	14
+#define clk_HFCORECLKUSBC	15
+#define clk_HFCORECLKUSB	16
+#define clk_HFCORECLKLE		17
+#define clk_HFCORECLKEBI	18
+#define clk_HFPERCLKUSART0	19
+#define clk_HFPERCLKUSART1	20
+#define clk_HFPERCLKUSART2	21
+#define clk_HFPERCLKUART0	22
+#define clk_HFPERCLKUART1	23
+#define clk_HFPERCLKTIMER0	24
+#define clk_HFPERCLKTIMER1	25
+#define clk_HFPERCLKTIMER2	26
+#define clk_HFPERCLKTIMER3	27
+#define clk_HFPERCLKACMP0	28
+#define clk_HFPERCLKACMP1	29
+#define clk_HFPERCLKI2C0	30
+#define clk_HFPERCLKI2C1	31
+#define clk_HFPERCLKGPIO	32
+#define clk_HFPERCLKVCMP	33
+#define clk_HFPERCLKPRS		34
+#define clk_HFPERCLKADC0	35
+#define clk_HFPERCLKDAC0	36
+
+#endif /* __DT_BINDINGS_CLOCK_EFM32_CMU_H */
	1	+* Clock bindings for Energy Micro efm32 Giant Gecko's Clock Management Unit
	2	+
	3	+Required properties:
	4	+- compatible: Should be "efm32gg,cmu"
	5	+- reg: Base address and length of the register set
	6	+- interrupts: Interrupt used by the CMU
	7	+- #clock-cells: Should be <1>
	8	+
	9	+The clock consumer should specify the desired clock by having the clock ID in
	10	+its "clocks" phandle cell. The header efm32-clk.h contains a list of available
	11	+IDs.
...	...	@@ -11,6 +11,7 @@
11	11
12	12	# SoCs specific
13	13	obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
	14	+obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
14	15	obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
15	16	obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
16	17	obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
	1	+/*
	2	+ * Copyright (C) 2013 Pengutronix
	3	+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
	4	+ *
	5	+ * This program is free software; you can redistribute it and/or modify it under
	6	+ * the terms of the GNU General Public License version 2 as published by the
	7	+ * Free Software Foundation.
	8	+ */
	9	+#include <linux/clk.h>
	10	+#include <linux/io.h>
	11	+#include <linux/clk-provider.h>
	12	+#include <linux/of.h>
	13	+#include <linux/of_address.h>
	14	+
	15	+#include <dt-bindings/clock/efm32-cmu.h>
	16	+
	17	+#define CMU_HFPERCLKEN0 0x44
	18	+
	19	+static struct clk *clk[37];
	20	+static struct clk_onecell_data clk_data = {
	21	+ .clks = clk,
	22	+ .clk_num = ARRAY_SIZE(clk),
	23	+};
	24	+
	25	+static int __init efm32gg_cmu_init(struct device_node *np)
	26	+{
	27	+ int i;
	28	+ void __iomem *base;
	29	+
	30	+ for (i = 0; i < ARRAY_SIZE(clk); ++i)
	31	+ clk[i] = ERR_PTR(-ENOENT);
	32	+
	33	+ base = of_iomap(np, 0);
	34	+ if (!base) {
	35	+ pr_warn("Failed to map address range for efm32gg,cmu node\n");
	36	+ return -EADDRNOTAVAIL;
	37	+ }
	38	+
	39	+ clk[clk_HFXO] = clk_register_fixed_rate(NULL, "HFXO", NULL,
	40	+ CLK_IS_ROOT, 48000000);
	41	+
	42	+ clk[clk_HFPERCLKUSART0] = clk_register_gate(NULL, "HFPERCLK.USART0",
	43	+ "HFXO", 0, base + CMU_HFPERCLKEN0, 0, 0, NULL);
	44	+ clk[clk_HFPERCLKUSART1] = clk_register_gate(NULL, "HFPERCLK.USART1",
	45	+ "HFXO", 0, base + CMU_HFPERCLKEN0, 1, 0, NULL);
	46	+ clk[clk_HFPERCLKUSART2] = clk_register_gate(NULL, "HFPERCLK.USART2",
	47	+ "HFXO", 0, base + CMU_HFPERCLKEN0, 2, 0, NULL);
	48	+ clk[clk_HFPERCLKUART0] = clk_register_gate(NULL, "HFPERCLK.UART0",
	49	+ "HFXO", 0, base + CMU_HFPERCLKEN0, 3, 0, NULL);
	50	+ clk[clk_HFPERCLKUART1] = clk_register_gate(NULL, "HFPERCLK.UART1",
	51	+ "HFXO", 0, base + CMU_HFPERCLKEN0, 4, 0, NULL);
	52	+ clk[clk_HFPERCLKTIMER0] = clk_register_gate(NULL, "HFPERCLK.TIMER0",
	53	+ "HFXO", 0, base + CMU_HFPERCLKEN0, 5, 0, NULL);
	54	+ clk[clk_HFPERCLKTIMER1] = clk_register_gate(NULL, "HFPERCLK.TIMER1",
	55	+ "HFXO", 0, base + CMU_HFPERCLKEN0, 6, 0, NULL);
	56	+ clk[clk_HFPERCLKTIMER2] = clk_register_gate(NULL, "HFPERCLK.TIMER2",
	57	+ "HFXO", 0, base + CMU_HFPERCLKEN0, 7, 0, NULL);
	58	+ clk[clk_HFPERCLKTIMER3] = clk_register_gate(NULL, "HFPERCLK.TIMER3",
	59	+ "HFXO", 0, base + CMU_HFPERCLKEN0, 8, 0, NULL);
	60	+ clk[clk_HFPERCLKACMP0] = clk_register_gate(NULL, "HFPERCLK.ACMP0",
	61	+ "HFXO", 0, base + CMU_HFPERCLKEN0, 9, 0, NULL);
	62	+ clk[clk_HFPERCLKACMP1] = clk_register_gate(NULL, "HFPERCLK.ACMP1",
	63	+ "HFXO", 0, base + CMU_HFPERCLKEN0, 10, 0, NULL);
	64	+ clk[clk_HFPERCLKI2C0] = clk_register_gate(NULL, "HFPERCLK.I2C0",
	65	+ "HFXO", 0, base + CMU_HFPERCLKEN0, 11, 0, NULL);
	66	+ clk[clk_HFPERCLKI2C1] = clk_register_gate(NULL, "HFPERCLK.I2C1",
	67	+ "HFXO", 0, base + CMU_HFPERCLKEN0, 12, 0, NULL);
	68	+ clk[clk_HFPERCLKGPIO] = clk_register_gate(NULL, "HFPERCLK.GPIO",
	69	+ "HFXO", 0, base + CMU_HFPERCLKEN0, 13, 0, NULL);
	70	+ clk[clk_HFPERCLKVCMP] = clk_register_gate(NULL, "HFPERCLK.VCMP",
	71	+ "HFXO", 0, base + CMU_HFPERCLKEN0, 14, 0, NULL);
	72	+ clk[clk_HFPERCLKPRS] = clk_register_gate(NULL, "HFPERCLK.PRS",
	73	+ "HFXO", 0, base + CMU_HFPERCLKEN0, 15, 0, NULL);
	74	+ clk[clk_HFPERCLKADC0] = clk_register_gate(NULL, "HFPERCLK.ADC0",
	75	+ "HFXO", 0, base + CMU_HFPERCLKEN0, 16, 0, NULL);
	76	+ clk[clk_HFPERCLKDAC0] = clk_register_gate(NULL, "HFPERCLK.DAC0",
	77	+ "HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL);
	78	+
	79	+ return of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
	80	+}
	81	+CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init);
	1	+#ifndef __DT_BINDINGS_CLOCK_EFM32_CMU_H
	2	+#define __DT_BINDINGS_CLOCK_EFM32_CMU_H
	3	+
	4	+#define clk_HFXO 0
	5	+#define clk_HFRCO 1
	6	+#define clk_LFXO 2
	7	+#define clk_LFRCO 3
	8	+#define clk_ULFRCO 4
	9	+#define clk_AUXHFRCO 5
	10	+#define clk_HFCLKNODIV 6
	11	+#define clk_HFCLK 7
	12	+#define clk_HFPERCLK 8
	13	+#define clk_HFCORECLK 9
	14	+#define clk_LFACLK 10
	15	+#define clk_LFBCLK 11
	16	+#define clk_WDOGCLK 12
	17	+#define clk_HFCORECLKDMA 13
	18	+#define clk_HFCORECLKAES 14
	19	+#define clk_HFCORECLKUSBC 15
	20	+#define clk_HFCORECLKUSB 16
	21	+#define clk_HFCORECLKLE 17
	22	+#define clk_HFCORECLKEBI 18
	23	+#define clk_HFPERCLKUSART0 19
	24	+#define clk_HFPERCLKUSART1 20
	25	+#define clk_HFPERCLKUSART2 21
	26	+#define clk_HFPERCLKUART0 22
	27	+#define clk_HFPERCLKUART1 23
	28	+#define clk_HFPERCLKTIMER0 24
	29	+#define clk_HFPERCLKTIMER1 25
	30	+#define clk_HFPERCLKTIMER2 26
	31	+#define clk_HFPERCLKTIMER3 27
	32	+#define clk_HFPERCLKACMP0 28
	33	+#define clk_HFPERCLKACMP1 29
	34	+#define clk_HFPERCLKI2C0 30
	35	+#define clk_HFPERCLKI2C1 31
	36	+#define clk_HFPERCLKGPIO 32
	37	+#define clk_HFPERCLKVCMP 33
	38	+#define clk_HFPERCLKPRS 34
	39	+#define clk_HFPERCLKADC0 35
	40	+#define clk_HFPERCLKDAC0 36
	41	+
	42	+#endif /* __DT_BINDINGS_CLOCK_EFM32_CMU_H */