Commit a4463c4f669ac776a1f456fb51fd3c8c99ef904f

Authored by Amit Daniel Kachhap
Committed by Eduardo Valentin
1 parent 7ca04e587e

thermal: exynos: Fix to clear only the generated interrupts

This patch uses the TMU status register to know the generated interrupts
and only clear them in the interrupt handler.

Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Acked-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Acked-by: Eduardo Valentin <eduardo.valentin@ti.com>
Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>

Showing 2 changed files with 7 additions and 6 deletions Side-by-side Diff

drivers/thermal/samsung/exynos_tmu.c
... ... @@ -351,17 +351,16 @@
351 351 struct exynos_tmu_data, irq_work);
352 352 struct exynos_tmu_platform_data *pdata = data->pdata;
353 353 const struct exynos_tmu_registers *reg = pdata->registers;
  354 + unsigned int val_irq;
354 355  
355 356 exynos_report_trigger();
356 357 mutex_lock(&data->lock);
357 358 clk_enable(data->clk);
358 359  
359   - if (data->soc == SOC_ARCH_EXYNOS)
360   - writel((reg->inten_rise_mask << reg->inten_rise_shift) |
361   - (reg->inten_fall_mask << reg->inten_fall_shift),
362   - data->base + reg->tmu_intclear);
363   - else
364   - writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
  360 + /* TODO: take action based on particular interrupt */
  361 + val_irq = readl(data->base + reg->tmu_intstat);
  362 + /* clear the interrupts */
  363 + writel(val_irq, data->base + reg->tmu_intclear);
365 364  
366 365 clk_disable(data->clk);
367 366 mutex_unlock(&data->lock);
drivers/thermal/samsung/exynos_tmu_data.c
... ... @@ -45,6 +45,7 @@
45 45 .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
46 46 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
47 47 .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
  48 + .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
48 49 .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
49 50 };
50 51 struct exynos_tmu_platform_data const exynos4210_default_tmu_data = {
... ... @@ -112,6 +113,7 @@
112 113 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
113 114 .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
114 115 .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
  116 + .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
115 117 .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
116 118 .emul_con = EXYNOS_EMUL_CON,
117 119 .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,