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Commit a69ba6293d11b7dfd395a742f3449d6ddda8ecad

Authored by Jayachandran C
Committed by John Crispin
1 parent a264b5e8dc
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

MIPS: Netlogic: Split XLP L1 i-cache among threads 

Since we now use r4k cache code for Netlogic XLP, it is
better to split L1 icache among the active threads, so that
threads won't step on each other while flushing icache.

The L1 dcache is already split among the threads in the core.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4787/
Signed-off-by: John Crispin <blogic@openwrt.org>

Showing 2 changed files with 8 additions and 0 deletions Side-by-side Diff

arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
Diff comments   View file @ a69ba62
... ... @@ -46,6 +46,8 @@
46 46 #define CPU_BLOCKID_FPU 9
47 47 #define CPU_BLOCKID_MAP 10
48 48  
  49 +#define ICU_DEFEATURE 0x100
  50 +
49 51 #define LSU_DEFEATURE 0x304
50 52 #define LSU_DEBUG_ADDR 0x305
51 53 #define LSU_DEBUG_DATA0 0x306
arch/mips/netlogic/common/smpboot.S
Diff comments   View file @ a69ba62
... ... @@ -69,6 +69,12 @@
69 69 #endif
70 70 mtcr t1, t0
71 71  
  72 + li t0, ICU_DEFEATURE
  73 + mfcr t1, t0
  74 + ori t1, 0x1000 /* Enable Icache partitioning */
  75 + mtcr t1, t0
  76 +
  77 +
72 78 #ifdef XLP_AX_WORKAROUND
73 79 li t0, SCHED_DEFEATURE
74 80 lui t1, 0x0100 /* Disable BRU accepting ALU ops */