Commit a895bf8b1e1ea4c032a8fa8a09475a2ce09fe77a

Authored by Mauro Carvalho Chehab
1 parent 5e2af0c09e

edac: move nr_pages to dimm struct

The number of pages is a dimm property. Move it to the dimm struct.

After this change, it is possible to add sysfs nodes for the DIMM's that
will properly represent the DIMM stick properties, including its size.

A TODO fix here is to properly represent dual-rank/quad-rank DIMMs when
the memory controller represents the memory via chip select rows.

Reviewed-by: Aristeu Rozanski <arozansk@redhat.com>
Acked-by: Borislav Petkov <borislav.petkov@amd.com>
Acked-by: Chris Metcalf <cmetcalf@tilera.com>
Cc: Doug Thompson <norsk5@yahoo.com>
Cc: Mark Gross <mark.gross@intel.com>
Cc: Jason Uhlenkott <juhlenko@akamai.com>
Cc: Tim Small <tim@buttersideup.com>
Cc: Ranganathan Desikan <ravi@jetztechnologies.com>
Cc: "Arvind R." <arvino55@gmail.com>
Cc: Olof Johansson <olof@lixom.net>
Cc: Egor Martovetsky <egor@pasemi.com>
Cc: Michal Marek <mmarek@suse.cz>
Cc: Jiri Kosina <jkosina@suse.cz>
Cc: Joe Perches <joe@perches.com>
Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Hitoshi Mitake <h.mitake@gmail.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: "Niklas Söderlund" <niklas.soderlund@ericsson.com>
Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
Cc: Josh Boyer <jwboyer@gmail.com>
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

Showing 28 changed files with 146 additions and 116 deletions Side-by-side Diff

drivers/edac/amd64_edac.c
... ... @@ -2152,7 +2152,7 @@
2152 2152 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode) << (20 - PAGE_SHIFT);
2153 2153  
2154 2154 debugf0(" (csrow=%d) DBAM map index= %d\n", csrow_nr, cs_mode);
2155   - debugf0(" nr_pages= %u channel-count = %d\n",
  2155 + debugf0(" nr_pages/channel= %u channel-count = %d\n",
2156 2156 nr_pages, pvt->channel_count);
2157 2157  
2158 2158 return nr_pages;
... ... @@ -2171,6 +2171,7 @@
2171 2171 int i, j, empty = 1;
2172 2172 enum mem_type mtype;
2173 2173 enum edac_type edac_mode;
  2174 + int nr_pages = 0;
2174 2175  
2175 2176 amd64_read_pci_cfg(pvt->F3, NBCFG, &val);
2176 2177  
2177 2178  
... ... @@ -2194,9 +2195,9 @@
2194 2195  
2195 2196 empty = 0;
2196 2197 if (csrow_enabled(i, 0, pvt))
2197   - csrow->nr_pages = amd64_csrow_nr_pages(pvt, 0, i);
  2198 + nr_pages = amd64_csrow_nr_pages(pvt, 0, i);
2198 2199 if (csrow_enabled(i, 1, pvt))
2199   - csrow->nr_pages += amd64_csrow_nr_pages(pvt, 1, i);
  2200 + nr_pages += amd64_csrow_nr_pages(pvt, 1, i);
2200 2201  
2201 2202 get_cs_base_and_mask(pvt, i, 0, &base, &mask);
2202 2203 /* 8 bytes of resolution */
... ... @@ -2204,7 +2205,7 @@
2204 2205 mtype = amd64_determine_memory_type(pvt, i);
2205 2206  
2206 2207 debugf1(" for MC node %d csrow %d:\n", pvt->mc_node_id, i);
2207   - debugf1(" nr_pages: %u\n", csrow->nr_pages);
  2208 + debugf1(" nr_pages: %u\n", nr_pages * pvt->channel_count);
2208 2209  
2209 2210 /*
2210 2211 * determine whether CHIPKILL or JUST ECC or NO ECC is operating
... ... @@ -2218,6 +2219,7 @@
2218 2219 for (j = 0; j < pvt->channel_count; j++) {
2219 2220 csrow->channels[j].dimm->mtype = mtype;
2220 2221 csrow->channels[j].dimm->edac_mode = edac_mode;
  2222 + csrow->channels[j].dimm->nr_pages = nr_pages;
2221 2223 }
2222 2224 }
2223 2225  
drivers/edac/amd76x_edac.c
... ... @@ -205,10 +205,10 @@
205 205 mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
206 206 pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms);
207 207 csrow->first_page = mba_base >> PAGE_SHIFT;
208   - csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
209   - csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
  208 + dimm->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
  209 + csrow->last_page = csrow->first_page + dimm->nr_pages - 1;
210 210 csrow->page_mask = mba_mask >> PAGE_SHIFT;
211   - dimm->grain = csrow->nr_pages << PAGE_SHIFT;
  211 + dimm->grain = dimm->nr_pages << PAGE_SHIFT;
212 212 dimm->mtype = MEM_RDDR;
213 213 dimm->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
214 214 dimm->edac_mode = edac_mode;
drivers/edac/cell_edac.c
... ... @@ -128,6 +128,7 @@
128 128 struct cell_edac_priv *priv = mci->pvt_info;
129 129 struct device_node *np;
130 130 int j;
  131 + u32 nr_pages;
131 132  
132 133 for (np = NULL;
133 134 (np = of_find_node_by_name(np, "memory")) != NULL;) {
134 135  
135 136  
... ... @@ -142,19 +143,20 @@
142 143 if (of_node_to_nid(np) != priv->node)
143 144 continue;
144 145 csrow->first_page = r.start >> PAGE_SHIFT;
145   - csrow->nr_pages = resource_size(&r) >> PAGE_SHIFT;
146   - csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
  146 + nr_pages = resource_size(&r) >> PAGE_SHIFT;
  147 + csrow->last_page = csrow->first_page + nr_pages - 1;
147 148  
148 149 for (j = 0; j < csrow->nr_channels; j++) {
149 150 dimm = csrow->channels[j].dimm;
150 151 dimm->mtype = MEM_XDR;
151 152 dimm->edac_mode = EDAC_SECDED;
  153 + dimm->nr_pages = nr_pages / csrow->nr_channels;
152 154 }
153 155 dev_dbg(mci->dev,
154 156 "Initialized on node %d, chanmask=0x%x,"
155 157 " first_page=0x%lx, nr_pages=0x%x\n",
156 158 priv->node, priv->chanmask,
157   - csrow->first_page, csrow->nr_pages);
  159 + csrow->first_page, dimm->nr_pages);
158 160 break;
159 161 }
160 162 }
drivers/edac/cpc925_edac.c
... ... @@ -332,7 +332,7 @@
332 332 struct dimm_info *dimm;
333 333 int index, j;
334 334 u32 mbmr, mbbar, bba;
335   - unsigned long row_size, last_nr_pages = 0;
  335 + unsigned long row_size, nr_pages, last_nr_pages = 0;
336 336  
337 337 get_total_mem(pdata);
338 338  
339 339  
... ... @@ -351,12 +351,14 @@
351 351  
352 352 row_size = bba * (1UL << 28); /* 256M */
353 353 csrow->first_page = last_nr_pages;
354   - csrow->nr_pages = row_size >> PAGE_SHIFT;
355   - csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
  354 + nr_pages = row_size >> PAGE_SHIFT;
  355 + csrow->last_page = csrow->first_page + nr_pages - 1;
356 356 last_nr_pages = csrow->last_page + 1;
357 357  
358 358 for (j = 0; j < csrow->nr_channels; j++) {
359 359 dimm = csrow->channels[j].dimm;
  360 +
  361 + dimm->nr_pages = nr_pages / csrow->nr_channels;
360 362 dimm->mtype = MEM_RDDR;
361 363 dimm->edac_mode = EDAC_SECDED;
362 364  
drivers/edac/e752x_edac.c
... ... @@ -1044,7 +1044,7 @@
1044 1044 int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */
1045 1045 int drc_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */
1046 1046 u8 value;
1047   - u32 dra, drc, cumul_size, i;
  1047 + u32 dra, drc, cumul_size, i, nr_pages;
1048 1048  
1049 1049 dra = 0;
1050 1050 for (index = 0; index < 4; index++) {
1051 1051  
... ... @@ -1078,11 +1078,13 @@
1078 1078  
1079 1079 csrow->first_page = last_cumul_size;
1080 1080 csrow->last_page = cumul_size - 1;
1081   - csrow->nr_pages = cumul_size - last_cumul_size;
  1081 + nr_pages = cumul_size - last_cumul_size;
1082 1082 last_cumul_size = cumul_size;
1083 1083  
1084 1084 for (i = 0; i < drc_chan + 1; i++) {
1085 1085 struct dimm_info *dimm = csrow->channels[i].dimm;
  1086 +
  1087 + dimm->nr_pages = nr_pages / (drc_chan + 1);
1086 1088 dimm->grain = 1 << 12; /* 4KiB - resolution of CELOG */
1087 1089 dimm->mtype = MEM_RDDR; /* only one type supported */
1088 1090 dimm->dtype = mem_dev ? DEV_X4 : DEV_X8;
drivers/edac/e7xxx_edac.c
... ... @@ -349,7 +349,7 @@
349 349 unsigned long last_cumul_size;
350 350 int index, j;
351 351 u8 value;
352   - u32 dra, cumul_size;
  352 + u32 dra, cumul_size, nr_pages;
353 353 int drc_chan, drc_drbg, drc_ddim, mem_dev;
354 354 struct csrow_info *csrow;
355 355 struct dimm_info *dimm;
356 356  
... ... @@ -380,12 +380,13 @@
380 380  
381 381 csrow->first_page = last_cumul_size;
382 382 csrow->last_page = cumul_size - 1;
383   - csrow->nr_pages = cumul_size - last_cumul_size;
  383 + nr_pages = cumul_size - last_cumul_size;
384 384 last_cumul_size = cumul_size;
385 385  
386 386 for (j = 0; j < drc_chan + 1; j++) {
387 387 dimm = csrow->channels[j].dimm;
388 388  
  389 + dimm->nr_pages = nr_pages / (drc_chan + 1);
389 390 dimm->grain = 1 << 12; /* 4KiB - resolution of CELOG */
390 391 dimm->mtype = MEM_RDDR; /* only one type supported */
391 392 dimm->dtype = mem_dev ? DEV_X4 : DEV_X8;
drivers/edac/edac_mc.c
... ... @@ -43,9 +43,10 @@
43 43 {
44 44 debugf4("\tchannel = %p\n", chan);
45 45 debugf4("\tchannel->chan_idx = %d\n", chan->chan_idx);
46   - debugf4("\tchannel->ce_count = %d\n", chan->dimm->ce_count);
47   - debugf4("\tchannel->label = '%s'\n", chan->dimm->label);
48 46 debugf4("\tchannel->csrow = %p\n\n", chan->csrow);
  47 + debugf4("\tdimm->ce_count = %d\n", chan->dimm->ce_count);
  48 + debugf4("\tdimm->label = '%s'\n", chan->dimm->label);
  49 + debugf4("\tdimm->nr_pages = 0x%x\n", chan->dimm->nr_pages);
49 50 }
50 51  
51 52 static void edac_mc_dump_csrow(struct csrow_info *csrow)
... ... @@ -55,7 +56,6 @@
55 56 debugf4("\tcsrow->first_page = 0x%lx\n", csrow->first_page);
56 57 debugf4("\tcsrow->last_page = 0x%lx\n", csrow->last_page);
57 58 debugf4("\tcsrow->page_mask = 0x%lx\n", csrow->page_mask);
58   - debugf4("\tcsrow->nr_pages = 0x%x\n", csrow->nr_pages);
59 59 debugf4("\tcsrow->nr_channels = %d\n", csrow->nr_channels);
60 60 debugf4("\tcsrow->channels = %p\n", csrow->channels);
61 61 debugf4("\tcsrow->mci = %p\n\n", csrow->mci);
62 62  
... ... @@ -652,15 +652,19 @@
652 652 int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page)
653 653 {
654 654 struct csrow_info *csrows = mci->csrows;
655   - int row, i;
  655 + int row, i, j, n;
656 656  
657 657 debugf1("MC%d: %s(): 0x%lx\n", mci->mc_idx, __func__, page);
658 658 row = -1;
659 659  
660 660 for (i = 0; i < mci->nr_csrows; i++) {
661 661 struct csrow_info *csrow = &csrows[i];
662   -
663   - if (csrow->nr_pages == 0)
  662 + n = 0;
  663 + for (j = 0; j < csrow->nr_channels; j++) {
  664 + struct dimm_info *dimm = csrow->channels[j].dimm;
  665 + n += dimm->nr_pages;
  666 + }
  667 + if (n == 0)
664 668 continue;
665 669  
666 670 debugf3("MC%d: %s(): first(0x%lx) page(0x%lx) last(0x%lx) "
drivers/edac/edac_mc_sysfs.c
... ... @@ -144,7 +144,13 @@
144 144 static ssize_t csrow_size_show(struct csrow_info *csrow, char *data,
145 145 int private)
146 146 {
147   - return sprintf(data, "%u\n", PAGES_TO_MiB(csrow->nr_pages));
  147 + int i;
  148 + u32 nr_pages = 0;
  149 +
  150 + for (i = 0; i < csrow->nr_channels; i++)
  151 + nr_pages += csrow->channels[i].dimm->nr_pages;
  152 +
  153 + return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages));
148 154 }
149 155  
150 156 static ssize_t csrow_mem_type_show(struct csrow_info *csrow, char *data,
151 157  
152 158  
153 159  
... ... @@ -519,16 +525,16 @@
519 525  
520 526 static ssize_t mci_size_mb_show(struct mem_ctl_info *mci, char *data)
521 527 {
522   - int total_pages, csrow_idx;
  528 + int total_pages = 0, csrow_idx, j;
523 529  
524   - for (total_pages = csrow_idx = 0; csrow_idx < mci->nr_csrows;
525   - csrow_idx++) {
  530 + for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) {
526 531 struct csrow_info *csrow = &mci->csrows[csrow_idx];
527 532  
528   - if (!csrow->nr_pages)
529   - continue;
  533 + for (j = 0; j < csrow->nr_channels; j++) {
  534 + struct dimm_info *dimm = csrow->channels[j].dimm;
530 535  
531   - total_pages += csrow->nr_pages;
  536 + total_pages += dimm->nr_pages;
  537 + }
532 538 }
533 539  
534 540 return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages));
... ... @@ -900,7 +906,7 @@
900 906 */
901 907 int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
902 908 {
903   - int i;
  909 + int i, j;
904 910 int err;
905 911 struct csrow_info *csrow;
906 912 struct kobject *kobj_mci = &mci->edac_mci_kobj;
907 913  
908 914  
... ... @@ -934,10 +940,13 @@
934 940 /* Make directories for each CSROW object under the mc<id> kobject
935 941 */
936 942 for (i = 0; i < mci->nr_csrows; i++) {
  943 + int nr_pages = 0;
  944 +
937 945 csrow = &mci->csrows[i];
  946 + for (j = 0; j < csrow->nr_channels; j++)
  947 + nr_pages += csrow->channels[j].dimm->nr_pages;
938 948  
939   - /* Only expose populated CSROWs */
940   - if (csrow->nr_pages > 0) {
  949 + if (nr_pages > 0) {
941 950 err = edac_create_csrow_object(mci, csrow, i);
942 951 if (err) {
943 952 debugf1("%s() failure: create csrow %d obj\n",
944 953  
... ... @@ -949,10 +958,14 @@
949 958  
950 959 return 0;
951 960  
952   - /* CSROW error: backout what has already been registered, */
953 961 fail1:
954 962 for (i--; i >= 0; i--) {
955   - if (mci->csrows[i].nr_pages > 0)
  963 + int nr_pages = 0;
  964 +
  965 + csrow = &mci->csrows[i];
  966 + for (j = 0; j < csrow->nr_channels; j++)
  967 + nr_pages += csrow->channels[j].dimm->nr_pages;
  968 + if (nr_pages > 0)
956 969 kobject_put(&mci->csrows[i].kobj);
957 970 }
958 971  
959 972  
... ... @@ -972,14 +985,20 @@
972 985 */
973 986 void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
974 987 {
975   - int i;
  988 + struct csrow_info *csrow;
  989 + int i, j;
976 990  
977 991 debugf0("%s()\n", __func__);
978 992  
979 993 /* remove all csrow kobjects */
980 994 debugf4("%s() unregister this mci kobj\n", __func__);
981 995 for (i = 0; i < mci->nr_csrows; i++) {
982   - if (mci->csrows[i].nr_pages > 0) {
  996 + int nr_pages = 0;
  997 +
  998 + csrow = &mci->csrows[i];
  999 + for (j = 0; j < csrow->nr_channels; j++)
  1000 + nr_pages += csrow->channels[j].dimm->nr_pages;
  1001 + if (nr_pages > 0) {
983 1002 debugf0("%s() unreg csrow-%d\n", __func__, i);
984 1003 kobject_put(&mci->csrows[i].kobj);
985 1004 }
drivers/edac/i3000_edac.c
... ... @@ -306,7 +306,7 @@
306 306 int rc;
307 307 int i, j;
308 308 struct mem_ctl_info *mci = NULL;
309   - unsigned long last_cumul_size;
  309 + unsigned long last_cumul_size, nr_pages;
310 310 int interleaved, nr_channels;
311 311 unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS];
312 312 unsigned char *c0dra = dra, *c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2];
313 313  
... ... @@ -391,11 +391,13 @@
391 391  
392 392 csrow->first_page = last_cumul_size;
393 393 csrow->last_page = cumul_size - 1;
394   - csrow->nr_pages = cumul_size - last_cumul_size;
  394 + nr_pages = cumul_size - last_cumul_size;
395 395 last_cumul_size = cumul_size;
396 396  
397 397 for (j = 0; j < nr_channels; j++) {
398 398 struct dimm_info *dimm = csrow->channels[j].dimm;
  399 +
  400 + dimm->nr_pages = nr_pages / nr_channels;
399 401 dimm->grain = I3000_DEAP_GRAIN;
400 402 dimm->mtype = MEM_DDR2;
401 403 dimm->dtype = DEV_UNKNOWN;
drivers/edac/i3200_edac.c
... ... @@ -376,11 +376,10 @@
376 376 if (nr_pages == 0)
377 377 continue;
378 378  
379   - csrow->nr_pages = nr_pages;
380   -
381 379 for (j = 0; j < nr_channels; j++) {
382 380 struct dimm_info *dimm = csrow->channels[j].dimm;
383 381  
  382 + dimm->nr_pages = nr_pages / nr_channels;
384 383 dimm->grain = nr_pages << PAGE_SHIFT;
385 384 dimm->mtype = MEM_DDR2;
386 385 dimm->dtype = DEV_UNKNOWN;
drivers/edac/i5000_edac.c
... ... @@ -1236,6 +1236,7 @@
1236 1236 {
1237 1237 struct i5000_pvt *pvt;
1238 1238 struct csrow_info *p_csrow;
  1239 + struct dimm_info *dimm;
1239 1240 int empty, channel_count;
1240 1241 int max_csrows;
1241 1242 int mtr, mtr1;
1242 1243  
1243 1244  
1244 1245  
1245 1246  
1246 1247  
1247 1248  
... ... @@ -1265,21 +1266,22 @@
1265 1266  
1266 1267 csrow_megs = 0;
1267 1268 for (channel = 0; channel < pvt->maxch; channel++) {
  1269 + dimm = p_csrow->channels[channel].dimm;
1268 1270 csrow_megs += pvt->dimm_info[csrow][channel].megabytes;
1269   - p_csrow->channels[channel].dimm->grain = 8;
  1271 + dimm->grain = 8;
1270 1272  
1271 1273 /* Assume DDR2 for now */
1272   - p_csrow->channels[channel].dimm->mtype = MEM_FB_DDR2;
  1274 + dimm->mtype = MEM_FB_DDR2;
1273 1275  
1274 1276 /* ask what device type on this row */
1275 1277 if (MTR_DRAM_WIDTH(mtr))
1276   - p_csrow->channels[channel].dimm->dtype = DEV_X8;
  1278 + dimm->dtype = DEV_X8;
1277 1279 else
1278   - p_csrow->channels[channel].dimm->dtype = DEV_X4;
  1280 + dimm->dtype = DEV_X4;
1279 1281  
1280   - p_csrow->channels[channel].dimm->edac_mode = EDAC_S8ECD8ED;
  1282 + dimm->edac_mode = EDAC_S8ECD8ED;
  1283 + dimm->nr_pages = (csrow_megs << 8) / pvt->maxch;
1281 1284 }
1282   - p_csrow->nr_pages = csrow_megs << 8;
1283 1285  
1284 1286 empty = 0;
1285 1287 }
drivers/edac/i5100_edac.c
... ... @@ -859,7 +859,6 @@
859 859 * FIXME: these two are totally bogus -- I don't see how to
860 860 * map them correctly to this structure...
861 861 */
862   - mci->csrows[i].nr_pages = npages;
863 862 mci->csrows[i].csrow_idx = i;
864 863 mci->csrows[i].mci = mci;
865 864 mci->csrows[i].nr_channels = 1;
... ... @@ -867,14 +866,19 @@
867 866 total_pages += npages;
868 867  
869 868 dimm = mci->csrows[i].channels[0].dimm;
870   - dimm->grain = 32;
871   - dimm->dtype = (priv->mtr[chan][rank].width == 4) ?
872   - DEV_X4 : DEV_X8;
873   - dimm->mtype = MEM_RDDR2;
874   - dimm->edac_mode = EDAC_SECDED;
875   - snprintf(dimm->label, sizeof(dimm->label),
876   - "DIMM%u",
877   - i5100_rank_to_slot(mci, chan, rank));
  869 + dimm->nr_pages = npages;
  870 + if (npages) {
  871 + total_pages += npages;
  872 +
  873 + dimm->grain = 32;
  874 + dimm->dtype = (priv->mtr[chan][rank].width == 4) ?
  875 + DEV_X4 : DEV_X8;
  876 + dimm->mtype = MEM_RDDR2;
  877 + dimm->edac_mode = EDAC_SECDED;
  878 + snprintf(dimm->label, sizeof(dimm->label),
  879 + "DIMM%u",
  880 + i5100_rank_to_slot(mci, chan, rank));
  881 + }
878 882 }
879 883 }
880 884  
drivers/edac/i5400_edac.c
... ... @@ -1156,7 +1156,7 @@
1156 1156 int empty, channel_count;
1157 1157 int max_csrows;
1158 1158 int mtr;
1159   - int csrow_megs;
  1159 + int size_mb;
1160 1160 int channel;
1161 1161 int csrow;
1162 1162 struct dimm_info *dimm;
... ... @@ -1171,8 +1171,6 @@
1171 1171 for (csrow = 0; csrow < max_csrows; csrow++) {
1172 1172 p_csrow = &mci->csrows[csrow];
1173 1173  
1174   - p_csrow->csrow_idx = csrow;
1175   -
1176 1174 /* use branch 0 for the basis */
1177 1175 mtr = determine_mtr(pvt, csrow, 0);
1178 1176  
1179 1177  
1180 1178  
1181 1179  
... ... @@ -1180,12 +1178,11 @@
1180 1178 if (!MTR_DIMMS_PRESENT(mtr))
1181 1179 continue;
1182 1180  
1183   - csrow_megs = 0;
1184 1181 for (channel = 0; channel < pvt->maxch; channel++) {
1185   - csrow_megs += pvt->dimm_info[csrow][channel].megabytes;
  1182 + size_mb = pvt->dimm_info[csrow][channel].megabytes;
1186 1183  
1187   - p_csrow->nr_pages = csrow_megs << 8;
1188 1184 dimm = p_csrow->channels[channel].dimm;
  1185 + dimm->nr_pages = size_mb << 8;
1189 1186 dimm->grain = 8;
1190 1187 dimm->dtype = MTR_DRAM_WIDTH(mtr) ? DEV_X8 : DEV_X4;
1191 1188 dimm->mtype = MEM_RDDR2;
drivers/edac/i7300_edac.c
... ... @@ -617,9 +617,7 @@
617 617 static int decode_mtr(struct i7300_pvt *pvt,
618 618 int slot, int ch, int branch,
619 619 struct i7300_dimm_info *dinfo,
620   - struct csrow_info *p_csrow,
621   - struct dimm_info *dimm,
622   - u32 *nr_pages)
  620 + struct dimm_info *dimm)
623 621 {
624 622 int mtr, ans, addrBits, channel;
625 623  
... ... @@ -651,7 +649,6 @@
651 649 addrBits -= 3; /* 8 bits per bytes */
652 650  
653 651 dinfo->megabytes = 1 << addrBits;
654   - *nr_pages = dinfo->megabytes << 8;
655 652  
656 653 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
657 654  
... ... @@ -664,8 +661,6 @@
664 661 debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
665 662 debugf2("\t\tSIZE: %d MB\n", dinfo->megabytes);
666 663  
667   - p_csrow->csrow_idx = slot;
668   -
669 664 /*
670 665 * The type of error detection actually depends of the
671 666 * mode of operation. When it is just one single memory chip, at
... ... @@ -675,6 +670,7 @@
675 670 * See datasheet Sections 7.3.6 to 7.3.8
676 671 */
677 672  
  673 + dimm->nr_pages = MiB_TO_PAGES(dinfo->megabytes);
678 674 dimm->grain = 8;
679 675 dimm->mtype = MEM_FB_DDR2;
680 676 if (IS_SINGLE_MODE(pvt->mc_settings_a)) {
681 677  
... ... @@ -774,11 +770,9 @@
774 770 {
775 771 struct i7300_pvt *pvt;
776 772 struct i7300_dimm_info *dinfo;
777   - struct csrow_info *p_csrow;
778 773 int rc = -ENODEV;
779 774 int mtr;
780 775 int ch, branch, slot, channel;
781   - u32 nr_pages;
782 776 struct dimm_info *dimm;
783 777  
784 778 pvt = mci->pvt_info;
... ... @@ -804,7 +798,6 @@
804 798 }
805 799  
806 800 /* Get the set of MTR[0-7] regs by each branch */
807   - nr_pages = 0;
808 801 for (slot = 0; slot < MAX_SLOTS; slot++) {
809 802 int where = mtr_regs[slot];
810 803 for (branch = 0; branch < MAX_BRANCHES; branch++) {
811 804  
812 805  
813 806  
814 807  
... ... @@ -815,21 +808,18 @@
815 808 int channel = to_channel(ch, branch);
816 809  
817 810 dinfo = &pvt->dimm_info[slot][channel];
818   - p_csrow = &mci->csrows[slot];
819 811  
820   - dimm = p_csrow->channels[branch * MAX_CH_PER_BRANCH + ch].dimm;
  812 + dimm = mci->csrows[slot].channels[branch * MAX_CH_PER_BRANCH + ch].dimm;
821 813  
822 814 mtr = decode_mtr(pvt, slot, ch, branch,
823   - dinfo, p_csrow, dimm,
824   - &nr_pages);
  815 + dinfo, dimm);
  816 +
825 817 /* if no DIMMS on this row, continue */
826 818 if (!MTR_DIMMS_PRESENT(mtr))
827 819 continue;
828 820  
829   - /* Update per_csrow memory count */
830   - p_csrow->nr_pages += nr_pages;
831   -
832 821 rc = 0;
  822 +
833 823 }
834 824 }
835 825 }
drivers/edac/i7core_edac.c
... ... @@ -715,17 +715,12 @@
715 715 npages = MiB_TO_PAGES(size);
716 716  
717 717 csr = &mci->csrows[csrow];
718   - csr->nr_pages = npages;
719 718  
720   - csr->csrow_idx = csrow;
721   - csr->nr_channels = 1;
722   -
723   - csr->channels[0].chan_idx = i;
724   - csr->channels[0].ce_count = 0;
725   -
726 719 pvt->csrow_map[i][j] = csrow;
727 720  
728 721 dimm = csr->channels[0].dimm;
  722 + dimm->nr_pages = npages;
  723 +
729 724 switch (banks) {
730 725 case 4:
731 726 dimm->dtype = DEV_X4;
... ... @@ -746,6 +741,7 @@
746 741 dimm->grain = 8;
747 742 dimm->edac_mode = mode;
748 743 dimm->mtype = mtype;
  744 + csrow++;
749 745 }
750 746  
751 747 pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
drivers/edac/i82443bxgx_edac.c
... ... @@ -220,7 +220,7 @@
220 220 row_base = row_high_limit_last;
221 221 csrow->first_page = row_base >> PAGE_SHIFT;
222 222 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
223   - csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
  223 + dimm->nr_pages = csrow->last_page - csrow->first_page + 1;
224 224 /* EAP reports in 4kilobyte granularity [61] */
225 225 dimm->grain = 1 << 12;
226 226 dimm->mtype = mtype;
drivers/edac/i82860_edac.c
... ... @@ -167,7 +167,7 @@
167 167  
168 168 csrow->first_page = last_cumul_size;
169 169 csrow->last_page = cumul_size - 1;
170   - csrow->nr_pages = cumul_size - last_cumul_size;
  170 + dimm->nr_pages = cumul_size - last_cumul_size;
171 171 last_cumul_size = cumul_size;
172 172 dimm->grain = 1 << 12; /* I82860_EAP has 4KiB reolution */
173 173 dimm->mtype = MEM_RMBS;
drivers/edac/i82875p_edac.c
... ... @@ -347,7 +347,7 @@
347 347 unsigned long last_cumul_size;
348 348 u8 value;
349 349 u32 drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
350   - u32 cumul_size;
  350 + u32 cumul_size, nr_pages;
351 351 int index, j;
352 352  
353 353 drc_ddim = (drc >> 18) & 0x1;
354 354  
... ... @@ -371,12 +371,13 @@
371 371  
372 372 csrow->first_page = last_cumul_size;
373 373 csrow->last_page = cumul_size - 1;
374   - csrow->nr_pages = cumul_size - last_cumul_size;
  374 + nr_pages = cumul_size - last_cumul_size;
375 375 last_cumul_size = cumul_size;
376 376  
377 377 for (j = 0; j < nr_chans; j++) {
378 378 dimm = csrow->channels[j].dimm;
379 379  
  380 + dimm->nr_pages = nr_pages / nr_chans;
380 381 dimm->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
381 382 dimm->mtype = MEM_DDR;
382 383 dimm->dtype = DEV_UNKNOWN;
drivers/edac/i82975x_edac.c
... ... @@ -370,7 +370,7 @@
370 370 struct csrow_info *csrow;
371 371 unsigned long last_cumul_size;
372 372 u8 value;
373   - u32 cumul_size;
  373 + u32 cumul_size, nr_pages;
374 374 int index, chan;
375 375 struct dimm_info *dimm;
376 376 enum dev_type dtype;
... ... @@ -402,6 +402,7 @@
402 402 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
403 403 cumul_size);
404 404  
  405 + nr_pages = cumul_size - last_cumul_size;
405 406 /*
406 407 * Initialise dram labels
407 408 * index values:
... ... @@ -411,6 +412,11 @@
411 412 dtype = i82975x_dram_type(mch_window, index);
412 413 for (chan = 0; chan < csrow->nr_channels; chan++) {
413 414 dimm = mci->csrows[index].channels[chan].dimm;
  415 +
  416 + if (!nr_pages)
  417 + continue;
  418 +
  419 + dimm->nr_pages = nr_pages / csrow->nr_channels;
414 420 strncpy(csrow->channels[chan].dimm->label,
415 421 labels[(index >> 1) + (chan * 2)],
416 422 EDAC_MC_LABEL_LEN);
417 423  
... ... @@ -420,12 +426,11 @@
420 426 dimm->edac_mode = EDAC_SECDED; /* only supported */
421 427 }
422 428  
423   - if (cumul_size == last_cumul_size)
  429 + if (!nr_pages)
424 430 continue; /* not populated */
425 431  
426 432 csrow->first_page = last_cumul_size;
427 433 csrow->last_page = cumul_size - 1;
428   - csrow->nr_pages = cumul_size - last_cumul_size;
429 434 last_cumul_size = cumul_size;
430 435 }
431 436 }
drivers/edac/mpc85xx_edac.c
... ... @@ -947,7 +947,8 @@
947 947  
948 948 csrow->first_page = start;
949 949 csrow->last_page = end;
950   - csrow->nr_pages = end + 1 - start;
  950 +
  951 + dimm->nr_pages = end + 1 - start;
951 952 dimm->grain = 8;
952 953 dimm->mtype = mtype;
953 954 dimm->dtype = DEV_UNKNOWN;
drivers/edac/mv64x60_edac.c
... ... @@ -667,7 +667,8 @@
667 667  
668 668 csrow = &mci->csrows[0];
669 669 dimm = csrow->channels[0].dimm;
670   - csrow->nr_pages = pdata->total_mem >> PAGE_SHIFT;
  670 +
  671 + dimm->nr_pages = pdata->total_mem >> PAGE_SHIFT;
671 672 dimm->grain = 8;
672 673  
673 674 dimm->mtype = (ctl & MV64X60_SDRAM_REGISTERED) ? MEM_RDDR : MEM_DDR;
drivers/edac/pasemi_edac.c
... ... @@ -153,20 +153,20 @@
153 153 switch ((rankcfg & MCDRAM_RANKCFG_TYPE_SIZE_M) >>
154 154 MCDRAM_RANKCFG_TYPE_SIZE_S) {
155 155 case 0:
156   - csrow->nr_pages = 128 << (20 - PAGE_SHIFT);
  156 + dimm->nr_pages = 128 << (20 - PAGE_SHIFT);
157 157 break;
158 158 case 1:
159   - csrow->nr_pages = 256 << (20 - PAGE_SHIFT);
  159 + dimm->nr_pages = 256 << (20 - PAGE_SHIFT);
160 160 break;
161 161 case 2:
162 162 case 3:
163   - csrow->nr_pages = 512 << (20 - PAGE_SHIFT);
  163 + dimm->nr_pages = 512 << (20 - PAGE_SHIFT);
164 164 break;
165 165 case 4:
166   - csrow->nr_pages = 1024 << (20 - PAGE_SHIFT);
  166 + dimm->nr_pages = 1024 << (20 - PAGE_SHIFT);
167 167 break;
168 168 case 5:
169   - csrow->nr_pages = 2048 << (20 - PAGE_SHIFT);
  169 + dimm->nr_pages = 2048 << (20 - PAGE_SHIFT);
170 170 break;
171 171 default:
172 172 edac_mc_printk(mci, KERN_ERR,
... ... @@ -176,8 +176,8 @@
176 176 }
177 177  
178 178 csrow->first_page = last_page_in_mmc;
179   - csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
180   - last_page_in_mmc += csrow->nr_pages;
  179 + csrow->last_page = csrow->first_page + dimm->nr_pages - 1;
  180 + last_page_in_mmc += dimm->nr_pages;
181 181 csrow->page_mask = 0;
182 182 dimm->grain = PASEMI_EDAC_ERROR_GRAIN;
183 183 dimm->mtype = MEM_DDR;
drivers/edac/ppc4xx_edac.c
... ... @@ -896,7 +896,7 @@
896 896 enum dev_type dtype;
897 897 enum edac_type edac_mode;
898 898 int row, j;
899   - u32 mbxcf, size;
  899 + u32 mbxcf, size, nr_pages;
900 900  
901 901 /* Establish the memory type and width */
902 902  
... ... @@ -947,7 +947,7 @@
947 947 case SDRAM_MBCF_SZ_2GB:
948 948 case SDRAM_MBCF_SZ_4GB:
949 949 case SDRAM_MBCF_SZ_8GB:
950   - csi->nr_pages = SDRAM_MBCF_SZ_TO_PAGES(size);
  950 + nr_pages = SDRAM_MBCF_SZ_TO_PAGES(size);
951 951 break;
952 952 default:
953 953 ppc4xx_edac_mc_printk(KERN_ERR, mci,
... ... @@ -973,6 +973,7 @@
973 973 for (j = 0; j < csi->nr_channels; j++) {
974 974 struct dimm_info *dimm = csi->channels[j].dimm;
975 975  
  976 + dimm->nr_pages = nr_pages / csi->nr_channels;
976 977 dimm->grain = 1;
977 978  
978 979 dimm->mtype = mtype;
drivers/edac/r82600_edac.c
... ... @@ -249,7 +249,8 @@
249 249  
250 250 csrow->first_page = row_base >> PAGE_SHIFT;
251 251 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
252   - csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
  252 +
  253 + dimm->nr_pages = csrow->last_page - csrow->first_page + 1;
253 254 /* Error address is top 19 bits - so granularity is *
254 255 * 14 bits */
255 256 dimm->grain = 1 << 14;
drivers/edac/sb_edac.c
... ... @@ -561,7 +561,6 @@
561 561 u32 reg;
562 562 enum edac_type mode;
563 563 enum mem_type mtype;
564   - struct dimm_info *dimm;
565 564  
566 565 pci_read_config_dword(pvt->pci_br, SAD_TARGET, &reg);
567 566 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
568 567  
... ... @@ -613,11 +612,11 @@
613 612 /* On all supported DDR3 DIMM types, there are 8 banks available */
614 613 banks = 8;
615 614  
616   - dimm = mci->dimms;
617 615 for (i = 0; i < NUM_CHANNELS; i++) {
618 616 u32 mtr;
619 617  
620 618 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
  619 + struct dimm_info *dimm = &mci->dimms[j];
621 620 pci_read_config_dword(pvt->pci_tad[i],
622 621 mtr_regs[j], &mtr);
623 622 debugf4("Channel #%d MTR%d = %x\n", i, j, mtr);
624 623  
... ... @@ -642,15 +641,12 @@
642 641 * csrows.
643 642 */
644 643 csr = &mci->csrows[csrow];
645   - csr->nr_pages = npages;
646   - csr->csrow_idx = csrow;
647   - csr->nr_channels = 1;
648   - csr->channels[0].chan_idx = i;
649 644 pvt->csrow_map[i][j] = csrow;
650 645 last_page += npages;
651 646 csrow++;
652 647  
653 648 csr->channels[0].dimm = dimm;
  649 + dimm->nr_pages = npages;
654 650 dimm->grain = 32;
655 651 dimm->dtype = (banks == 8) ? DEV_X8 : DEV_X4;
656 652 dimm->mtype = mtype;
drivers/edac/tile_edac.c
... ... @@ -110,7 +110,7 @@
110 110 return -1;
111 111 }
112 112  
113   - csrow->nr_pages = mem_info.mem_size >> PAGE_SHIFT;
  113 + dimm->nr_pages = mem_info.mem_size >> PAGE_SHIFT;
114 114 dimm->grain = TILE_EDAC_ERROR_GRAIN;
115 115 dimm->dtype = DEV_UNKNOWN;
116 116  
drivers/edac/x38_edac.c
... ... @@ -373,10 +373,10 @@
373 373 if (nr_pages == 0)
374 374 continue;
375 375  
376   - csrow->nr_pages = nr_pages;
377   -
378 376 for (j = 0; j < x38_channel_num; j++) {
379 377 struct dimm_info *dimm = csrow->channels[j].dimm;
  378 +
  379 + dimm->nr_pages = nr_pages / x38_channel_num;
380 380 dimm->grain = nr_pages << PAGE_SHIFT;
381 381 dimm->mtype = MEM_DDR2;
382 382 dimm->dtype = DEV_UNKNOWN;
include/linux/edac.h
... ... @@ -324,6 +324,8 @@
324 324 enum mem_type mtype; /* memory dimm type */
325 325 enum edac_type edac_mode; /* EDAC mode for this dimm */
326 326  
  327 + u32 nr_pages; /* number of pages in csrow */
  328 +
327 329 u32 ce_count; /* Correctable Errors for this dimm */
328 330 };
329 331  
330 332  
331 333  
... ... @@ -350,12 +352,12 @@
350 352 };
351 353  
352 354 struct csrow_info {
  355 + /* Used only by edac_mc_find_csrow_by_page() */
353 356 unsigned long first_page; /* first page number in csrow */
354 357 unsigned long last_page; /* last page number in csrow */
355   - u32 nr_pages; /* number of pages in csrow */
356 358 unsigned long page_mask; /* used for interleaving -
357   - * 0UL for non intlv
358   - */
  359 + * 0UL for non intlv */
  360 +
359 361 int csrow_idx; /* the chip-select row */
360 362  
361 363 u32 ue_count; /* Uncorrectable Errors for this csrow */