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Commit a94f8ecb2f778f92deb1d3633426a70e1fcf56db

Authored by Shawn Guo
1 parent 5da826abe9
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

ARM: imx6q: remove board specific CLKO setup 

The CLKO is widely used by imx6q board designs to clock audio codec.
Since most codecs accept 24 MHz frequency, let's initially set up CLKO
with OSC24M (cko <-- cko2 <-- osc).  Then those board specific CLKO
setup for audio codec can be removed.

The board dts files also need an update on cko reference in codec node.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Showing 5 changed files with 14 additions and 72 deletions Side-by-side Diff

arch/arm/boot/dts/imx6q-sabrelite.dts
Diff comments   View file @ a94f8ec
... ... @@ -167,7 +167,7 @@
167 167 codec: sgtl5000@0a {
168 168 compatible = "fsl,sgtl5000";
169 169 reg = <0x0a>;
170   - clocks = <&clks 169>;
  170 + clocks = <&clks 201>;
171 171 VDDA-supply = <&reg_2p5v>;
172 172 VDDIO-supply = <&reg_3p3v>;
173 173 };
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
Diff comments   View file @ a94f8ec
... ... @@ -109,7 +109,7 @@
109 109 codec: wm8962@1a {
110 110 compatible = "wlf,wm8962";
111 111 reg = <0x1a>;
112   - clocks = <&clks 169>;
  112 + clocks = <&clks 201>;
113 113 DCVDD-supply = <&reg_audio>;
114 114 DBVDD-supply = <&reg_audio>;
115 115 AVDD-supply = <&reg_audio>;
arch/arm/boot/dts/imx6qdl-wandboard.dtsi
Diff comments   View file @ a94f8ec
... ... @@ -60,7 +60,7 @@
60 60 codec: sgtl5000@0a {
61 61 compatible = "fsl,sgtl5000";
62 62 reg = <0x0a>;
63   - clocks = <&clks 169>;
  63 + clocks = <&clks 201>;
64 64 VDDA-supply = <&reg_2p5v>;
65 65 VDDIO-supply = <&reg_3p3v>;
66 66 };
arch/arm/mach-imx/clk-imx6q.c
Diff comments   View file @ a94f8ec
... ... @@ -288,6 +288,7 @@
288 288 struct device_node *np;
289 289 void __iomem *base;
290 290 int i, irq;
  291 + int ret;
291 292  
292 293 clk[dummy] = imx_clk_fixed("dummy", 0);
293 294 clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
... ... @@ -591,6 +592,16 @@
591 592 clk_prepare_enable(clk[usbphy1_gate]);
592 593 clk_prepare_enable(clk[usbphy2_gate]);
593 594 }
  595 +
  596 + /*
  597 + * Let's initially set up CLKO with OSC24M, since this configuration
  598 + * is widely used by imx6q board designs to clock audio codec.
  599 + */
  600 + ret = clk_set_parent(clk[cko2_sel], clk[osc]);
  601 + if (!ret)
  602 + ret = clk_set_parent(clk[cko], clk[cko2]);
  603 + if (ret)
  604 + pr_warn("failed to set up CLKO: %d\n", ret);
594 605  
595 606 /* Set initial power mode */
596 607 imx6q_set_lpm(WAIT_CLOCKED);
arch/arm/mach-imx/mach-imx6q.c
Diff comments   View file @ a94f8ec
... ... @@ -162,30 +162,6 @@
162 162 return 0;
163 163 }
164 164  
165   -static void __init imx6q_sabrelite_cko1_setup(void)
166   -{
167   - struct clk *cko1_sel, *ahb, *cko1;
168   - unsigned long rate;
169   -
170   - cko1_sel = clk_get_sys(NULL, "cko1_sel");
171   - ahb = clk_get_sys(NULL, "ahb");
172   - cko1 = clk_get_sys(NULL, "cko1");
173   - if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
174   - pr_err("cko1 setup failed!\n");
175   - goto put_clk;
176   - }
177   - clk_set_parent(cko1_sel, ahb);
178   - rate = clk_round_rate(cko1, 16000000);
179   - clk_set_rate(cko1, rate);
180   -put_clk:
181   - if (!IS_ERR(cko1_sel))
182   - clk_put(cko1_sel);
183   - if (!IS_ERR(ahb))
184   - clk_put(ahb);
185   - if (!IS_ERR(cko1))
186   - clk_put(cko1);
187   -}
188   -
189 165 #define PHY_ID_AR8031 0x004dd074
190 166  
191 167 static void __init imx6q_enet_phy_init(void)
... ... @@ -200,45 +176,6 @@
200 176 }
201 177 }
202 178  
203   -static void __init imx6q_sabresd_cko1_setup(void)
204   -{
205   - struct clk *cko1_sel, *pll4, *pll4_post, *cko1;
206   - unsigned long rate;
207   -
208   - cko1_sel = clk_get_sys(NULL, "cko1_sel");
209   - pll4 = clk_get_sys(NULL, "pll4_audio");
210   - pll4_post = clk_get_sys(NULL, "pll4_post_div");
211   - cko1 = clk_get_sys(NULL, "cko1");
212   - if (IS_ERR(cko1_sel) || IS_ERR(pll4)
213   - || IS_ERR(pll4_post) || IS_ERR(cko1)) {
214   - pr_err("cko1 setup failed!\n");
215   - goto put_clk;
216   - }
217   - /*
218   - * Setting pll4 at 768MHz (24MHz * 32)
219   - * So its child clock can get 24MHz easily
220   - */
221   - clk_set_rate(pll4, 768000000);
222   -
223   - clk_set_parent(cko1_sel, pll4_post);
224   - rate = clk_round_rate(cko1, 24000000);
225   - clk_set_rate(cko1, rate);
226   -put_clk:
227   - if (!IS_ERR(cko1_sel))
228   - clk_put(cko1_sel);
229   - if (!IS_ERR(pll4_post))
230   - clk_put(pll4_post);
231   - if (!IS_ERR(pll4))
232   - clk_put(pll4);
233   - if (!IS_ERR(cko1))
234   - clk_put(cko1);
235   -}
236   -
237   -static void __init imx6q_sabresd_init(void)
238   -{
239   - imx6q_sabresd_cko1_setup();
240   -}
241   -
242 179 static void __init imx6q_1588_init(void)
243 180 {
244 181 struct regmap *gpr;
... ... @@ -255,12 +192,6 @@
255 192  
256 193 static void __init imx6q_init_machine(void)
257 194 {
258   - if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
259   - imx6q_sabrelite_cko1_setup();
260   - else if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
261   - of_machine_is_compatible("fsl,imx6dl-sabresd"))
262   - imx6q_sabresd_init();
263   -
264 195 imx6q_enet_phy_init();
265 196  
266 197 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);