[PATCH] ia64/sn __iomem annotations

Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>

[PATCH] ia64/sn __iomem annotations
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Al Viro · Linus Torvalds
1 parent cfa7fd72ca
Showing 5 changed files with 26 additions and 26 deletions Side-by-side Diff
arch/ia64/sn/pci/pcibr/pcibr_ate.c
arch/ia64/sn/pci/tioce_provider.c
include/asm-ia64/sn/pcibr_provider.h
include/asm-ia64/sn/tioca_provider.h
include/asm-ia64/sn/tioce_provider.h
@@ -126,7 +126,7 @@
  * Setup an Address Translation Entry as specified.  Use either the Bridge
  * internal maps or the external map RAM, as appropriate.
  */
-static inline u64 *pcibr_ate_addr(struct pcibus_info *pcibus_info,
+static inline u64 __iomem *pcibr_ate_addr(struct pcibus_info *pcibus_info,
 				       int ate_index)
 {
 	if (ate_index < pcibus_info->pbi_int_ate_size) {
@@ -53,7 +53,7 @@
  */
  
 static void inline
-tioce_mmr_war_pre(struct tioce_kernel *kern, void *mmr_addr)
+tioce_mmr_war_pre(struct tioce_kernel *kern, void __iomem *mmr_addr)
 {
 	u64 mmr_base;
 	u64 mmr_offset;
@@ -62,7 +62,7 @@
 		return;
  
 	mmr_base = kern->ce_common->ce_pcibus.bs_base;
-	mmr_offset = (u64)mmr_addr - mmr_base;
+	mmr_offset = (unsigned long)mmr_addr - mmr_base;
  
 	if (mmr_offset < 0x45000) {
 		u64 mmr_war_offset;
@@ -79,7 +79,7 @@
 }
  
 static void inline
-tioce_mmr_war_post(struct tioce_kernel *kern, void *mmr_addr)
+tioce_mmr_war_post(struct tioce_kernel *kern, void __iomem *mmr_addr)
 {
 	u64 mmr_base;
 	u64 mmr_offset;
@@ -88,7 +88,7 @@
 		return;
  
 	mmr_base = kern->ce_common->ce_pcibus.bs_base;
-	mmr_offset = (u64)mmr_addr - mmr_base;
+	mmr_offset = (unsigned long)mmr_addr - mmr_base;
  
 	if (mmr_offset < 0x45000) {
 		if (mmr_offset == 0x100)
@@ -223,7 +223,7 @@
  * @pci_dev.
  */
 static inline void
-pcidev_to_tioce(struct pci_dev *pdev, struct tioce **base,
+pcidev_to_tioce(struct pci_dev *pdev, struct tioce __iomem **base,
 		struct tioce_kernel **kernel, int *port)
 {
 	struct pcidev_info *pcidev_info;
@@ -235,7 +235,7 @@
 	ce_kernel = (struct tioce_kernel *)ce_common->ce_kernel_private;
  
 	if (base)
-		*base = (struct tioce *)ce_common->ce_pcibus.bs_base;
+		*base = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base;
 	if (kernel)
 		*kernel = ce_kernel;
  
  
  
@@ -275,13 +275,13 @@
 	u64 pagesize;
 	int msi_capable, msi_wanted;
 	u64 *ate_shadow;
-	u64 *ate_reg;
+	u64 __iomem *ate_reg;
 	u64 addr;
-	struct tioce *ce_mmr;
+	struct tioce __iomem *ce_mmr;
 	u64 bus_base;
 	struct tioce_dmamap *map;
  
-	ce_mmr = (struct tioce *)ce_kern->ce_common->ce_pcibus.bs_base;
+	ce_mmr = (struct tioce __iomem *)ce_kern->ce_common->ce_pcibus.bs_base;
  
 	switch (type) {
 	case TIOCE_ATE_M32:
@@ -386,7 +386,7 @@
 {
 	int dma_ok;
 	int port;
-	struct tioce *ce_mmr;
+	struct tioce __iomem *ce_mmr;
 	struct tioce_kernel *ce_kern;
 	u64 ct_upper;
 	u64 ct_lower;
@@ -461,7 +461,7 @@
 	int i;
 	int port;
 	struct tioce_kernel *ce_kern;
-	struct tioce *ce_mmr;
+	struct tioce __iomem *ce_mmr;
 	unsigned long flags;
  
 	bus_addr = tioce_dma_barrier(bus_addr, 0);
  
@@ -700,9 +700,9 @@
 tioce_reserve_m32(struct tioce_kernel *ce_kern, u64 base, u64 limit)
 {
 	int ate_index, last_ate, ps;
-	struct tioce *ce_mmr;
+	struct tioce __iomem *ce_mmr;
  
-	ce_mmr = (struct tioce *)ce_kern->ce_common->ce_pcibus.bs_base;
+	ce_mmr = (struct tioce __iomem *)ce_kern->ce_common->ce_pcibus.bs_base;
 	ps = ce_kern->ce_ate3240_pagesize;
 	ate_index = ATE_PAGE(base, ps);
 	last_ate = ate_index + ATE_NPAGES(base, limit-base+1, ps) - 1;
@@ -736,7 +736,7 @@
 	int dev;
 	u32 tmp;
 	unsigned int seg, bus;
-	struct tioce *tioce_mmr;
+	struct tioce __iomem *tioce_mmr;
 	struct tioce_kernel *tioce_kern;
  
 	tioce_kern = kzalloc(sizeof(struct tioce_kernel), GFP_KERNEL);
@@ -767,7 +767,7 @@
 	 * the ate's.
 	 */
  
-	tioce_mmr = (struct tioce *)tioce_common->ce_pcibus.bs_base;
+	tioce_mmr = (struct tioce __iomem *)tioce_common->ce_pcibus.bs_base;
 	tioce_mmr_clri(tioce_kern, &tioce_mmr->ce_ure_page_map,
 		       CE_URE_PAGESIZE_MASK);
 	tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_ure_page_map,
@@ -858,7 +858,7 @@
 	struct pcidev_info *pcidev_info;
 	struct tioce_common *ce_common;
 	struct tioce_kernel *ce_kern;
-	struct tioce *ce_mmr;
+	struct tioce __iomem *ce_mmr;
 	u64 force_int_val;
  
 	if (!sn_irq_info->irq_bridge)
@@ -872,7 +872,7 @@
 		return;
  
 	ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
-	ce_mmr = (struct tioce *)ce_common->ce_pcibus.bs_base;
+	ce_mmr = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base;
 	ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private;
  
 	/*
@@ -953,7 +953,7 @@
 	struct pcidev_info *pcidev_info;
 	struct tioce_common *ce_common;
 	struct tioce_kernel *ce_kern;
-	struct tioce *ce_mmr;
+	struct tioce __iomem *ce_mmr;
 	int bit;
 	u64 vector;
  
@@ -962,7 +962,7 @@
 		return;
  
 	ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
-	ce_mmr = (struct tioce *)ce_common->ce_pcibus.bs_base;
+	ce_mmr = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base;
 	ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private;
  
 	bit = sn_irq_info->irq_int_bit;
@@ -994,7 +994,7 @@
 	cnodeid_t my_cnode, mem_cnode;
 	struct tioce_common *tioce_common;
 	struct tioce_kernel *tioce_kern;
-	struct tioce *tioce_mmr;
+	struct tioce __iomem *tioce_mmr;
  
 	/*
 	 * Allocate kernel bus soft and copy from prom.
@@ -1018,7 +1018,7 @@
 	 * interrupt handler.
 	 */
  
-	tioce_mmr = (struct tioce *)tioce_common->ce_pcibus.bs_base;
+	tioce_mmr = (struct tioce __iomem *)tioce_common->ce_pcibus.bs_base;
 	tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_int_status_alias, ~0ULL);
 	tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_error_summary_alias,
 		       ~0ULL);
@@ -135,7 +135,7 @@
 extern void             pcireg_force_intr_set(struct pcibus_info *, int);
 extern u64         pcireg_wrb_flush_get(struct pcibus_info *, int);
 extern void             pcireg_int_ate_set(struct pcibus_info *, int, u64);
-extern u64 *	pcireg_int_ate_addr(struct pcibus_info *, int);
+extern u64 __iomem *	pcireg_int_ate_addr(struct pcibus_info *, int);
 extern void 		pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
 extern void 		pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
 extern int 		pcibr_ate_alloc(struct pcibus_info *, int);
@@ -162,11 +162,11 @@
 tioca_tlbflush(struct tioca_kernel *tioca_kernel)
 {
 	volatile u64 tmp;
-	volatile struct tioca *ca_base;
+	volatile struct tioca __iomem *ca_base;
 	struct tioca_common *tioca_common;
  
 	tioca_common = tioca_kernel->ca_common;
-	ca_base = (struct tioca *)tioca_common->ca_common.bs_base;
+	ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base;
  
 	/*
 	 * Explicit flushes not needed if GART is in cached mode
@@ -53,7 +53,7 @@
 	u64		ct_start;	/* coretalk start address */
 	u64		pci_start;	/* bus start address */
  
-	u64		*ate_hw;	/* hw ptr of first ate in map */
+	u64		__iomem *ate_hw;/* hw ptr of first ate in map */
 	u64		*ate_shadow;	/* shadow ptr of firat ate */
 	u16		ate_count;	/* # ate's in the map */
 };
...	...	@@ -126,7 +126,7 @@
126	126	* Setup an Address Translation Entry as specified. Use either the Bridge
127	127	* internal maps or the external map RAM, as appropriate.
128	128	*/
129		-static inline u64 pcibr_ate_addr(struct pcibus_info pcibus_info,
	129	+static inline u64 __iomem pcibr_ate_addr(struct pcibus_info pcibus_info,
130	130	int ate_index)
131	131	{
132	132	if (ate_index < pcibus_info->pbi_int_ate_size) {
...	...	@@ -53,7 +53,7 @@
53	53	*/
54	54
55	55	static void inline
56		-tioce_mmr_war_pre(struct tioce_kernel kern, void mmr_addr)
	56	+tioce_mmr_war_pre(struct tioce_kernel kern, void __iomem mmr_addr)
57	57	{
58	58	u64 mmr_base;
59	59	u64 mmr_offset;
...	...	@@ -62,7 +62,7 @@
62	62	return;
63	63
64	64	mmr_base = kern->ce_common->ce_pcibus.bs_base;
65		- mmr_offset = (u64)mmr_addr - mmr_base;
	65	+ mmr_offset = (unsigned long)mmr_addr - mmr_base;
66	66
67	67	if (mmr_offset < 0x45000) {
68	68	u64 mmr_war_offset;
...	...	@@ -79,7 +79,7 @@
79	79	}
80	80
81	81	static void inline
82		-tioce_mmr_war_post(struct tioce_kernel kern, void mmr_addr)
	82	+tioce_mmr_war_post(struct tioce_kernel kern, void __iomem mmr_addr)
83	83	{
84	84	u64 mmr_base;
85	85	u64 mmr_offset;
...	...	@@ -88,7 +88,7 @@
88	88	return;
89	89
90	90	mmr_base = kern->ce_common->ce_pcibus.bs_base;
91		- mmr_offset = (u64)mmr_addr - mmr_base;
	91	+ mmr_offset = (unsigned long)mmr_addr - mmr_base;
92	92
93	93	if (mmr_offset < 0x45000) {
94	94	if (mmr_offset == 0x100)
...	...	@@ -223,7 +223,7 @@
223	223	* @pci_dev.
224	224	*/
225	225	static inline void
226		-pcidev_to_tioce(struct pci_dev pdev, struct tioce *base,
	226	+pcidev_to_tioce(struct pci_dev pdev, struct tioce __iomem *base,
227	227	struct tioce_kernel *kernel, int port)
228	228	{
229	229	struct pcidev_info *pcidev_info;
...	...	@@ -235,7 +235,7 @@
235	235	ce_kernel = (struct tioce_kernel *)ce_common->ce_kernel_private;
236	236
237	237	if (base)
238		- base = (struct tioce )ce_common->ce_pcibus.bs_base;
	238	+ base = (struct tioce __iomem )ce_common->ce_pcibus.bs_base;
239	239	if (kernel)
240	240	*kernel = ce_kernel;
241	241
242	242
243	243
...	...	@@ -275,13 +275,13 @@
275	275	u64 pagesize;
276	276	int msi_capable, msi_wanted;
277	277	u64 *ate_shadow;
278		- u64 *ate_reg;
	278	+ u64 __iomem *ate_reg;
279	279	u64 addr;
280		- struct tioce *ce_mmr;
	280	+ struct tioce __iomem *ce_mmr;
281	281	u64 bus_base;
282	282	struct tioce_dmamap *map;
283	283
284		- ce_mmr = (struct tioce *)ce_kern->ce_common->ce_pcibus.bs_base;
	284	+ ce_mmr = (struct tioce __iomem *)ce_kern->ce_common->ce_pcibus.bs_base;
285	285
286	286	switch (type) {
287	287	case TIOCE_ATE_M32:
...	...	@@ -386,7 +386,7 @@
386	386	{
387	387	int dma_ok;
388	388	int port;
389		- struct tioce *ce_mmr;
	389	+ struct tioce __iomem *ce_mmr;
390	390	struct tioce_kernel *ce_kern;
391	391	u64 ct_upper;
392	392	u64 ct_lower;
...	...	@@ -461,7 +461,7 @@
461	461	int i;
462	462	int port;
463	463	struct tioce_kernel *ce_kern;
464		- struct tioce *ce_mmr;
	464	+ struct tioce __iomem *ce_mmr;
465	465	unsigned long flags;
466	466
467	467	bus_addr = tioce_dma_barrier(bus_addr, 0);
468	468
...	...	@@ -700,9 +700,9 @@
700	700	tioce_reserve_m32(struct tioce_kernel *ce_kern, u64 base, u64 limit)
701	701	{
702	702	int ate_index, last_ate, ps;
703		- struct tioce *ce_mmr;
	703	+ struct tioce __iomem *ce_mmr;
704	704
705		- ce_mmr = (struct tioce *)ce_kern->ce_common->ce_pcibus.bs_base;
	705	+ ce_mmr = (struct tioce __iomem *)ce_kern->ce_common->ce_pcibus.bs_base;
706	706	ps = ce_kern->ce_ate3240_pagesize;
707	707	ate_index = ATE_PAGE(base, ps);
708	708	last_ate = ate_index + ATE_NPAGES(base, limit-base+1, ps) - 1;
...	...	@@ -736,7 +736,7 @@
736	736	int dev;
737	737	u32 tmp;
738	738	unsigned int seg, bus;
739		- struct tioce *tioce_mmr;
	739	+ struct tioce __iomem *tioce_mmr;
740	740	struct tioce_kernel *tioce_kern;
741	741
742	742	tioce_kern = kzalloc(sizeof(struct tioce_kernel), GFP_KERNEL);
...	...	@@ -767,7 +767,7 @@
767	767	* the ate's.
768	768	*/
769	769
770		- tioce_mmr = (struct tioce *)tioce_common->ce_pcibus.bs_base;
	770	+ tioce_mmr = (struct tioce __iomem *)tioce_common->ce_pcibus.bs_base;
771	771	tioce_mmr_clri(tioce_kern, &tioce_mmr->ce_ure_page_map,
772	772	CE_URE_PAGESIZE_MASK);
773	773	tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_ure_page_map,
...	...	@@ -858,7 +858,7 @@
858	858	struct pcidev_info *pcidev_info;
859	859	struct tioce_common *ce_common;
860	860	struct tioce_kernel *ce_kern;
861		- struct tioce *ce_mmr;
	861	+ struct tioce __iomem *ce_mmr;
862	862	u64 force_int_val;
863	863
864	864	if (!sn_irq_info->irq_bridge)
...	...	@@ -872,7 +872,7 @@
872	872	return;
873	873
874	874	ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
875		- ce_mmr = (struct tioce *)ce_common->ce_pcibus.bs_base;
	875	+ ce_mmr = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base;
876	876	ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private;
877	877
878	878	/*
...	...	@@ -953,7 +953,7 @@
953	953	struct pcidev_info *pcidev_info;
954	954	struct tioce_common *ce_common;
955	955	struct tioce_kernel *ce_kern;
956		- struct tioce *ce_mmr;
	956	+ struct tioce __iomem *ce_mmr;
957	957	int bit;
958	958	u64 vector;
959	959
...	...	@@ -962,7 +962,7 @@
962	962	return;
963	963
964	964	ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
965		- ce_mmr = (struct tioce *)ce_common->ce_pcibus.bs_base;
	965	+ ce_mmr = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base;
966	966	ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private;
967	967
968	968	bit = sn_irq_info->irq_int_bit;
...	...	@@ -994,7 +994,7 @@
994	994	cnodeid_t my_cnode, mem_cnode;
995	995	struct tioce_common *tioce_common;
996	996	struct tioce_kernel *tioce_kern;
997		- struct tioce *tioce_mmr;
	997	+ struct tioce __iomem *tioce_mmr;
998	998
999	999	/*
1000	1000	* Allocate kernel bus soft and copy from prom.
...	...	@@ -1018,7 +1018,7 @@
1018	1018	* interrupt handler.
1019	1019	*/
1020	1020
1021		- tioce_mmr = (struct tioce *)tioce_common->ce_pcibus.bs_base;
	1021	+ tioce_mmr = (struct tioce __iomem *)tioce_common->ce_pcibus.bs_base;
1022	1022	tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_int_status_alias, ~0ULL);
1023	1023	tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_error_summary_alias,
1024	1024	~0ULL);
...	...	@@ -135,7 +135,7 @@
135	135	extern void pcireg_force_intr_set(struct pcibus_info *, int);
136	136	extern u64 pcireg_wrb_flush_get(struct pcibus_info *, int);
137	137	extern void pcireg_int_ate_set(struct pcibus_info *, int, u64);
138		-extern u64 * pcireg_int_ate_addr(struct pcibus_info *, int);
	138	+extern u64 __iomem * pcireg_int_ate_addr(struct pcibus_info *, int);
139	139	extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
140	140	extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
141	141	extern int pcibr_ate_alloc(struct pcibus_info *, int);
...	...	@@ -162,11 +162,11 @@
162	162	tioca_tlbflush(struct tioca_kernel *tioca_kernel)
163	163	{
164	164	volatile u64 tmp;
165		- volatile struct tioca *ca_base;
	165	+ volatile struct tioca __iomem *ca_base;
166	166	struct tioca_common *tioca_common;
167	167
168	168	tioca_common = tioca_kernel->ca_common;
169		- ca_base = (struct tioca *)tioca_common->ca_common.bs_base;
	169	+ ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base;
170	170
171	171	/*
172	172	* Explicit flushes not needed if GART is in cached mode
...	...	@@ -53,7 +53,7 @@
53	53	u64 ct_start; /* coretalk start address */
54	54	u64 pci_start; /* bus start address */
55	55
56		- u64 ate_hw; / hw ptr of first ate in map */
	56	+ u64 __iomem ate_hw;/ hw ptr of first ate in map */
57	57	u64 ate_shadow; / shadow ptr of firat ate */
58	58	u16 ate_count; /* # ate's in the map */
59	59	};