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Commit aa4a5db52a440d32eab134bfb79d2c9af71eedb4

Authored by Nobuhiro Iwamatsu
Committed by Paul Mundt
1 parent 08d2e099fb
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

sh: Solution Engine 770x IPR irq setup. 

Fixups for external IPR IRQs for the SE770x FPGA.

Signed-off-by: Nobuhiro Iwamatsu <hemamu@t-base.ne.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

Showing 2 changed files with 75 additions and 41 deletions Inline Diff

arch/sh/boards/se/770x/irq.c
Diff comments   View file @ aa4a5db
1 /* 1 /*
2 * linux/arch/sh/boards/se/770x/irq.c 2 * linux/arch/sh/boards/se/770x/irq.c
3 * 3 *
4 * Copyright (C) 2000 Kazumoto Kojima 4 * Copyright (C) 2000 Kazumoto Kojima
5 * Copyright (C) 2006 Nobuhiro Iwamatsu
5 * 6 *
6 * Hitachi SolutionEngine Support. 7 * Hitachi SolutionEngine Support.
7 * 8 *
8 */ 9 */
9 10
10 #include <linux/init.h> 11 #include <linux/init.h>
12 #include <linux/interrupt.h>
11 #include <linux/irq.h> 13 #include <linux/irq.h>
12 #include <asm/irq.h> 14 #include <asm/irq.h>
13 #include <asm/io.h> 15 #include <asm/io.h>
14 #include <asm/se.h> 16 #include <asm/se.h>
15 17
18 /*
19 * If the problem of make_ipr_irq is solved,
20 * this code will become unnecessary. :-)
21 */
22 static void se770x_disable_ipr_irq(unsigned int irq)
23 {
24 struct ipr_data *p = get_irq_chip_data(irq);
25
26 ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << p->shift)), p->addr);
27 }
28
29 static void se770x_enable_ipr_irq(unsigned int irq)
30 {
31 struct ipr_data *p = get_irq_chip_data(irq);
32
33 ctrl_outw(ctrl_inw(p->addr) | (p->priority << p->shift), p->addr);
34 }
35
36 static struct irq_chip se770x_irq_chip = {
37 .name = "MS770xSE-FPGA",
38 .mask = se770x_disable_ipr_irq,
39 .unmask = se770x_enable_ipr_irq,
40 .mask_ack = se770x_disable_ipr_irq,
41 };
42
43 void make_se770x_irq(struct ipr_data *table, unsigned int nr_irqs)
44 {
45 int i;
46
47 for (i = 0; i < nr_irqs; i++) {
48 unsigned int irq = table[i].irq;
49 disable_irq_nosync(irq);
50 set_irq_chip_and_handler_name(irq, &se770x_irq_chip,
51 handle_level_irq, "level");
52 set_irq_chip_data(irq, &table[i]);
53 se770x_enable_ipr_irq(irq);
54 }
55 }
56
16 static struct ipr_data se770x_ipr_map[] = { 57 static struct ipr_data se770x_ipr_map[] = {
17 #if defined(CONFIG_CPU_SUBTYPE_SH7705) 58 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
18 /* This is default value */ 59 /* This is default value */
19 { 0xf-0x2, BCR_ILCRA, 2, 0x2 }, 60 { 0xf-0x2, 0, 8, 0x2 , BCR_ILCRA},
20 { 0xf-0xa, BCR_ILCRA, 1, 0xa }, 61 { 0xf-0xa, 0, 4, 0xa , BCR_ILCRA},
21 { 0xf-0x5, BCR_ILCRB, 0, 0x5 }, 62 { 0xf-0x5, 0, 0, 0x5 , BCR_ILCRB},
22 { 0xf-0x8, BCR_ILCRC, 1, 0x8 }, 63 { 0xf-0x8, 0, 4, 0x8 , BCR_ILCRC},
23 { 0xf-0xc, BCR_ILCRC, 0, 0xc }, 64 { 0xf-0xc, 0, 0, 0xc , BCR_ILCRC},
24 { 0xf-0xe, BCR_ILCRD, 3, 0xe }, 65 { 0xf-0xe, 0, 12, 0xe , BCR_ILCRD},
25 { 0xf-0x3, BCR_ILCRD, 1, 0x3 }, /* LAN */ 66 { 0xf-0x3, 0, 4, 0x3 , BCR_ILCRD}, /* LAN */
26 { 0xf-0xd, BCR_ILCRE, 2, 0xd }, 67 { 0xf-0xd, 0, 8, 0xd , BCR_ILCRE},
27 { 0xf-0x9, BCR_ILCRE, 1, 0x9 }, 68 { 0xf-0x9, 0, 4, 0x9 , BCR_ILCRE},
28 { 0xf-0x1, BCR_ILCRE, 0, 0x1 }, 69 { 0xf-0x1, 0, 0, 0x1 , BCR_ILCRE},
29 { 0xf-0xf, BCR_ILCRF, 3, 0xf }, 70 { 0xf-0xf, 0, 12, 0xf , BCR_ILCRF},
30 { 0xf-0xb, BCR_ILCRF, 1, 0xb }, 71 { 0xf-0xb, 0, 4, 0xb , BCR_ILCRF},
31 { 0xf-0x7, BCR_ILCRG, 3, 0x7 }, 72 { 0xf-0x7, 0, 12, 0x7 , BCR_ILCRG},
32 { 0xf-0x6, BCR_ILCRG, 2, 0x6 }, 73 { 0xf-0x6, 0, 8, 0x6 , BCR_ILCRG},
33 { 0xf-0x4, BCR_ILCRG, 1, 0x4 }, 74 { 0xf-0x4, 0, 4, 0x4 , BCR_ILCRG},
34 #else 75 #else
35 { 14, BCR_ILCRA, 2, 0x0f-14 }, 76 { 14, 0, 8, 0x0f-14 ,BCR_ILCRA},
36 { 12, BCR_ILCRA, 1, 0x0f-12 }, 77 { 12, 0, 4, 0x0f-12 ,BCR_ILCRA},
37 { 8, BCR_ILCRB, 1, 0x0f- 8 }, 78 { 8, 0, 4, 0x0f- 8 ,BCR_ILCRB},
38 { 6, BCR_ILCRC, 3, 0x0f- 6 }, 79 { 6, 0, 12, 0x0f- 6 ,BCR_ILCRC},
39 { 5, BCR_ILCRC, 2, 0x0f- 5 }, 80 { 5, 0, 8, 0x0f- 5 ,BCR_ILCRC},
40 { 4, BCR_ILCRC, 1, 0x0f- 4 }, 81 { 4, 0, 4, 0x0f- 4 ,BCR_ILCRC},
41 { 3, BCR_ILCRC, 0, 0x0f- 3 }, 82 { 3, 0, 0, 0x0f- 3 ,BCR_ILCRC},
42 { 1, BCR_ILCRD, 3, 0x0f- 1 }, 83 { 1, 0, 12, 0x0f- 1 ,BCR_ILCRD},
43 84 /* ST NIC */
44 { 10, BCR_ILCRD, 1, 0x0f-10 }, /* LAN */ 85 { 10, 0, 4, 0x0f-10 ,BCR_ILCRD}, /* LAN */
45 86 /* MRSHPC IRQs setting */
46 { 0, BCR_ILCRE, 3, 0x0f- 0 }, /* PCIRQ3 */ 87 { 0, 0, 12, 0x0f- 0 ,BCR_ILCRE}, /* PCIRQ3 */
47 { 11, BCR_ILCRE, 2, 0x0f-11 }, /* PCIRQ2 */ 88 { 11, 0, 8, 0x0f-11 ,BCR_ILCRE}, /* PCIRQ2 */
48 { 9, BCR_ILCRE, 1, 0x0f- 9 }, /* PCIRQ1 */ 89 { 9, 0, 4, 0x0f- 9 ,BCR_ILCRE}, /* PCIRQ1 */
49 { 7, BCR_ILCRE, 0, 0x0f- 7 }, /* PCIRQ0 */ 90 { 7, 0, 0, 0x0f- 7 ,BCR_ILCRE}, /* PCIRQ0 */
50
51 /* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */ 91 /* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */
52 /* NOTE: #2 and #13 are not used on PC */ 92 /* NOTE: #2 and #13 are not used on PC */
53 { 13, BCR_ILCRG, 1, 0x0f-13 }, /* SLOTIRQ2 */ 93 { 13, 0, 4, 0x0f-13 ,BCR_ILCRG}, /* SLOTIRQ2 */
54 { 2, BCR_ILCRG, 0, 0x0f- 2 }, /* SLOTIRQ1 */ 94 { 2, 0, 0, 0x0f- 2 ,BCR_ILCRG}, /* SLOTIRQ1 */
55 #endif 95 #endif
56 }; 96 };
57 97
58 /* 98 /*
59 * Initialize IRQ setting 99 * Initialize IRQ setting
60 */ 100 */
61 void __init init_se_IRQ(void) 101 void __init init_se_IRQ(void)
62 { 102 {
63 /* 103 /*
64 * Super I/O (Just mimic PC): 104 * Super I/O (Just mimic PC):
65 * 1: keyboard 105 * 1: keyboard
66 * 3: serial 0 106 * 3: serial 0
67 * 4: serial 1 107 * 4: serial 1
68 * 5: printer 108 * 5: printer
69 * 6: floppy 109 * 6: floppy
70 * 8: rtc 110 * 8: rtc
71 * 12: mouse 111 * 12: mouse
72 * 14: ide0 112 * 14: ide0
73 */ 113 */
74 #if defined(CONFIG_CPU_SUBTYPE_SH7705) 114 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
75 /* Disable all interrupts */ 115 /* Disable all interrupts */
76 ctrl_outw(0, BCR_ILCRA); 116 ctrl_outw(0, BCR_ILCRA);
77 ctrl_outw(0, BCR_ILCRB); 117 ctrl_outw(0, BCR_ILCRB);
78 ctrl_outw(0, BCR_ILCRC); 118 ctrl_outw(0, BCR_ILCRC);
79 ctrl_outw(0, BCR_ILCRD); 119 ctrl_outw(0, BCR_ILCRD);
80 ctrl_outw(0, BCR_ILCRE); 120 ctrl_outw(0, BCR_ILCRE);
81 ctrl_outw(0, BCR_ILCRF); 121 ctrl_outw(0, BCR_ILCRF);
82 ctrl_outw(0, BCR_ILCRG); 122 ctrl_outw(0, BCR_ILCRG);
83 #endif 123 #endif
84 make_ipr_irq(se770x_ipr_map, ARRAY_SIZE(se770x_ipr_map)); 124 make_se770x_irq(se770x_ipr_map, ARRAY_SIZE(se770x_ipr_map));
85 } 125 }
arch/sh/boards/se/770x/setup.c
Diff comments   View file @ aa4a5db
1 /* $Id: setup.c,v 1.1.2.4 2002/03/02 21:57:07 lethal Exp $ 1 /*
2 *
3 * linux/arch/sh/boards/se/770x/setup.c 2 * linux/arch/sh/boards/se/770x/setup.c
4 * 3 *
5 * Copyright (C) 2000 Kazumoto Kojima 4 * Copyright (C) 2000 Kazumoto Kojima
6 * 5 *
7 * Hitachi SolutionEngine Support. 6 * Hitachi SolutionEngine Support.
8 * 7 *
9 */ 8 */
10 #include <linux/init.h> 9 #include <linux/init.h>
11 #include <asm/machvec.h> 10 #include <asm/machvec.h>
12 #include <asm/se.h> 11 #include <asm/se.h>
13 #include <asm/io.h> 12 #include <asm/io.h>
14 #include <asm/smc37c93x.h> 13 #include <asm/smc37c93x.h>
15 14
16 void heartbeat_se(void); 15 void heartbeat_se(void);
17 void init_se_IRQ(void); 16 void init_se_IRQ(void);
18 17
19 /* 18 /*
20 * Configure the Super I/O chip 19 * Configure the Super I/O chip
21 */ 20 */
22 static void __init smsc_config(int index, int data) 21 static void __init smsc_config(int index, int data)
23 { 22 {
24 outb_p(index, INDEX_PORT); 23 outb_p(index, INDEX_PORT);
25 outb_p(data, DATA_PORT); 24 outb_p(data, DATA_PORT);
26 } 25 }
27 26
28 /* XXX: Another candidate for a more generic cchip machine vector */ 27 /* XXX: Another candidate for a more generic cchip machine vector */
29 static void __init smsc_setup(char **cmdline_p) 28 static void __init smsc_setup(char **cmdline_p)
30 { 29 {
31 outb_p(CONFIG_ENTER, CONFIG_PORT); 30 outb_p(CONFIG_ENTER, CONFIG_PORT);
32 outb_p(CONFIG_ENTER, CONFIG_PORT); 31 outb_p(CONFIG_ENTER, CONFIG_PORT);
33 32
34 /* FDC */ 33 /* FDC */
35 smsc_config(CURRENT_LDN_INDEX, LDN_FDC); 34 smsc_config(CURRENT_LDN_INDEX, LDN_FDC);
36 smsc_config(ACTIVATE_INDEX, 0x01); 35 smsc_config(ACTIVATE_INDEX, 0x01);
37 smsc_config(IRQ_SELECT_INDEX, 6); /* IRQ6 */ 36 smsc_config(IRQ_SELECT_INDEX, 6); /* IRQ6 */
38
39 /* IDE1 */
40 smsc_config(CURRENT_LDN_INDEX, LDN_IDE1);
41 smsc_config(ACTIVATE_INDEX, 0x01);
42 smsc_config(IRQ_SELECT_INDEX, 14); /* IRQ14 */
43 37
44 /* AUXIO (GPIO): to use IDE1 */ 38 /* AUXIO (GPIO): to use IDE1 */
45 smsc_config(CURRENT_LDN_INDEX, LDN_AUXIO); 39 smsc_config(CURRENT_LDN_INDEX, LDN_AUXIO);
46 smsc_config(GPIO46_INDEX, 0x00); /* nIOROP */ 40 smsc_config(GPIO46_INDEX, 0x00); /* nIOROP */
47 smsc_config(GPIO47_INDEX, 0x00); /* nIOWOP */ 41 smsc_config(GPIO47_INDEX, 0x00); /* nIOWOP */
48 42
49 /* COM1 */ 43 /* COM1 */
50 smsc_config(CURRENT_LDN_INDEX, LDN_COM1); 44 smsc_config(CURRENT_LDN_INDEX, LDN_COM1);
51 smsc_config(ACTIVATE_INDEX, 0x01); 45 smsc_config(ACTIVATE_INDEX, 0x01);
52 smsc_config(IO_BASE_HI_INDEX, 0x03); 46 smsc_config(IO_BASE_HI_INDEX, 0x03);
53 smsc_config(IO_BASE_LO_INDEX, 0xf8); 47 smsc_config(IO_BASE_LO_INDEX, 0xf8);
54 smsc_config(IRQ_SELECT_INDEX, 4); /* IRQ4 */ 48 smsc_config(IRQ_SELECT_INDEX, 4); /* IRQ4 */
55 49
56 /* COM2 */ 50 /* COM2 */
57 smsc_config(CURRENT_LDN_INDEX, LDN_COM2); 51 smsc_config(CURRENT_LDN_INDEX, LDN_COM2);
58 smsc_config(ACTIVATE_INDEX, 0x01); 52 smsc_config(ACTIVATE_INDEX, 0x01);
59 smsc_config(IO_BASE_HI_INDEX, 0x02); 53 smsc_config(IO_BASE_HI_INDEX, 0x02);
60 smsc_config(IO_BASE_LO_INDEX, 0xf8); 54 smsc_config(IO_BASE_LO_INDEX, 0xf8);
61 smsc_config(IRQ_SELECT_INDEX, 3); /* IRQ3 */ 55 smsc_config(IRQ_SELECT_INDEX, 3); /* IRQ3 */
62 56
63 /* RTC */ 57 /* RTC */
64 smsc_config(CURRENT_LDN_INDEX, LDN_RTC); 58 smsc_config(CURRENT_LDN_INDEX, LDN_RTC);
65 smsc_config(ACTIVATE_INDEX, 0x01); 59 smsc_config(ACTIVATE_INDEX, 0x01);
66 smsc_config(IRQ_SELECT_INDEX, 8); /* IRQ8 */ 60 smsc_config(IRQ_SELECT_INDEX, 8); /* IRQ8 */
67 61
68 /* XXX: PARPORT, KBD, and MOUSE will come here... */ 62 /* XXX: PARPORT, KBD, and MOUSE will come here... */
69 outb_p(CONFIG_EXIT, CONFIG_PORT); 63 outb_p(CONFIG_EXIT, CONFIG_PORT);
70 } 64 }
71 65
72 /* 66 /*
73 * The Machine Vector 67 * The Machine Vector
74 */ 68 */
75 struct sh_machine_vector mv_se __initmv = { 69 struct sh_machine_vector mv_se __initmv = {
76 .mv_name = "SolutionEngine", 70 .mv_name = "SolutionEngine",
77 .mv_setup = smsc_setup, 71 .mv_setup = smsc_setup,
78 #if defined(CONFIG_CPU_SH4) 72 #if defined(CONFIG_CPU_SH4)
79 .mv_nr_irqs = 48, 73 .mv_nr_irqs = 48,
80 #elif defined(CONFIG_CPU_SUBTYPE_SH7708) 74 #elif defined(CONFIG_CPU_SUBTYPE_SH7708)
81 .mv_nr_irqs = 32, 75 .mv_nr_irqs = 32,
82 #elif defined(CONFIG_CPU_SUBTYPE_SH7709) 76 #elif defined(CONFIG_CPU_SUBTYPE_SH7709)
83 .mv_nr_irqs = 61, 77 .mv_nr_irqs = 61,
84 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) 78 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
85 .mv_nr_irqs = 86, 79 .mv_nr_irqs = 86,
86 #endif 80 #endif
87 81
88 .mv_inb = se_inb, 82 .mv_inb = se_inb,
89 .mv_inw = se_inw, 83 .mv_inw = se_inw,
90 .mv_inl = se_inl, 84 .mv_inl = se_inl,
91 .mv_outb = se_outb, 85 .mv_outb = se_outb,
92 .mv_outw = se_outw, 86 .mv_outw = se_outw,
93 .mv_outl = se_outl, 87 .mv_outl = se_outl,
94 88
95 .mv_inb_p = se_inb_p, 89 .mv_inb_p = se_inb_p,
96 .mv_inw_p = se_inw, 90 .mv_inw_p = se_inw,
97 .mv_inl_p = se_inl, 91 .mv_inl_p = se_inl,
98 .mv_outb_p = se_outb_p, 92 .mv_outb_p = se_outb_p,
99 .mv_outw_p = se_outw, 93 .mv_outw_p = se_outw,
100 .mv_outl_p = se_outl, 94 .mv_outl_p = se_outl,
101 95
102 .mv_insb = se_insb, 96 .mv_insb = se_insb,
103 .mv_insw = se_insw, 97 .mv_insw = se_insw,
104 .mv_insl = se_insl, 98 .mv_insl = se_insl,
105 .mv_outsb = se_outsb, 99 .mv_outsb = se_outsb,
106 .mv_outsw = se_outsw, 100 .mv_outsw = se_outsw,
107 .mv_outsl = se_outsl, 101 .mv_outsl = se_outsl,
108 102
109 .mv_init_irq = init_se_IRQ, 103 .mv_init_irq = init_se_IRQ,
110 #ifdef CONFIG_HEARTBEAT 104 #ifdef CONFIG_HEARTBEAT
111 .mv_heartbeat = heartbeat_se, 105 .mv_heartbeat = heartbeat_se,
112 #endif 106 #endif
113 }; 107 };
114 ALIAS_MV(se) 108 ALIAS_MV(se)
115 109