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Commit aa4a5db52a440d32eab134bfb79d2c9af71eedb4

Authored by Nobuhiro Iwamatsu
Committed by Paul Mundt
1 parent 08d2e099fb
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

sh: Solution Engine 770x IPR irq setup. 

Fixups for external IPR IRQs for the SE770x FPGA.

Signed-off-by: Nobuhiro Iwamatsu <hemamu@t-base.ne.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

Showing 2 changed files with 75 additions and 41 deletions Side-by-side Diff

arch/sh/boards/se/770x/irq.c
Diff comments   View file @ aa4a5db
... ... @@ -2,56 +2,96 @@
2 2 * linux/arch/sh/boards/se/770x/irq.c
3 3 *
4 4 * Copyright (C) 2000 Kazumoto Kojima
  5 + * Copyright (C) 2006 Nobuhiro Iwamatsu
5 6 *
6 7 * Hitachi SolutionEngine Support.
7 8 *
8 9 */
9 10  
10 11 #include <linux/init.h>
  12 +#include <linux/interrupt.h>
11 13 #include <linux/irq.h>
12 14 #include <asm/irq.h>
13 15 #include <asm/io.h>
14 16 #include <asm/se.h>
15 17  
  18 +/*
  19 + * If the problem of make_ipr_irq is solved,
  20 + * this code will become unnecessary. :-)
  21 + */
  22 +static void se770x_disable_ipr_irq(unsigned int irq)
  23 +{
  24 + struct ipr_data *p = get_irq_chip_data(irq);
  25 +
  26 + ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << p->shift)), p->addr);
  27 +}
  28 +
  29 +static void se770x_enable_ipr_irq(unsigned int irq)
  30 +{
  31 + struct ipr_data *p = get_irq_chip_data(irq);
  32 +
  33 + ctrl_outw(ctrl_inw(p->addr) | (p->priority << p->shift), p->addr);
  34 +}
  35 +
  36 +static struct irq_chip se770x_irq_chip = {
  37 + .name = "MS770xSE-FPGA",
  38 + .mask = se770x_disable_ipr_irq,
  39 + .unmask = se770x_enable_ipr_irq,
  40 + .mask_ack = se770x_disable_ipr_irq,
  41 +};
  42 +
  43 +void make_se770x_irq(struct ipr_data *table, unsigned int nr_irqs)
  44 +{
  45 + int i;
  46 +
  47 + for (i = 0; i < nr_irqs; i++) {
  48 + unsigned int irq = table[i].irq;
  49 + disable_irq_nosync(irq);
  50 + set_irq_chip_and_handler_name(irq, &se770x_irq_chip,
  51 + handle_level_irq, "level");
  52 + set_irq_chip_data(irq, &table[i]);
  53 + se770x_enable_ipr_irq(irq);
  54 + }
  55 +}
  56 +
16 57 static struct ipr_data se770x_ipr_map[] = {
17 58 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
18 59 /* This is default value */
19   - { 0xf-0x2, BCR_ILCRA, 2, 0x2 },
20   - { 0xf-0xa, BCR_ILCRA, 1, 0xa },
21   - { 0xf-0x5, BCR_ILCRB, 0, 0x5 },
22   - { 0xf-0x8, BCR_ILCRC, 1, 0x8 },
23   - { 0xf-0xc, BCR_ILCRC, 0, 0xc },
24   - { 0xf-0xe, BCR_ILCRD, 3, 0xe },
25   - { 0xf-0x3, BCR_ILCRD, 1, 0x3 }, /* LAN */
26   - { 0xf-0xd, BCR_ILCRE, 2, 0xd },
27   - { 0xf-0x9, BCR_ILCRE, 1, 0x9 },
28   - { 0xf-0x1, BCR_ILCRE, 0, 0x1 },
29   - { 0xf-0xf, BCR_ILCRF, 3, 0xf },
30   - { 0xf-0xb, BCR_ILCRF, 1, 0xb },
31   - { 0xf-0x7, BCR_ILCRG, 3, 0x7 },
32   - { 0xf-0x6, BCR_ILCRG, 2, 0x6 },
33   - { 0xf-0x4, BCR_ILCRG, 1, 0x4 },
  60 + { 0xf-0x2, 0, 8, 0x2 , BCR_ILCRA},
  61 + { 0xf-0xa, 0, 4, 0xa , BCR_ILCRA},
  62 + { 0xf-0x5, 0, 0, 0x5 , BCR_ILCRB},
  63 + { 0xf-0x8, 0, 4, 0x8 , BCR_ILCRC},
  64 + { 0xf-0xc, 0, 0, 0xc , BCR_ILCRC},
  65 + { 0xf-0xe, 0, 12, 0xe , BCR_ILCRD},
  66 + { 0xf-0x3, 0, 4, 0x3 , BCR_ILCRD}, /* LAN */
  67 + { 0xf-0xd, 0, 8, 0xd , BCR_ILCRE},
  68 + { 0xf-0x9, 0, 4, 0x9 , BCR_ILCRE},
  69 + { 0xf-0x1, 0, 0, 0x1 , BCR_ILCRE},
  70 + { 0xf-0xf, 0, 12, 0xf , BCR_ILCRF},
  71 + { 0xf-0xb, 0, 4, 0xb , BCR_ILCRF},
  72 + { 0xf-0x7, 0, 12, 0x7 , BCR_ILCRG},
  73 + { 0xf-0x6, 0, 8, 0x6 , BCR_ILCRG},
  74 + { 0xf-0x4, 0, 4, 0x4 , BCR_ILCRG},
34 75 #else
35   - { 14, BCR_ILCRA, 2, 0x0f-14 },
36   - { 12, BCR_ILCRA, 1, 0x0f-12 },
37   - { 8, BCR_ILCRB, 1, 0x0f- 8 },
38   - { 6, BCR_ILCRC, 3, 0x0f- 6 },
39   - { 5, BCR_ILCRC, 2, 0x0f- 5 },
40   - { 4, BCR_ILCRC, 1, 0x0f- 4 },
41   - { 3, BCR_ILCRC, 0, 0x0f- 3 },
42   - { 1, BCR_ILCRD, 3, 0x0f- 1 },
43   -
44   - { 10, BCR_ILCRD, 1, 0x0f-10 }, /* LAN */
45   -
46   - { 0, BCR_ILCRE, 3, 0x0f- 0 }, /* PCIRQ3 */
47   - { 11, BCR_ILCRE, 2, 0x0f-11 }, /* PCIRQ2 */
48   - { 9, BCR_ILCRE, 1, 0x0f- 9 }, /* PCIRQ1 */
49   - { 7, BCR_ILCRE, 0, 0x0f- 7 }, /* PCIRQ0 */
50   -
  76 + { 14, 0, 8, 0x0f-14 ,BCR_ILCRA},
  77 + { 12, 0, 4, 0x0f-12 ,BCR_ILCRA},
  78 + { 8, 0, 4, 0x0f- 8 ,BCR_ILCRB},
  79 + { 6, 0, 12, 0x0f- 6 ,BCR_ILCRC},
  80 + { 5, 0, 8, 0x0f- 5 ,BCR_ILCRC},
  81 + { 4, 0, 4, 0x0f- 4 ,BCR_ILCRC},
  82 + { 3, 0, 0, 0x0f- 3 ,BCR_ILCRC},
  83 + { 1, 0, 12, 0x0f- 1 ,BCR_ILCRD},
  84 + /* ST NIC */
  85 + { 10, 0, 4, 0x0f-10 ,BCR_ILCRD}, /* LAN */
  86 + /* MRSHPC IRQs setting */
  87 + { 0, 0, 12, 0x0f- 0 ,BCR_ILCRE}, /* PCIRQ3 */
  88 + { 11, 0, 8, 0x0f-11 ,BCR_ILCRE}, /* PCIRQ2 */
  89 + { 9, 0, 4, 0x0f- 9 ,BCR_ILCRE}, /* PCIRQ1 */
  90 + { 7, 0, 0, 0x0f- 7 ,BCR_ILCRE}, /* PCIRQ0 */
51 91 /* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */
52 92 /* NOTE: #2 and #13 are not used on PC */
53   - { 13, BCR_ILCRG, 1, 0x0f-13 }, /* SLOTIRQ2 */
54   - { 2, BCR_ILCRG, 0, 0x0f- 2 }, /* SLOTIRQ1 */
  93 + { 13, 0, 4, 0x0f-13 ,BCR_ILCRG}, /* SLOTIRQ2 */
  94 + { 2, 0, 0, 0x0f- 2 ,BCR_ILCRG}, /* SLOTIRQ1 */
55 95 #endif
56 96 };
57 97  
... ... @@ -81,6 +121,6 @@
81 121 ctrl_outw(0, BCR_ILCRF);
82 122 ctrl_outw(0, BCR_ILCRG);
83 123 #endif
84   - make_ipr_irq(se770x_ipr_map, ARRAY_SIZE(se770x_ipr_map));
  124 + make_se770x_irq(se770x_ipr_map, ARRAY_SIZE(se770x_ipr_map));
85 125 }
arch/sh/boards/se/770x/setup.c
Diff comments   View file @ aa4a5db
1   -/* $Id: setup.c,v 1.1.2.4 2002/03/02 21:57:07 lethal Exp $
2   - *
  1 +/*
3 2 * linux/arch/sh/boards/se/770x/setup.c
4 3 *
5 4 * Copyright (C) 2000 Kazumoto Kojima
... ... @@ -35,11 +34,6 @@
35 34 smsc_config(CURRENT_LDN_INDEX, LDN_FDC);
36 35 smsc_config(ACTIVATE_INDEX, 0x01);
37 36 smsc_config(IRQ_SELECT_INDEX, 6); /* IRQ6 */
38   -
39   - /* IDE1 */
40   - smsc_config(CURRENT_LDN_INDEX, LDN_IDE1);
41   - smsc_config(ACTIVATE_INDEX, 0x01);
42   - smsc_config(IRQ_SELECT_INDEX, 14); /* IRQ14 */
43 37  
44 38 /* AUXIO (GPIO): to use IDE1 */
45 39 smsc_config(CURRENT_LDN_INDEX, LDN_AUXIO);