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Commit aba11fc50c925bbd6fb25d54eae2f86277a3b107

Authored by Kumar Gala
1 parent fc4033b2f8
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

powerpc/e500mc: flush L2 on NAP for e500mc 

If we have an L2CSR register (e500mc) we need to flush the L2 before going
to nap.  We use the HW flush mechanism provided in that register.

The code reuses the CPU_FTR_604_PERF_MON bit as it is no longer used by
any code in the kernel.  Additionally we didn't reuse the exist L2CR
feature bit as this is intended for the 7xxx L2CR register and L2CSR
is part of the new Freescale "Book-E" registers.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Showing 3 changed files with 30 additions and 4 deletions Side-by-side Diff

arch/powerpc/kernel/idle_e500.S
Diff comments   View file @ aba11fc
... ... @@ -47,6 +47,15 @@
47 47 mtlr r0
48 48 lis r3,HID0_NAP@h
49 49 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
  50 +BEGIN_FTR_SECTION
  51 + msync
  52 + li r7,L2CSR0_L2FL@l
  53 + mtspr SPRN_L2CSR0,r7
  54 +2:
  55 + mfspr r7,SPRN_L2CSR0
  56 + andi. r4,r7,L2CSR0_L2FL@l
  57 + bne 2b
  58 +END_FTR_SECTION_IFSET(CPU_FTR_L2CSR|CPU_FTR_CAN_NAP)
50 59 1:
51 60 /* Go to NAP or DOZE now */
52 61 mfspr r4,SPRN_HID0
include/asm-powerpc/cputable.h
Diff comments   View file @ aba11fc
... ... @@ -132,7 +132,7 @@
132 132 #define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
133 133 #define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
134 134 #define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
135   -#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
  135 +#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080)
136 136 #define CPU_FTR_601 ASM_CONST(0x0000000000000100)
137 137 #define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
138 138 #define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
... ... @@ -245,8 +245,7 @@
245 245 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
246 246 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
247 247 #define CPU_FTRS_604 (CPU_FTR_COMMON | \
248   - CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
249   - CPU_FTR_PPC_LE)
  248 + CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPC_LE)
250 249 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
251 250 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
252 251 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
... ... @@ -353,7 +352,8 @@
353 352 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \
354 353 CPU_FTR_NODSISRALIGN)
355 354 #define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
356   - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
  355 + CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \
  356 + CPU_FTR_L2CSR)
357 357 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
358 358  
359 359 /* 64-bit CPUs */
include/asm-powerpc/reg_booke.h
Diff comments   View file @ aba11fc
... ... @@ -80,6 +80,7 @@
80 80 #define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */
81 81 #define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */
82 82 #define SPRN_SPRG9 0x25D /* Special Purpose Register General 9 */
  83 +#define SPRN_L1CSR2 0x25E /* L1 Cache Control and Status Register 2 */
83 84 #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
84 85 #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
85 86 #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
... ... @@ -110,6 +111,8 @@
110 111 #define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */
111 112 #define SPRN_PIT 0x3DB /* Programmable Interval Timer */
112 113 #define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */
  114 +#define SPRN_L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */
  115 +#define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */
113 116 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
114 117 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
115 118 #define SPRN_SVR 0x3FF /* System Version Register */
... ... @@ -392,6 +395,20 @@
392 395 #define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */
393 396 #define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
394 397 #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
  398 +
  399 +/* Bit definitions for L2CSR0. */
  400 +#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
  401 +#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
  402 +#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */
  403 +#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
  404 +#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
  405 +#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */
  406 +#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */
  407 +#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */
  408 +#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
  409 +#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
  410 +#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */
  411 +#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */
395 412  
396 413 /* Bit definitions for SGR. */
397 414 #define SGR_NORMAL 0 /* Speculative fetching allowed. */