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Commit ac68936652819dad1e5decefddb1c7fc1d7bc364

Authored by Maxime Ripard
Committed by Linus Walleij
1 parent 44abb933f7
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

pinctrl: sunxi: Add Allwinner A10s pins 

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Showing 2 changed files with 646 additions and 0 deletions Inline Diff

drivers/pinctrl/pinctrl-sunxi-pins.h
Diff comments   View file @ ac68936
1 /* 1 /*
2 * Allwinner A1X SoCs pinctrl driver. 2 * Allwinner A1X SoCs pinctrl driver.
3 * 3 *
4 * Copyright (C) 2012 Maxime Ripard 4 * Copyright (C) 2012 Maxime Ripard
5 * 5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com> 6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 * 7 *
8 * This file is licensed under the terms of the GNU General Public 8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any 9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied. 10 * warranty of any kind, whether express or implied.
11 */ 11 */
12 12
13 #ifndef __PINCTRL_SUNXI_PINS_H 13 #ifndef __PINCTRL_SUNXI_PINS_H
14 #define __PINCTRL_SUNXI_PINS_H 14 #define __PINCTRL_SUNXI_PINS_H
15 15
16 #include "pinctrl-sunxi.h" 16 #include "pinctrl-sunxi.h"
17 17
18 static const struct sunxi_desc_pin sun4i_a10_pins[] = { 18 static const struct sunxi_desc_pin sun4i_a10_pins[] = {
19 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0, 19 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
20 SUNXI_FUNCTION(0x0, "gpio_in"), 20 SUNXI_FUNCTION(0x0, "gpio_in"),
21 SUNXI_FUNCTION(0x1, "gpio_out"), 21 SUNXI_FUNCTION(0x1, "gpio_out"),
22 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */ 22 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
23 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */ 23 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
24 SUNXI_FUNCTION(0x4, "uart2")), /* RTS */ 24 SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
25 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1, 25 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
26 SUNXI_FUNCTION(0x0, "gpio_in"), 26 SUNXI_FUNCTION(0x0, "gpio_in"),
27 SUNXI_FUNCTION(0x1, "gpio_out"), 27 SUNXI_FUNCTION(0x1, "gpio_out"),
28 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */ 28 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
29 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ 29 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
30 SUNXI_FUNCTION(0x4, "uart2")), /* CTS */ 30 SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
31 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2, 31 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
32 SUNXI_FUNCTION(0x0, "gpio_in"), 32 SUNXI_FUNCTION(0x0, "gpio_in"),
33 SUNXI_FUNCTION(0x1, "gpio_out"), 33 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */ 34 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
35 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ 35 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
36 SUNXI_FUNCTION(0x4, "uart2")), /* TX */ 36 SUNXI_FUNCTION(0x4, "uart2")), /* TX */
37 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3, 37 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
38 SUNXI_FUNCTION(0x0, "gpio_in"), 38 SUNXI_FUNCTION(0x0, "gpio_in"),
39 SUNXI_FUNCTION(0x1, "gpio_out"), 39 SUNXI_FUNCTION(0x1, "gpio_out"),
40 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */ 40 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
41 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ 41 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
42 SUNXI_FUNCTION(0x4, "uart2")), /* RX */ 42 SUNXI_FUNCTION(0x4, "uart2")), /* RX */
43 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4, 43 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
44 SUNXI_FUNCTION(0x0, "gpio_in"), 44 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out"), 45 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */ 46 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
47 SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */ 47 SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */
48 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5, 48 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
49 SUNXI_FUNCTION(0x0, "gpio_in"), 49 SUNXI_FUNCTION(0x0, "gpio_in"),
50 SUNXI_FUNCTION(0x1, "gpio_out"), 50 SUNXI_FUNCTION(0x1, "gpio_out"),
51 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */ 51 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
52 SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */ 52 SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */
53 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6, 53 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
54 SUNXI_FUNCTION(0x0, "gpio_in"), 54 SUNXI_FUNCTION(0x0, "gpio_in"),
55 SUNXI_FUNCTION(0x1, "gpio_out"), 55 SUNXI_FUNCTION(0x1, "gpio_out"),
56 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */ 56 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
57 SUNXI_FUNCTION(0x3, "spi3")), /* CLK */ 57 SUNXI_FUNCTION(0x3, "spi3")), /* CLK */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7, 58 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
59 SUNXI_FUNCTION(0x0, "gpio_in"), 59 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out"), 60 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */ 61 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
62 SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */ 62 SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */
63 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8, 63 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
64 SUNXI_FUNCTION(0x0, "gpio_in"), 64 SUNXI_FUNCTION(0x0, "gpio_in"),
65 SUNXI_FUNCTION(0x1, "gpio_out"), 65 SUNXI_FUNCTION(0x1, "gpio_out"),
66 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */ 66 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
67 SUNXI_FUNCTION(0x3, "spi3")), /* MISO */ 67 SUNXI_FUNCTION(0x3, "spi3")), /* MISO */
68 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9, 68 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
69 SUNXI_FUNCTION(0x0, "gpio_in"), 69 SUNXI_FUNCTION(0x0, "gpio_in"),
70 SUNXI_FUNCTION(0x1, "gpio_out"), 70 SUNXI_FUNCTION(0x1, "gpio_out"),
71 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */ 71 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
72 SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */ 72 SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */
73 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10, 73 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
74 SUNXI_FUNCTION(0x0, "gpio_in"), 74 SUNXI_FUNCTION(0x0, "gpio_in"),
75 SUNXI_FUNCTION(0x1, "gpio_out"), 75 SUNXI_FUNCTION(0x1, "gpio_out"),
76 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */ 76 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
77 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 77 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
78 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11, 78 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
79 SUNXI_FUNCTION(0x0, "gpio_in"), 79 SUNXI_FUNCTION(0x0, "gpio_in"),
80 SUNXI_FUNCTION(0x1, "gpio_out"), 80 SUNXI_FUNCTION(0x1, "gpio_out"),
81 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */ 81 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
82 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 82 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
83 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12, 83 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
84 SUNXI_FUNCTION(0x0, "gpio_in"), 84 SUNXI_FUNCTION(0x0, "gpio_in"),
85 SUNXI_FUNCTION(0x1, "gpio_out"), 85 SUNXI_FUNCTION(0x1, "gpio_out"),
86 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */ 86 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
87 SUNXI_FUNCTION(0x3, "uart6"), /* TX */ 87 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
88 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ 88 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
89 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13, 89 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
90 SUNXI_FUNCTION(0x0, "gpio_in"), 90 SUNXI_FUNCTION(0x0, "gpio_in"),
91 SUNXI_FUNCTION(0x1, "gpio_out"), 91 SUNXI_FUNCTION(0x1, "gpio_out"),
92 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */ 92 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
93 SUNXI_FUNCTION(0x3, "uart6"), /* RX */ 93 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
94 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ 94 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
95 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14, 95 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
96 SUNXI_FUNCTION(0x0, "gpio_in"), 96 SUNXI_FUNCTION(0x0, "gpio_in"),
97 SUNXI_FUNCTION(0x1, "gpio_out"), 97 SUNXI_FUNCTION(0x1, "gpio_out"),
98 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */ 98 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
99 SUNXI_FUNCTION(0x3, "uart7"), /* TX */ 99 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
100 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ 100 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
101 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15, 101 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
102 SUNXI_FUNCTION(0x0, "gpio_in"), 102 SUNXI_FUNCTION(0x0, "gpio_in"),
103 SUNXI_FUNCTION(0x1, "gpio_out"), 103 SUNXI_FUNCTION(0x1, "gpio_out"),
104 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */ 104 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
105 SUNXI_FUNCTION(0x3, "uart7"), /* RX */ 105 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
106 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ 106 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
107 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16, 107 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
108 SUNXI_FUNCTION(0x0, "gpio_in"), 108 SUNXI_FUNCTION(0x0, "gpio_in"),
109 SUNXI_FUNCTION(0x1, "gpio_out"), 109 SUNXI_FUNCTION(0x1, "gpio_out"),
110 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */ 110 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
111 SUNXI_FUNCTION(0x3, "can"), /* TX */ 111 SUNXI_FUNCTION(0x3, "can"), /* TX */
112 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ 112 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
113 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17, 113 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
114 SUNXI_FUNCTION(0x0, "gpio_in"), 114 SUNXI_FUNCTION(0x0, "gpio_in"),
115 SUNXI_FUNCTION(0x1, "gpio_out"), 115 SUNXI_FUNCTION(0x1, "gpio_out"),
116 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */ 116 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
117 SUNXI_FUNCTION(0x3, "can"), /* RX */ 117 SUNXI_FUNCTION(0x3, "can"), /* RX */
118 SUNXI_FUNCTION(0x4, "uart1")), /* RING */ 118 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
119 /* Hole */ 119 /* Hole */
120 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, 120 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
121 SUNXI_FUNCTION(0x0, "gpio_in"), 121 SUNXI_FUNCTION(0x0, "gpio_in"),
122 SUNXI_FUNCTION(0x1, "gpio_out"), 122 SUNXI_FUNCTION(0x1, "gpio_out"),
123 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ 123 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, 124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
125 SUNXI_FUNCTION(0x0, "gpio_in"), 125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out"), 126 SUNXI_FUNCTION(0x1, "gpio_out"),
127 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ 127 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
128 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, 128 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
129 SUNXI_FUNCTION(0x0, "gpio_in"), 129 SUNXI_FUNCTION(0x0, "gpio_in"),
130 SUNXI_FUNCTION(0x1, "gpio_out"), 130 SUNXI_FUNCTION(0x1, "gpio_out"),
131 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */ 131 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
132 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, 132 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
133 SUNXI_FUNCTION(0x0, "gpio_in"), 133 SUNXI_FUNCTION(0x0, "gpio_in"),
134 SUNXI_FUNCTION(0x1, "gpio_out"), 134 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "ir0")), /* TX */ 135 SUNXI_FUNCTION(0x2, "ir0")), /* TX */
136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, 136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
137 SUNXI_FUNCTION(0x0, "gpio_in"), 137 SUNXI_FUNCTION(0x0, "gpio_in"),
138 SUNXI_FUNCTION(0x1, "gpio_out"), 138 SUNXI_FUNCTION(0x1, "gpio_out"),
139 SUNXI_FUNCTION(0x2, "ir0")), /* RX */ 139 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
140 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5, 140 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
141 SUNXI_FUNCTION(0x0, "gpio_in"), 141 SUNXI_FUNCTION(0x0, "gpio_in"),
142 SUNXI_FUNCTION(0x1, "gpio_out"), 142 SUNXI_FUNCTION(0x1, "gpio_out"),
143 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ 143 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
144 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */ 144 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6, 145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
146 SUNXI_FUNCTION(0x0, "gpio_in"), 146 SUNXI_FUNCTION(0x0, "gpio_in"),
147 SUNXI_FUNCTION(0x1, "gpio_out"), 147 SUNXI_FUNCTION(0x1, "gpio_out"),
148 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ 148 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
149 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */ 149 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7, 150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
151 SUNXI_FUNCTION(0x0, "gpio_in"), 151 SUNXI_FUNCTION(0x0, "gpio_in"),
152 SUNXI_FUNCTION(0x1, "gpio_out"), 152 SUNXI_FUNCTION(0x1, "gpio_out"),
153 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */ 153 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
154 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */ 154 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8, 155 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
156 SUNXI_FUNCTION(0x0, "gpio_in"), 156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"), 157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */ 158 SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */
159 SUNXI_FUNCTION(0x3, "ac97")), /* DO */ 159 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9, 160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
161 SUNXI_FUNCTION(0x0, "gpio_in"), 161 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"), 162 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */ 163 SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */
164 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, 164 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
165 SUNXI_FUNCTION(0x0, "gpio_in"), 165 SUNXI_FUNCTION(0x0, "gpio_in"),
166 SUNXI_FUNCTION(0x1, "gpio_out"), 166 SUNXI_FUNCTION(0x1, "gpio_out"),
167 SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */ 167 SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */
168 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11, 168 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
169 SUNXI_FUNCTION(0x0, "gpio_in"), 169 SUNXI_FUNCTION(0x0, "gpio_in"),
170 SUNXI_FUNCTION(0x1, "gpio_out"), 170 SUNXI_FUNCTION(0x1, "gpio_out"),
171 SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */ 171 SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */
172 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12, 172 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
173 SUNXI_FUNCTION(0x0, "gpio_in"), 173 SUNXI_FUNCTION(0x0, "gpio_in"),
174 SUNXI_FUNCTION(0x1, "gpio_out"), 174 SUNXI_FUNCTION(0x1, "gpio_out"),
175 SUNXI_FUNCTION(0x2, "i2s"), /* DI */ 175 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
176 SUNXI_FUNCTION(0x3, "ac97")), /* DI */ 176 SUNXI_FUNCTION(0x3, "ac97")), /* DI */
177 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13, 177 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
178 SUNXI_FUNCTION(0x0, "gpio_in"), 178 SUNXI_FUNCTION(0x0, "gpio_in"),
179 SUNXI_FUNCTION(0x1, "gpio_out"), 179 SUNXI_FUNCTION(0x1, "gpio_out"),
180 SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */ 180 SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */
181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14, 181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
182 SUNXI_FUNCTION(0x0, "gpio_in"), 182 SUNXI_FUNCTION(0x0, "gpio_in"),
183 SUNXI_FUNCTION(0x1, "gpio_out"), 183 SUNXI_FUNCTION(0x1, "gpio_out"),
184 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ 184 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
185 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */ 185 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
186 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, 186 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
187 SUNXI_FUNCTION(0x0, "gpio_in"), 187 SUNXI_FUNCTION(0x0, "gpio_in"),
188 SUNXI_FUNCTION(0x1, "gpio_out"), 188 SUNXI_FUNCTION(0x1, "gpio_out"),
189 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ 189 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
190 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */ 190 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
191 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, 191 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
192 SUNXI_FUNCTION(0x0, "gpio_in"), 192 SUNXI_FUNCTION(0x0, "gpio_in"),
193 SUNXI_FUNCTION(0x1, "gpio_out"), 193 SUNXI_FUNCTION(0x1, "gpio_out"),
194 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ 194 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
195 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */ 195 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
196 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, 196 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
197 SUNXI_FUNCTION(0x0, "gpio_in"), 197 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out"), 198 SUNXI_FUNCTION(0x1, "gpio_out"),
199 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ 199 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
200 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */ 200 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
201 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, 201 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
202 SUNXI_FUNCTION(0x0, "gpio_in"), 202 SUNXI_FUNCTION(0x0, "gpio_in"),
203 SUNXI_FUNCTION(0x1, "gpio_out"), 203 SUNXI_FUNCTION(0x1, "gpio_out"),
204 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ 204 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
205 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19, 205 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
206 SUNXI_FUNCTION(0x0, "gpio_in"), 206 SUNXI_FUNCTION(0x0, "gpio_in"),
207 SUNXI_FUNCTION(0x1, "gpio_out"), 207 SUNXI_FUNCTION(0x1, "gpio_out"),
208 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ 208 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
209 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20, 209 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
210 SUNXI_FUNCTION(0x0, "gpio_in"), 210 SUNXI_FUNCTION(0x0, "gpio_in"),
211 SUNXI_FUNCTION(0x1, "gpio_out"), 211 SUNXI_FUNCTION(0x1, "gpio_out"),
212 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ 212 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21, 213 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
214 SUNXI_FUNCTION(0x0, "gpio_in"), 214 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"), 215 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ 216 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22, 217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
218 SUNXI_FUNCTION(0x0, "gpio_in"), 218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"), 219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "uart0"), /* TX */ 220 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
221 SUNXI_FUNCTION(0x3, "ir1")), /* TX */ 221 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
222 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23, 222 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
223 SUNXI_FUNCTION(0x0, "gpio_in"), 223 SUNXI_FUNCTION(0x0, "gpio_in"),
224 SUNXI_FUNCTION(0x1, "gpio_out"), 224 SUNXI_FUNCTION(0x1, "gpio_out"),
225 SUNXI_FUNCTION(0x2, "uart0"), /* RX */ 225 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
226 SUNXI_FUNCTION(0x3, "ir1")), /* RX */ 226 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
227 /* Hole */ 227 /* Hole */
228 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, 228 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
229 SUNXI_FUNCTION(0x0, "gpio_in"), 229 SUNXI_FUNCTION(0x0, "gpio_in"),
230 SUNXI_FUNCTION(0x1, "gpio_out"), 230 SUNXI_FUNCTION(0x1, "gpio_out"),
231 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ 231 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
232 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ 232 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
233 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, 233 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
234 SUNXI_FUNCTION(0x0, "gpio_in"), 234 SUNXI_FUNCTION(0x0, "gpio_in"),
235 SUNXI_FUNCTION(0x1, "gpio_out"), 235 SUNXI_FUNCTION(0x1, "gpio_out"),
236 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ 236 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
237 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ 237 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
238 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, 238 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
239 SUNXI_FUNCTION(0x0, "gpio_in"), 239 SUNXI_FUNCTION(0x0, "gpio_in"),
240 SUNXI_FUNCTION(0x1, "gpio_out"), 240 SUNXI_FUNCTION(0x1, "gpio_out"),
241 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ 241 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
242 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */ 242 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
243 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, 243 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
244 SUNXI_FUNCTION(0x0, "gpio_in"), 244 SUNXI_FUNCTION(0x0, "gpio_in"),
245 SUNXI_FUNCTION(0x1, "gpio_out"), 245 SUNXI_FUNCTION(0x1, "gpio_out"),
246 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */ 246 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
247 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, 247 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
248 SUNXI_FUNCTION(0x0, "gpio_in"), 248 SUNXI_FUNCTION(0x0, "gpio_in"),
249 SUNXI_FUNCTION(0x1, "gpio_out"), 249 SUNXI_FUNCTION(0x1, "gpio_out"),
250 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ 250 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
251 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, 251 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
252 SUNXI_FUNCTION(0x0, "gpio_in"), 252 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x1, "gpio_out"), 253 SUNXI_FUNCTION(0x1, "gpio_out"),
254 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */ 254 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
255 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, 255 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
256 SUNXI_FUNCTION(0x0, "gpio_in"), 256 SUNXI_FUNCTION(0x0, "gpio_in"),
257 SUNXI_FUNCTION(0x1, "gpio_out"), 257 SUNXI_FUNCTION(0x1, "gpio_out"),
258 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ 258 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
259 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ 259 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
260 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, 260 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
261 SUNXI_FUNCTION(0x0, "gpio_in"), 261 SUNXI_FUNCTION(0x0, "gpio_in"),
262 SUNXI_FUNCTION(0x1, "gpio_out"), 262 SUNXI_FUNCTION(0x1, "gpio_out"),
263 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ 263 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
264 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ 264 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
265 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, 265 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
266 SUNXI_FUNCTION(0x0, "gpio_in"), 266 SUNXI_FUNCTION(0x0, "gpio_in"),
267 SUNXI_FUNCTION(0x1, "gpio_out"), 267 SUNXI_FUNCTION(0x1, "gpio_out"),
268 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ 268 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
269 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ 269 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
270 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, 270 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
271 SUNXI_FUNCTION(0x0, "gpio_in"), 271 SUNXI_FUNCTION(0x0, "gpio_in"),
272 SUNXI_FUNCTION(0x1, "gpio_out"), 272 SUNXI_FUNCTION(0x1, "gpio_out"),
273 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ 273 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
274 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ 274 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
275 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, 275 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
276 SUNXI_FUNCTION(0x0, "gpio_in"), 276 SUNXI_FUNCTION(0x0, "gpio_in"),
277 SUNXI_FUNCTION(0x1, "gpio_out"), 277 SUNXI_FUNCTION(0x1, "gpio_out"),
278 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ 278 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
279 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ 279 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
280 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, 280 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
281 SUNXI_FUNCTION(0x0, "gpio_in"), 281 SUNXI_FUNCTION(0x0, "gpio_in"),
282 SUNXI_FUNCTION(0x1, "gpio_out"), 282 SUNXI_FUNCTION(0x1, "gpio_out"),
283 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ 283 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
284 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ 284 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
285 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, 285 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
286 SUNXI_FUNCTION(0x0, "gpio_in"), 286 SUNXI_FUNCTION(0x0, "gpio_in"),
287 SUNXI_FUNCTION(0x1, "gpio_out"), 287 SUNXI_FUNCTION(0x1, "gpio_out"),
288 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */ 288 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
289 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, 289 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
290 SUNXI_FUNCTION(0x0, "gpio_in"), 290 SUNXI_FUNCTION(0x0, "gpio_in"),
291 SUNXI_FUNCTION(0x1, "gpio_out"), 291 SUNXI_FUNCTION(0x1, "gpio_out"),
292 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */ 292 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, 293 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
294 SUNXI_FUNCTION(0x0, "gpio_in"), 294 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out"), 295 SUNXI_FUNCTION(0x1, "gpio_out"),
296 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */ 296 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
297 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, 297 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
298 SUNXI_FUNCTION(0x0, "gpio_in"), 298 SUNXI_FUNCTION(0x0, "gpio_in"),
299 SUNXI_FUNCTION(0x1, "gpio_out"), 299 SUNXI_FUNCTION(0x1, "gpio_out"),
300 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */ 300 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
301 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16, 301 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
302 SUNXI_FUNCTION(0x0, "gpio_in"), 302 SUNXI_FUNCTION(0x0, "gpio_in"),
303 SUNXI_FUNCTION(0x1, "gpio_out"), 303 SUNXI_FUNCTION(0x1, "gpio_out"),
304 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */ 304 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
305 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17, 305 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
306 SUNXI_FUNCTION(0x0, "gpio_in"), 306 SUNXI_FUNCTION(0x0, "gpio_in"),
307 SUNXI_FUNCTION(0x1, "gpio_out"), 307 SUNXI_FUNCTION(0x1, "gpio_out"),
308 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */ 308 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18, 309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
310 SUNXI_FUNCTION(0x0, "gpio_in"), 310 SUNXI_FUNCTION(0x0, "gpio_in"),
311 SUNXI_FUNCTION(0x1, "gpio_out"), 311 SUNXI_FUNCTION(0x1, "gpio_out"),
312 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */ 312 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
313 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, 313 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
314 SUNXI_FUNCTION(0x0, "gpio_in"), 314 SUNXI_FUNCTION(0x0, "gpio_in"),
315 SUNXI_FUNCTION(0x1, "gpio_out"), 315 SUNXI_FUNCTION(0x1, "gpio_out"),
316 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ 316 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
317 SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */ 317 SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20, 318 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
319 SUNXI_FUNCTION(0x0, "gpio_in"), 319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"), 320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */ 321 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
322 SUNXI_FUNCTION(0x3, "spi2")), /* CLK */ 322 SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
323 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21, 323 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
324 SUNXI_FUNCTION(0x0, "gpio_in"), 324 SUNXI_FUNCTION(0x0, "gpio_in"),
325 SUNXI_FUNCTION(0x1, "gpio_out"), 325 SUNXI_FUNCTION(0x1, "gpio_out"),
326 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */ 326 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
327 SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */ 327 SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
328 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22, 328 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
329 SUNXI_FUNCTION(0x0, "gpio_in"), 329 SUNXI_FUNCTION(0x0, "gpio_in"),
330 SUNXI_FUNCTION(0x1, "gpio_out"), 330 SUNXI_FUNCTION(0x1, "gpio_out"),
331 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */ 331 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
332 SUNXI_FUNCTION(0x3, "spi2")), /* MISO */ 332 SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
333 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23, 333 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
334 SUNXI_FUNCTION(0x0, "gpio_in"), 334 SUNXI_FUNCTION(0x0, "gpio_in"),
335 SUNXI_FUNCTION(0x1, "gpio_out"), 335 SUNXI_FUNCTION(0x1, "gpio_out"),
336 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ 336 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
337 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24, 337 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
338 SUNXI_FUNCTION(0x0, "gpio_in"), 338 SUNXI_FUNCTION(0x0, "gpio_in"),
339 SUNXI_FUNCTION(0x1, "gpio_out"), 339 SUNXI_FUNCTION(0x1, "gpio_out"),
340 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */ 340 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
341 /* Hole */ 341 /* Hole */
342 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0, 342 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
343 SUNXI_FUNCTION(0x0, "gpio_in"), 343 SUNXI_FUNCTION(0x0, "gpio_in"),
344 SUNXI_FUNCTION(0x1, "gpio_out"), 344 SUNXI_FUNCTION(0x1, "gpio_out"),
345 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ 345 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
346 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ 346 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
347 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1, 347 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
348 SUNXI_FUNCTION(0x0, "gpio_in"), 348 SUNXI_FUNCTION(0x0, "gpio_in"),
349 SUNXI_FUNCTION(0x1, "gpio_out"), 349 SUNXI_FUNCTION(0x1, "gpio_out"),
350 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ 350 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
351 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ 351 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
352 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, 352 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
353 SUNXI_FUNCTION(0x0, "gpio_in"), 353 SUNXI_FUNCTION(0x0, "gpio_in"),
354 SUNXI_FUNCTION(0x1, "gpio_out"), 354 SUNXI_FUNCTION(0x1, "gpio_out"),
355 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ 355 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
356 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ 356 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
357 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, 357 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
358 SUNXI_FUNCTION(0x0, "gpio_in"), 358 SUNXI_FUNCTION(0x0, "gpio_in"),
359 SUNXI_FUNCTION(0x1, "gpio_out"), 359 SUNXI_FUNCTION(0x1, "gpio_out"),
360 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ 360 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
361 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ 361 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
362 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, 362 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
363 SUNXI_FUNCTION(0x0, "gpio_in"), 363 SUNXI_FUNCTION(0x0, "gpio_in"),
364 SUNXI_FUNCTION(0x1, "gpio_out"), 364 SUNXI_FUNCTION(0x1, "gpio_out"),
365 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ 365 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
366 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ 366 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
367 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, 367 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
368 SUNXI_FUNCTION(0x0, "gpio_in"), 368 SUNXI_FUNCTION(0x0, "gpio_in"),
369 SUNXI_FUNCTION(0x1, "gpio_out"), 369 SUNXI_FUNCTION(0x1, "gpio_out"),
370 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ 370 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
371 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ 371 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
372 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, 372 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
373 SUNXI_FUNCTION(0x0, "gpio_in"), 373 SUNXI_FUNCTION(0x0, "gpio_in"),
374 SUNXI_FUNCTION(0x1, "gpio_out"), 374 SUNXI_FUNCTION(0x1, "gpio_out"),
375 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ 375 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
376 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ 376 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
377 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, 377 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
378 SUNXI_FUNCTION(0x0, "gpio_in"), 378 SUNXI_FUNCTION(0x0, "gpio_in"),
379 SUNXI_FUNCTION(0x1, "gpio_out"), 379 SUNXI_FUNCTION(0x1, "gpio_out"),
380 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ 380 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
381 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ 381 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
382 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8, 382 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
383 SUNXI_FUNCTION(0x0, "gpio_in"), 383 SUNXI_FUNCTION(0x0, "gpio_in"),
384 SUNXI_FUNCTION(0x1, "gpio_out"), 384 SUNXI_FUNCTION(0x1, "gpio_out"),
385 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ 385 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
386 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ 386 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
387 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9, 387 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
388 SUNXI_FUNCTION(0x0, "gpio_in"), 388 SUNXI_FUNCTION(0x0, "gpio_in"),
389 SUNXI_FUNCTION(0x1, "gpio_out"), 389 SUNXI_FUNCTION(0x1, "gpio_out"),
390 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ 390 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
391 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */ 391 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
392 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, 392 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
393 SUNXI_FUNCTION(0x0, "gpio_in"), 393 SUNXI_FUNCTION(0x0, "gpio_in"),
394 SUNXI_FUNCTION(0x1, "gpio_out"), 394 SUNXI_FUNCTION(0x1, "gpio_out"),
395 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ 395 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
396 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */ 396 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
397 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, 397 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
398 SUNXI_FUNCTION(0x0, "gpio_in"), 398 SUNXI_FUNCTION(0x0, "gpio_in"),
399 SUNXI_FUNCTION(0x1, "gpio_out"), 399 SUNXI_FUNCTION(0x1, "gpio_out"),
400 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ 400 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
401 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */ 401 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
402 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, 402 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
403 SUNXI_FUNCTION(0x0, "gpio_in"), 403 SUNXI_FUNCTION(0x0, "gpio_in"),
404 SUNXI_FUNCTION(0x1, "gpio_out"), 404 SUNXI_FUNCTION(0x1, "gpio_out"),
405 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ 405 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
406 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */ 406 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
407 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, 407 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
408 SUNXI_FUNCTION(0x0, "gpio_in"), 408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out"), 409 SUNXI_FUNCTION(0x1, "gpio_out"),
410 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ 410 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
411 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */ 411 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
412 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, 412 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
413 SUNXI_FUNCTION(0x0, "gpio_in"), 413 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out"), 414 SUNXI_FUNCTION(0x1, "gpio_out"),
415 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ 415 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
416 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */ 416 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
417 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, 417 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
418 SUNXI_FUNCTION(0x0, "gpio_in"), 418 SUNXI_FUNCTION(0x0, "gpio_in"),
419 SUNXI_FUNCTION(0x1, "gpio_out"), 419 SUNXI_FUNCTION(0x1, "gpio_out"),
420 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ 420 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
421 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */ 421 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
422 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16, 422 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
423 SUNXI_FUNCTION(0x0, "gpio_in"), 423 SUNXI_FUNCTION(0x0, "gpio_in"),
424 SUNXI_FUNCTION(0x1, "gpio_out"), 424 SUNXI_FUNCTION(0x1, "gpio_out"),
425 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ 425 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
426 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */ 426 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
427 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17, 427 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
428 SUNXI_FUNCTION(0x0, "gpio_in"), 428 SUNXI_FUNCTION(0x0, "gpio_in"),
429 SUNXI_FUNCTION(0x1, "gpio_out"), 429 SUNXI_FUNCTION(0x1, "gpio_out"),
430 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ 430 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
431 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */ 431 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
432 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, 432 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
433 SUNXI_FUNCTION(0x0, "gpio_in"), 433 SUNXI_FUNCTION(0x0, "gpio_in"),
434 SUNXI_FUNCTION(0x1, "gpio_out"), 434 SUNXI_FUNCTION(0x1, "gpio_out"),
435 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ 435 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
436 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */ 436 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
437 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, 437 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
438 SUNXI_FUNCTION(0x0, "gpio_in"), 438 SUNXI_FUNCTION(0x0, "gpio_in"),
439 SUNXI_FUNCTION(0x1, "gpio_out"), 439 SUNXI_FUNCTION(0x1, "gpio_out"),
440 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ 440 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
441 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */ 441 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
442 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, 442 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
443 SUNXI_FUNCTION(0x0, "gpio_in"), 443 SUNXI_FUNCTION(0x0, "gpio_in"),
444 SUNXI_FUNCTION(0x1, "gpio_out"), 444 SUNXI_FUNCTION(0x1, "gpio_out"),
445 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ 445 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
446 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */ 446 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
447 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, 447 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
448 SUNXI_FUNCTION(0x0, "gpio_in"), 448 SUNXI_FUNCTION(0x0, "gpio_in"),
449 SUNXI_FUNCTION(0x1, "gpio_out"), 449 SUNXI_FUNCTION(0x1, "gpio_out"),
450 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ 450 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
451 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */ 451 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
452 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, 452 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
453 SUNXI_FUNCTION(0x0, "gpio_in"), 453 SUNXI_FUNCTION(0x0, "gpio_in"),
454 SUNXI_FUNCTION(0x1, "gpio_out"), 454 SUNXI_FUNCTION(0x1, "gpio_out"),
455 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ 455 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
456 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */ 456 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
457 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, 457 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
458 SUNXI_FUNCTION(0x0, "gpio_in"), 458 SUNXI_FUNCTION(0x0, "gpio_in"),
459 SUNXI_FUNCTION(0x1, "gpio_out"), 459 SUNXI_FUNCTION(0x1, "gpio_out"),
460 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ 460 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
461 SUNXI_FUNCTION(0x3, "sim")), /* DET */ 461 SUNXI_FUNCTION(0x3, "sim")), /* DET */
462 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, 462 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
463 SUNXI_FUNCTION(0x0, "gpio_in"), 463 SUNXI_FUNCTION(0x0, "gpio_in"),
464 SUNXI_FUNCTION(0x1, "gpio_out"), 464 SUNXI_FUNCTION(0x1, "gpio_out"),
465 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ 465 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
466 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */ 466 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
467 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, 467 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
468 SUNXI_FUNCTION(0x0, "gpio_in"), 468 SUNXI_FUNCTION(0x0, "gpio_in"),
469 SUNXI_FUNCTION(0x1, "gpio_out"), 469 SUNXI_FUNCTION(0x1, "gpio_out"),
470 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ 470 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
471 SUNXI_FUNCTION(0x3, "sim")), /* RST */ 471 SUNXI_FUNCTION(0x3, "sim")), /* RST */
472 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, 472 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
473 SUNXI_FUNCTION(0x0, "gpio_in"), 473 SUNXI_FUNCTION(0x0, "gpio_in"),
474 SUNXI_FUNCTION(0x1, "gpio_out"), 474 SUNXI_FUNCTION(0x1, "gpio_out"),
475 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ 475 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
476 SUNXI_FUNCTION(0x3, "sim")), /* SCK */ 476 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
477 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, 477 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
478 SUNXI_FUNCTION(0x0, "gpio_in"), 478 SUNXI_FUNCTION(0x0, "gpio_in"),
479 SUNXI_FUNCTION(0x1, "gpio_out"), 479 SUNXI_FUNCTION(0x1, "gpio_out"),
480 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ 480 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
481 SUNXI_FUNCTION(0x3, "sim")), /* SDA */ 481 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
482 /* Hole */ 482 /* Hole */
483 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, 483 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
484 SUNXI_FUNCTION(0x0, "gpio_in"), 484 SUNXI_FUNCTION(0x0, "gpio_in"),
485 SUNXI_FUNCTION(0x1, "gpio_out"), 485 SUNXI_FUNCTION(0x1, "gpio_out"),
486 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ 486 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
487 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */ 487 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
488 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, 488 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
489 SUNXI_FUNCTION(0x0, "gpio_in"), 489 SUNXI_FUNCTION(0x0, "gpio_in"),
490 SUNXI_FUNCTION(0x1, "gpio_out"), 490 SUNXI_FUNCTION(0x1, "gpio_out"),
491 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ 491 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
492 SUNXI_FUNCTION(0x3, "csi0")), /* CK */ 492 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
493 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, 493 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
494 SUNXI_FUNCTION(0x0, "gpio_in"), 494 SUNXI_FUNCTION(0x0, "gpio_in"),
495 SUNXI_FUNCTION(0x1, "gpio_out"), 495 SUNXI_FUNCTION(0x1, "gpio_out"),
496 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ 496 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
497 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */ 497 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
498 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, 498 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
499 SUNXI_FUNCTION(0x0, "gpio_in"), 499 SUNXI_FUNCTION(0x0, "gpio_in"),
500 SUNXI_FUNCTION(0x1, "gpio_out"), 500 SUNXI_FUNCTION(0x1, "gpio_out"),
501 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ 501 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
502 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */ 502 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, 503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
504 SUNXI_FUNCTION(0x0, "gpio_in"), 504 SUNXI_FUNCTION(0x0, "gpio_in"),
505 SUNXI_FUNCTION(0x1, "gpio_out"), 505 SUNXI_FUNCTION(0x1, "gpio_out"),
506 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ 506 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
507 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */ 507 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
508 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, 508 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
509 SUNXI_FUNCTION(0x0, "gpio_in"), 509 SUNXI_FUNCTION(0x0, "gpio_in"),
510 SUNXI_FUNCTION(0x1, "gpio_out"), 510 SUNXI_FUNCTION(0x1, "gpio_out"),
511 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ 511 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
512 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ 512 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
513 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */ 513 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
514 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, 514 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
515 SUNXI_FUNCTION(0x0, "gpio_in"), 515 SUNXI_FUNCTION(0x0, "gpio_in"),
516 SUNXI_FUNCTION(0x1, "gpio_out"), 516 SUNXI_FUNCTION(0x1, "gpio_out"),
517 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ 517 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
518 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */ 518 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
519 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, 519 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
520 SUNXI_FUNCTION(0x0, "gpio_in"), 520 SUNXI_FUNCTION(0x0, "gpio_in"),
521 SUNXI_FUNCTION(0x1, "gpio_out"), 521 SUNXI_FUNCTION(0x1, "gpio_out"),
522 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ 522 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
523 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */ 523 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
524 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, 524 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
525 SUNXI_FUNCTION(0x0, "gpio_in"), 525 SUNXI_FUNCTION(0x0, "gpio_in"),
526 SUNXI_FUNCTION(0x1, "gpio_out"), 526 SUNXI_FUNCTION(0x1, "gpio_out"),
527 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ 527 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
528 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */ 528 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
529 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, 529 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
530 SUNXI_FUNCTION(0x0, "gpio_in"), 530 SUNXI_FUNCTION(0x0, "gpio_in"),
531 SUNXI_FUNCTION(0x1, "gpio_out"), 531 SUNXI_FUNCTION(0x1, "gpio_out"),
532 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ 532 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
533 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */ 533 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, 534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
535 SUNXI_FUNCTION(0x0, "gpio_in"), 535 SUNXI_FUNCTION(0x0, "gpio_in"),
536 SUNXI_FUNCTION(0x1, "gpio_out"), 536 SUNXI_FUNCTION(0x1, "gpio_out"),
537 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ 537 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
538 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */ 538 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
539 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, 539 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
540 SUNXI_FUNCTION(0x0, "gpio_in"), 540 SUNXI_FUNCTION(0x0, "gpio_in"),
541 SUNXI_FUNCTION(0x1, "gpio_out"), 541 SUNXI_FUNCTION(0x1, "gpio_out"),
542 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ 542 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
543 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */ 543 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
544 /* Hole */ 544 /* Hole */
545 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, 545 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
546 SUNXI_FUNCTION(0x0, "gpio_in"), 546 SUNXI_FUNCTION(0x0, "gpio_in"),
547 SUNXI_FUNCTION(0x1, "gpio_out"), 547 SUNXI_FUNCTION(0x1, "gpio_out"),
548 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ 548 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
549 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */ 549 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
550 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, 550 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
551 SUNXI_FUNCTION(0x0, "gpio_in"), 551 SUNXI_FUNCTION(0x0, "gpio_in"),
552 SUNXI_FUNCTION(0x1, "gpio_out"), 552 SUNXI_FUNCTION(0x1, "gpio_out"),
553 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ 553 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
554 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ 554 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
555 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, 555 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
556 SUNXI_FUNCTION(0x0, "gpio_in"), 556 SUNXI_FUNCTION(0x0, "gpio_in"),
557 SUNXI_FUNCTION(0x1, "gpio_out"), 557 SUNXI_FUNCTION(0x1, "gpio_out"),
558 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ 558 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
559 SUNXI_FUNCTION(0x4, "uart0")), /* TX */ 559 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
560 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, 560 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
561 SUNXI_FUNCTION(0x0, "gpio_in"), 561 SUNXI_FUNCTION(0x0, "gpio_in"),
562 SUNXI_FUNCTION(0x1, "gpio_out"), 562 SUNXI_FUNCTION(0x1, "gpio_out"),
563 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ 563 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
564 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ 564 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
565 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, 565 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
566 SUNXI_FUNCTION(0x0, "gpio_in"), 566 SUNXI_FUNCTION(0x0, "gpio_in"),
567 SUNXI_FUNCTION(0x1, "gpio_out"), 567 SUNXI_FUNCTION(0x1, "gpio_out"),
568 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ 568 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
569 SUNXI_FUNCTION(0x4, "uart0")), /* RX */ 569 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
570 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, 570 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
571 SUNXI_FUNCTION(0x0, "gpio_in"), 571 SUNXI_FUNCTION(0x0, "gpio_in"),
572 SUNXI_FUNCTION(0x1, "gpio_out"), 572 SUNXI_FUNCTION(0x1, "gpio_out"),
573 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ 573 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
574 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ 574 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
575 /* Hole */ 575 /* Hole */
576 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, 576 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
577 SUNXI_FUNCTION(0x0, "gpio_in"), 577 SUNXI_FUNCTION(0x0, "gpio_in"),
578 SUNXI_FUNCTION(0x1, "gpio_out"), 578 SUNXI_FUNCTION(0x1, "gpio_out"),
579 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */ 579 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
580 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */ 580 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
581 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */ 581 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
582 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, 582 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
583 SUNXI_FUNCTION(0x0, "gpio_in"), 583 SUNXI_FUNCTION(0x0, "gpio_in"),
584 SUNXI_FUNCTION(0x1, "gpio_out"), 584 SUNXI_FUNCTION(0x1, "gpio_out"),
585 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */ 585 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
586 SUNXI_FUNCTION(0x3, "csi1"), /* CK */ 586 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
587 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */ 587 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
588 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, 588 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
589 SUNXI_FUNCTION(0x0, "gpio_in"), 589 SUNXI_FUNCTION(0x0, "gpio_in"),
590 SUNXI_FUNCTION(0x1, "gpio_out"), 590 SUNXI_FUNCTION(0x1, "gpio_out"),
591 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */ 591 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
592 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */ 592 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
593 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */ 593 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
594 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, 594 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
595 SUNXI_FUNCTION(0x0, "gpio_in"), 595 SUNXI_FUNCTION(0x0, "gpio_in"),
596 SUNXI_FUNCTION(0x1, "gpio_out"), 596 SUNXI_FUNCTION(0x1, "gpio_out"),
597 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */ 597 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
598 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */ 598 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
599 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */ 599 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
600 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, 600 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
601 SUNXI_FUNCTION(0x0, "gpio_in"), 601 SUNXI_FUNCTION(0x0, "gpio_in"),
602 SUNXI_FUNCTION(0x1, "gpio_out"), 602 SUNXI_FUNCTION(0x1, "gpio_out"),
603 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */ 603 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
604 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */ 604 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
605 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */ 605 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
606 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */ 606 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
607 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5, 607 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
608 SUNXI_FUNCTION(0x0, "gpio_in"), 608 SUNXI_FUNCTION(0x0, "gpio_in"),
609 SUNXI_FUNCTION(0x1, "gpio_out"), 609 SUNXI_FUNCTION(0x1, "gpio_out"),
610 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */ 610 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
611 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */ 611 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
612 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */ 612 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
613 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */ 613 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
614 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6, 614 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
615 SUNXI_FUNCTION(0x0, "gpio_in"), 615 SUNXI_FUNCTION(0x0, "gpio_in"),
616 SUNXI_FUNCTION(0x1, "gpio_out"), 616 SUNXI_FUNCTION(0x1, "gpio_out"),
617 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */ 617 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
618 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */ 618 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
619 SUNXI_FUNCTION(0x4, "uart3"), /* TX */ 619 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
620 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */ 620 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
621 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7, 621 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
622 SUNXI_FUNCTION(0x0, "gpio_in"), 622 SUNXI_FUNCTION(0x0, "gpio_in"),
623 SUNXI_FUNCTION(0x1, "gpio_out"), 623 SUNXI_FUNCTION(0x1, "gpio_out"),
624 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */ 624 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
625 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */ 625 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
626 SUNXI_FUNCTION(0x4, "uart3"), /* RX */ 626 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
627 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */ 627 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
628 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8, 628 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
629 SUNXI_FUNCTION(0x0, "gpio_in"), 629 SUNXI_FUNCTION(0x0, "gpio_in"),
630 SUNXI_FUNCTION(0x1, "gpio_out"), 630 SUNXI_FUNCTION(0x1, "gpio_out"),
631 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */ 631 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
632 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */ 632 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
633 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ 633 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
634 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */ 634 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
635 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, 635 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
636 SUNXI_FUNCTION(0x0, "gpio_in"), 636 SUNXI_FUNCTION(0x0, "gpio_in"),
637 SUNXI_FUNCTION(0x1, "gpio_out"), 637 SUNXI_FUNCTION(0x1, "gpio_out"),
638 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */ 638 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
639 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */ 639 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
640 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ 640 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
641 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */ 641 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
642 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, 642 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
643 SUNXI_FUNCTION(0x0, "gpio_in"), 643 SUNXI_FUNCTION(0x0, "gpio_in"),
644 SUNXI_FUNCTION(0x1, "gpio_out"), 644 SUNXI_FUNCTION(0x1, "gpio_out"),
645 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */ 645 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
646 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */ 646 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
647 SUNXI_FUNCTION(0x4, "uart4"), /* TX */ 647 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
648 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */ 648 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
649 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, 649 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
650 SUNXI_FUNCTION(0x0, "gpio_in"), 650 SUNXI_FUNCTION(0x0, "gpio_in"),
651 SUNXI_FUNCTION(0x1, "gpio_out"), 651 SUNXI_FUNCTION(0x1, "gpio_out"),
652 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */ 652 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
653 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */ 653 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
654 SUNXI_FUNCTION(0x4, "uart4"), /* RX */ 654 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
655 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */ 655 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
656 /* Hole */ 656 /* Hole */
657 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0, 657 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
658 SUNXI_FUNCTION(0x0, "gpio_in"), 658 SUNXI_FUNCTION(0x0, "gpio_in"),
659 SUNXI_FUNCTION(0x1, "gpio_out"), 659 SUNXI_FUNCTION(0x1, "gpio_out"),
660 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */ 660 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
661 SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */ 661 SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */
662 SUNXI_FUNCTION(0x4, "uart3"), /* TX */ 662 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
663 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */ 663 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
664 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */ 664 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
665 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1, 665 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
666 SUNXI_FUNCTION(0x0, "gpio_in"), 666 SUNXI_FUNCTION(0x0, "gpio_in"),
667 SUNXI_FUNCTION(0x1, "gpio_out"), 667 SUNXI_FUNCTION(0x1, "gpio_out"),
668 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */ 668 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
669 SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */ 669 SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */
670 SUNXI_FUNCTION(0x4, "uart3"), /* RX */ 670 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
671 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */ 671 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
672 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */ 672 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
673 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2, 673 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
674 SUNXI_FUNCTION(0x0, "gpio_in"), 674 SUNXI_FUNCTION(0x0, "gpio_in"),
675 SUNXI_FUNCTION(0x1, "gpio_out"), 675 SUNXI_FUNCTION(0x1, "gpio_out"),
676 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */ 676 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
677 SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */ 677 SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */
678 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ 678 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
679 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */ 679 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
680 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */ 680 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
681 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3, 681 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
682 SUNXI_FUNCTION(0x0, "gpio_in"), 682 SUNXI_FUNCTION(0x0, "gpio_in"),
683 SUNXI_FUNCTION(0x1, "gpio_out"), 683 SUNXI_FUNCTION(0x1, "gpio_out"),
684 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */ 684 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
685 SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */ 685 SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */
686 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ 686 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
687 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */ 687 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
688 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */ 688 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
689 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4, 689 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
690 SUNXI_FUNCTION(0x0, "gpio_in"), 690 SUNXI_FUNCTION(0x0, "gpio_in"),
691 SUNXI_FUNCTION(0x1, "gpio_out"), 691 SUNXI_FUNCTION(0x1, "gpio_out"),
692 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */ 692 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
693 SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */ 693 SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */
694 SUNXI_FUNCTION(0x4, "uart4"), /* TX */ 694 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
695 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */ 695 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
696 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */ 696 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
697 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5, 697 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
698 SUNXI_FUNCTION(0x0, "gpio_in"), 698 SUNXI_FUNCTION(0x0, "gpio_in"),
699 SUNXI_FUNCTION(0x1, "gpio_out"), 699 SUNXI_FUNCTION(0x1, "gpio_out"),
700 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */ 700 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
701 SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */ 701 SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */
702 SUNXI_FUNCTION(0x4, "uart4"), /* RX */ 702 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
703 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */ 703 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
704 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */ 704 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
705 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6, 705 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
706 SUNXI_FUNCTION(0x0, "gpio_in"), 706 SUNXI_FUNCTION(0x0, "gpio_in"),
707 SUNXI_FUNCTION(0x1, "gpio_out"), 707 SUNXI_FUNCTION(0x1, "gpio_out"),
708 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */ 708 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
709 SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */ 709 SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */
710 SUNXI_FUNCTION(0x4, "uart5"), /* TX */ 710 SUNXI_FUNCTION(0x4, "uart5"), /* TX */
711 SUNXI_FUNCTION(0x5, "ms"), /* BS */ 711 SUNXI_FUNCTION(0x5, "ms"), /* BS */
712 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */ 712 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
713 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */ 713 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
714 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7, 714 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
715 SUNXI_FUNCTION(0x0, "gpio_in"), 715 SUNXI_FUNCTION(0x0, "gpio_in"),
716 SUNXI_FUNCTION(0x1, "gpio_out"), 716 SUNXI_FUNCTION(0x1, "gpio_out"),
717 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */ 717 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
718 SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */ 718 SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */
719 SUNXI_FUNCTION(0x4, "uart5"), /* RX */ 719 SUNXI_FUNCTION(0x4, "uart5"), /* RX */
720 SUNXI_FUNCTION(0x5, "ms"), /* CLK */ 720 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
721 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */ 721 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
722 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */ 722 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
723 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8, 723 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
724 SUNXI_FUNCTION(0x0, "gpio_in"), 724 SUNXI_FUNCTION(0x0, "gpio_in"),
725 SUNXI_FUNCTION(0x1, "gpio_out"), 725 SUNXI_FUNCTION(0x1, "gpio_out"),
726 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */ 726 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
727 SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */ 727 SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */
728 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */ 728 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
729 SUNXI_FUNCTION(0x5, "ms"), /* D0 */ 729 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
730 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */ 730 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
731 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */ 731 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
732 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9, 732 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
733 SUNXI_FUNCTION(0x0, "gpio_in"), 733 SUNXI_FUNCTION(0x0, "gpio_in"),
734 SUNXI_FUNCTION(0x1, "gpio_out"), 734 SUNXI_FUNCTION(0x1, "gpio_out"),
735 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */ 735 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
736 SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */ 736 SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */
737 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */ 737 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
738 SUNXI_FUNCTION(0x5, "ms"), /* D1 */ 738 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
739 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */ 739 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
740 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */ 740 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
741 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10, 741 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
742 SUNXI_FUNCTION(0x0, "gpio_in"), 742 SUNXI_FUNCTION(0x0, "gpio_in"),
743 SUNXI_FUNCTION(0x1, "gpio_out"), 743 SUNXI_FUNCTION(0x1, "gpio_out"),
744 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */ 744 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
745 SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */ 745 SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */
746 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */ 746 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
747 SUNXI_FUNCTION(0x5, "ms"), /* D2 */ 747 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
748 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */ 748 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
749 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */ 749 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
750 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11, 750 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
751 SUNXI_FUNCTION(0x0, "gpio_in"), 751 SUNXI_FUNCTION(0x0, "gpio_in"),
752 SUNXI_FUNCTION(0x1, "gpio_out"), 752 SUNXI_FUNCTION(0x1, "gpio_out"),
753 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */ 753 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
754 SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */ 754 SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */
755 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */ 755 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
756 SUNXI_FUNCTION(0x5, "ms"), /* D3 */ 756 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
757 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */ 757 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
758 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */ 758 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
759 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12, 759 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
760 SUNXI_FUNCTION(0x0, "gpio_in"), 760 SUNXI_FUNCTION(0x0, "gpio_in"),
761 SUNXI_FUNCTION(0x1, "gpio_out"), 761 SUNXI_FUNCTION(0x1, "gpio_out"),
762 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */ 762 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
763 SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */ 763 SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */
764 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */ 764 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
765 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */ 765 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */
766 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */ 766 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
767 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13, 767 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
768 SUNXI_FUNCTION(0x0, "gpio_in"), 768 SUNXI_FUNCTION(0x0, "gpio_in"),
769 SUNXI_FUNCTION(0x1, "gpio_out"), 769 SUNXI_FUNCTION(0x1, "gpio_out"),
770 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */ 770 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
771 SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */ 771 SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */
772 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */ 772 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
773 SUNXI_FUNCTION(0x5, "sim"), /* RST */ 773 SUNXI_FUNCTION(0x5, "sim"), /* RST */
774 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */ 774 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */
775 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */ 775 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
776 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14, 776 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
777 SUNXI_FUNCTION(0x0, "gpio_in"), 777 SUNXI_FUNCTION(0x0, "gpio_in"),
778 SUNXI_FUNCTION(0x1, "gpio_out"), 778 SUNXI_FUNCTION(0x1, "gpio_out"),
779 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */ 779 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
780 SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */ 780 SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */
781 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */ 781 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
782 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */ 782 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
783 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */ 783 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
784 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */ 784 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
785 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15, 785 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
786 SUNXI_FUNCTION(0x0, "gpio_in"), 786 SUNXI_FUNCTION(0x0, "gpio_in"),
787 SUNXI_FUNCTION(0x1, "gpio_out"), 787 SUNXI_FUNCTION(0x1, "gpio_out"),
788 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */ 788 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
789 SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */ 789 SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */
790 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */ 790 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
791 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */ 791 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
792 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */ 792 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
793 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */ 793 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
794 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16, 794 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
795 SUNXI_FUNCTION(0x0, "gpio_in"), 795 SUNXI_FUNCTION(0x0, "gpio_in"),
796 SUNXI_FUNCTION(0x1, "gpio_out"), 796 SUNXI_FUNCTION(0x1, "gpio_out"),
797 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */ 797 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
798 SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */ 798 SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */
799 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */ 799 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
800 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */ 800 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
801 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */ 801 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
802 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17, 802 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
803 SUNXI_FUNCTION(0x0, "gpio_in"), 803 SUNXI_FUNCTION(0x0, "gpio_in"),
804 SUNXI_FUNCTION(0x1, "gpio_out"), 804 SUNXI_FUNCTION(0x1, "gpio_out"),
805 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */ 805 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
806 SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */ 806 SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */
807 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */ 807 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
808 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */ 808 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
809 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */ 809 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
810 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */ 810 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
811 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18, 811 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
812 SUNXI_FUNCTION(0x0, "gpio_in"), 812 SUNXI_FUNCTION(0x0, "gpio_in"),
813 SUNXI_FUNCTION(0x1, "gpio_out"), 813 SUNXI_FUNCTION(0x1, "gpio_out"),
814 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */ 814 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
815 SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */ 815 SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */
816 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */ 816 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
817 SUNXI_FUNCTION(0x5, "sim"), /* SCK */ 817 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
818 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */ 818 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
819 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */ 819 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
820 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19, 820 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
821 SUNXI_FUNCTION(0x0, "gpio_in"), 821 SUNXI_FUNCTION(0x0, "gpio_in"),
822 SUNXI_FUNCTION(0x1, "gpio_out"), 822 SUNXI_FUNCTION(0x1, "gpio_out"),
823 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */ 823 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
824 SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */ 824 SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */
825 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */ 825 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
826 SUNXI_FUNCTION(0x5, "sim"), /* SDA */ 826 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
827 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */ 827 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
828 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */ 828 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
829 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20, 829 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
830 SUNXI_FUNCTION(0x0, "gpio_in"), 830 SUNXI_FUNCTION(0x0, "gpio_in"),
831 SUNXI_FUNCTION(0x1, "gpio_out"), 831 SUNXI_FUNCTION(0x1, "gpio_out"),
832 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */ 832 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
833 SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */ 833 SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */
834 SUNXI_FUNCTION(0x4, "can"), /* TX */ 834 SUNXI_FUNCTION(0x4, "can"), /* TX */
835 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */ 835 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
836 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */ 836 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
837 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21, 837 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
838 SUNXI_FUNCTION(0x0, "gpio_in"), 838 SUNXI_FUNCTION(0x0, "gpio_in"),
839 SUNXI_FUNCTION(0x1, "gpio_out"), 839 SUNXI_FUNCTION(0x1, "gpio_out"),
840 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */ 840 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
841 SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */ 841 SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */
842 SUNXI_FUNCTION(0x4, "can"), /* RX */ 842 SUNXI_FUNCTION(0x4, "can"), /* RX */
843 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */ 843 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
844 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */ 844 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
845 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22, 845 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
846 SUNXI_FUNCTION(0x0, "gpio_in"), 846 SUNXI_FUNCTION(0x0, "gpio_in"),
847 SUNXI_FUNCTION(0x1, "gpio_out"), 847 SUNXI_FUNCTION(0x1, "gpio_out"),
848 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */ 848 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
849 SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */ 849 SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */
850 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */ 850 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
851 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */ 851 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
852 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */ 852 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
853 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23, 853 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
854 SUNXI_FUNCTION(0x0, "gpio_in"), 854 SUNXI_FUNCTION(0x0, "gpio_in"),
855 SUNXI_FUNCTION(0x1, "gpio_out"), 855 SUNXI_FUNCTION(0x1, "gpio_out"),
856 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */ 856 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
857 SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */ 857 SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */
858 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */ 858 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
859 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */ 859 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
860 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */ 860 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
861 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24, 861 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
862 SUNXI_FUNCTION(0x0, "gpio_in"), 862 SUNXI_FUNCTION(0x0, "gpio_in"),
863 SUNXI_FUNCTION(0x1, "gpio_out"), 863 SUNXI_FUNCTION(0x1, "gpio_out"),
864 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */ 864 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
865 SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */ 865 SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */
866 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */ 866 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
867 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */ 867 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
868 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */ 868 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
869 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25, 869 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
870 SUNXI_FUNCTION(0x0, "gpio_in"), 870 SUNXI_FUNCTION(0x0, "gpio_in"),
871 SUNXI_FUNCTION(0x1, "gpio_out"), 871 SUNXI_FUNCTION(0x1, "gpio_out"),
872 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */ 872 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
873 SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */ 873 SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */
874 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */ 874 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
875 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */ 875 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
876 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */ 876 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
877 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26, 877 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
878 SUNXI_FUNCTION(0x0, "gpio_in"), 878 SUNXI_FUNCTION(0x0, "gpio_in"),
879 SUNXI_FUNCTION(0x1, "gpio_out"), 879 SUNXI_FUNCTION(0x1, "gpio_out"),
880 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */ 880 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
881 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */ 881 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */
882 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */ 882 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
883 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */ 883 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
884 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */ 884 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
885 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27, 885 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
886 SUNXI_FUNCTION(0x0, "gpio_in"), 886 SUNXI_FUNCTION(0x0, "gpio_in"),
887 SUNXI_FUNCTION(0x1, "gpio_out"), 887 SUNXI_FUNCTION(0x1, "gpio_out"),
888 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */ 888 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
889 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */ 889 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */
890 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */ 890 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
891 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */ 891 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
892 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */ 892 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
893 /* Hole */ 893 /* Hole */
894 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0, 894 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
895 SUNXI_FUNCTION(0x0, "gpio_in"), 895 SUNXI_FUNCTION(0x0, "gpio_in"),
896 SUNXI_FUNCTION(0x1, "gpio_out")), 896 SUNXI_FUNCTION(0x1, "gpio_out")),
897 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1, 897 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1,
898 SUNXI_FUNCTION(0x0, "gpio_in"), 898 SUNXI_FUNCTION(0x0, "gpio_in"),
899 SUNXI_FUNCTION(0x1, "gpio_out")), 899 SUNXI_FUNCTION(0x1, "gpio_out")),
900 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2, 900 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2,
901 SUNXI_FUNCTION(0x0, "gpio_in"), 901 SUNXI_FUNCTION(0x0, "gpio_in"),
902 SUNXI_FUNCTION(0x1, "gpio_out")), 902 SUNXI_FUNCTION(0x1, "gpio_out")),
903 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3, 903 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
904 SUNXI_FUNCTION(0x0, "gpio_in"), 904 SUNXI_FUNCTION(0x0, "gpio_in"),
905 SUNXI_FUNCTION(0x1, "gpio_out"), 905 SUNXI_FUNCTION(0x1, "gpio_out"),
906 SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */ 906 SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */
907 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4, 907 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
908 SUNXI_FUNCTION(0x0, "gpio_in"), 908 SUNXI_FUNCTION(0x0, "gpio_in"),
909 SUNXI_FUNCTION(0x1, "gpio_out"), 909 SUNXI_FUNCTION(0x1, "gpio_out"),
910 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */ 910 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
911 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5, 911 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
912 SUNXI_FUNCTION(0x0, "gpio_in"), 912 SUNXI_FUNCTION(0x0, "gpio_in"),
913 SUNXI_FUNCTION(0x1, "gpio_out"), 913 SUNXI_FUNCTION(0x1, "gpio_out"),
914 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */ 914 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
915 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6, 915 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
916 SUNXI_FUNCTION(0x0, "gpio_in"), 916 SUNXI_FUNCTION(0x0, "gpio_in"),
917 SUNXI_FUNCTION(0x1, "gpio_out"), 917 SUNXI_FUNCTION(0x1, "gpio_out"),
918 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */ 918 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
919 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7, 919 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
920 SUNXI_FUNCTION(0x0, "gpio_in"), 920 SUNXI_FUNCTION(0x0, "gpio_in"),
921 SUNXI_FUNCTION(0x1, "gpio_out"), 921 SUNXI_FUNCTION(0x1, "gpio_out"),
922 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */ 922 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
923 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8, 923 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
924 SUNXI_FUNCTION(0x0, "gpio_in"), 924 SUNXI_FUNCTION(0x0, "gpio_in"),
925 SUNXI_FUNCTION(0x1, "gpio_out"), 925 SUNXI_FUNCTION(0x1, "gpio_out"),
926 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */ 926 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
927 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9, 927 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
928 SUNXI_FUNCTION(0x0, "gpio_in"), 928 SUNXI_FUNCTION(0x0, "gpio_in"),
929 SUNXI_FUNCTION(0x1, "gpio_out"), 929 SUNXI_FUNCTION(0x1, "gpio_out"),
930 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */ 930 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
931 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10, 931 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
932 SUNXI_FUNCTION(0x0, "gpio_in"), 932 SUNXI_FUNCTION(0x0, "gpio_in"),
933 SUNXI_FUNCTION(0x1, "gpio_out"), 933 SUNXI_FUNCTION(0x1, "gpio_out"),
934 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */ 934 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
935 SUNXI_FUNCTION(0x3, "uart5"), /* TX */ 935 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
936 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */ 936 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
937 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11, 937 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
938 SUNXI_FUNCTION(0x0, "gpio_in"), 938 SUNXI_FUNCTION(0x0, "gpio_in"),
939 SUNXI_FUNCTION(0x1, "gpio_out"), 939 SUNXI_FUNCTION(0x1, "gpio_out"),
940 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ 940 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
941 SUNXI_FUNCTION(0x3, "uart5"), /* RX */ 941 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
942 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */ 942 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
943 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12, 943 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
944 SUNXI_FUNCTION(0x0, "gpio_in"), 944 SUNXI_FUNCTION(0x0, "gpio_in"),
945 SUNXI_FUNCTION(0x1, "gpio_out"), 945 SUNXI_FUNCTION(0x1, "gpio_out"),
946 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ 946 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
947 SUNXI_FUNCTION(0x3, "uart6"), /* TX */ 947 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
948 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ 948 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
949 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13, 949 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
950 SUNXI_FUNCTION(0x0, "gpio_in"), 950 SUNXI_FUNCTION(0x0, "gpio_in"),
951 SUNXI_FUNCTION(0x1, "gpio_out"), 951 SUNXI_FUNCTION(0x1, "gpio_out"),
952 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ 952 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
953 SUNXI_FUNCTION(0x3, "uart6"), /* RX */ 953 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
954 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ 954 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
955 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14, 955 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
956 SUNXI_FUNCTION(0x0, "gpio_in"), 956 SUNXI_FUNCTION(0x0, "gpio_in"),
957 SUNXI_FUNCTION(0x1, "gpio_out"), 957 SUNXI_FUNCTION(0x1, "gpio_out"),
958 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */ 958 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
959 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */ 959 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
960 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */ 960 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
961 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */ 961 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
962 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15, 962 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
963 SUNXI_FUNCTION(0x0, "gpio_in"), 963 SUNXI_FUNCTION(0x0, "gpio_in"),
964 SUNXI_FUNCTION(0x1, "gpio_out"), 964 SUNXI_FUNCTION(0x1, "gpio_out"),
965 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ 965 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
966 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */ 966 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
967 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */ 967 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
968 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */ 968 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16, 969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
970 SUNXI_FUNCTION(0x0, "gpio_in"), 970 SUNXI_FUNCTION(0x0, "gpio_in"),
971 SUNXI_FUNCTION(0x1, "gpio_out"), 971 SUNXI_FUNCTION(0x1, "gpio_out"),
972 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ 972 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
973 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ 973 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
974 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */ 974 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
975 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17, 975 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
976 SUNXI_FUNCTION(0x0, "gpio_in"), 976 SUNXI_FUNCTION(0x0, "gpio_in"),
977 SUNXI_FUNCTION(0x1, "gpio_out"), 977 SUNXI_FUNCTION(0x1, "gpio_out"),
978 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ 978 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
979 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ 979 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
980 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */ 980 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
981 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18, 981 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
982 SUNXI_FUNCTION(0x0, "gpio_in"), 982 SUNXI_FUNCTION(0x0, "gpio_in"),
983 SUNXI_FUNCTION(0x1, "gpio_out"), 983 SUNXI_FUNCTION(0x1, "gpio_out"),
984 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ 984 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
985 SUNXI_FUNCTION(0x3, "uart2"), /* TX */ 985 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
986 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */ 986 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
987 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19, 987 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
988 SUNXI_FUNCTION(0x0, "gpio_in"), 988 SUNXI_FUNCTION(0x0, "gpio_in"),
989 SUNXI_FUNCTION(0x1, "gpio_out"), 989 SUNXI_FUNCTION(0x1, "gpio_out"),
990 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ 990 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
991 SUNXI_FUNCTION(0x3, "uart2"), /* RX */ 991 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
992 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */ 992 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
993 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20, 993 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
994 SUNXI_FUNCTION(0x0, "gpio_in"), 994 SUNXI_FUNCTION(0x0, "gpio_in"),
995 SUNXI_FUNCTION(0x1, "gpio_out"), 995 SUNXI_FUNCTION(0x1, "gpio_out"),
996 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */ 996 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
997 SUNXI_FUNCTION(0x3, "uart7"), /* TX */ 997 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
998 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */ 998 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
999 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21, 999 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
1000 SUNXI_FUNCTION(0x0, "gpio_in"), 1000 SUNXI_FUNCTION(0x0, "gpio_in"),
1001 SUNXI_FUNCTION(0x1, "gpio_out"), 1001 SUNXI_FUNCTION(0x1, "gpio_out"),
1002 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */ 1002 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
1003 SUNXI_FUNCTION(0x3, "uart7"), /* RX */ 1003 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
1004 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */ 1004 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
1005 }; 1005 };
1006 1006
1007 static const struct sunxi_desc_pin sun5i_a10s_pins[] = {
1008 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
1009 SUNXI_FUNCTION(0x0, "gpio_in"),
1010 SUNXI_FUNCTION(0x1, "gpio_out"),
1011 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
1012 SUNXI_FUNCTION(0x3, "ts0"), /* CLK */
1013 SUNXI_FUNCTION(0x5, "keypad")), /* IN0 */
1014 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
1015 SUNXI_FUNCTION(0x0, "gpio_in"),
1016 SUNXI_FUNCTION(0x1, "gpio_out"),
1017 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
1018 SUNXI_FUNCTION(0x3, "ts0"), /* ERR */
1019 SUNXI_FUNCTION(0x5, "keypad")), /* IN1 */
1020 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
1021 SUNXI_FUNCTION(0x0, "gpio_in"),
1022 SUNXI_FUNCTION(0x1, "gpio_out"),
1023 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
1024 SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */
1025 SUNXI_FUNCTION(0x5, "keypad")), /* IN2 */
1026 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
1027 SUNXI_FUNCTION(0x0, "gpio_in"),
1028 SUNXI_FUNCTION(0x1, "gpio_out"),
1029 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
1030 SUNXI_FUNCTION(0x3, "ts0"), /* DLVD */
1031 SUNXI_FUNCTION(0x5, "keypad")), /* IN3 */
1032 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
1033 SUNXI_FUNCTION(0x0, "gpio_in"),
1034 SUNXI_FUNCTION(0x1, "gpio_out"),
1035 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
1036 SUNXI_FUNCTION(0x3, "ts0"), /* D0 */
1037 SUNXI_FUNCTION(0x5, "keypad")), /* IN4 */
1038 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
1039 SUNXI_FUNCTION(0x0, "gpio_in"),
1040 SUNXI_FUNCTION(0x1, "gpio_out"),
1041 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
1042 SUNXI_FUNCTION(0x3, "ts0"), /* D1 */
1043 SUNXI_FUNCTION(0x5, "keypad")), /* IN5 */
1044 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
1045 SUNXI_FUNCTION(0x0, "gpio_in"),
1046 SUNXI_FUNCTION(0x1, "gpio_out"),
1047 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
1048 SUNXI_FUNCTION(0x3, "ts0"), /* D2 */
1049 SUNXI_FUNCTION(0x5, "keypad")), /* IN6 */
1050 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
1051 SUNXI_FUNCTION(0x0, "gpio_in"),
1052 SUNXI_FUNCTION(0x1, "gpio_out"),
1053 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
1054 SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
1055 SUNXI_FUNCTION(0x5, "keypad")), /* IN7 */
1056 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
1057 SUNXI_FUNCTION(0x0, "gpio_in"),
1058 SUNXI_FUNCTION(0x1, "gpio_out"),
1059 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
1060 SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
1061 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
1062 SUNXI_FUNCTION(0x5, "keypad")), /* OUT0 */
1063 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
1064 SUNXI_FUNCTION(0x0, "gpio_in"),
1065 SUNXI_FUNCTION(0x1, "gpio_out"),
1066 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
1067 SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
1068 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
1069 SUNXI_FUNCTION(0x5, "keypad")), /* OUT1 */
1070 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
1071 SUNXI_FUNCTION(0x0, "gpio_in"),
1072 SUNXI_FUNCTION(0x1, "gpio_out"),
1073 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
1074 SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
1075 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
1076 SUNXI_FUNCTION(0x5, "keypad")), /* OUT2 */
1077 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
1078 SUNXI_FUNCTION(0x0, "gpio_in"),
1079 SUNXI_FUNCTION(0x1, "gpio_out"),
1080 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
1081 SUNXI_FUNCTION(0x3, "ts0"), /* D7 */
1082 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
1083 SUNXI_FUNCTION(0x5, "keypad")), /* OUT3 */
1084 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
1085 SUNXI_FUNCTION(0x0, "gpio_in"),
1086 SUNXI_FUNCTION(0x1, "gpio_out"),
1087 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
1088 SUNXI_FUNCTION(0x3, "uart1"), /* TX */
1089 SUNXI_FUNCTION(0x5, "keypad")), /* OUT4 */
1090 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
1091 SUNXI_FUNCTION(0x0, "gpio_in"),
1092 SUNXI_FUNCTION(0x1, "gpio_out"),
1093 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
1094 SUNXI_FUNCTION(0x3, "uart1"), /* RX */
1095 SUNXI_FUNCTION(0x5, "keypad")), /* OUT5 */
1096 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
1097 SUNXI_FUNCTION(0x0, "gpio_in"),
1098 SUNXI_FUNCTION(0x1, "gpio_out"),
1099 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
1100 SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
1101 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
1102 SUNXI_FUNCTION(0x5, "keypad")), /* OUT6 */
1103 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
1104 SUNXI_FUNCTION(0x0, "gpio_in"),
1105 SUNXI_FUNCTION(0x1, "gpio_out"),
1106 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
1107 SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
1108 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
1109 SUNXI_FUNCTION(0x5, "keypad")), /* OUT7 */
1110 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
1111 SUNXI_FUNCTION(0x0, "gpio_in"),
1112 SUNXI_FUNCTION(0x1, "gpio_out"),
1113 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
1114 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
1115 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
1116 SUNXI_FUNCTION(0x0, "gpio_in"),
1117 SUNXI_FUNCTION(0x1, "gpio_out"),
1118 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
1119 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
1120 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
1121 /* Hole */
1122 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
1123 SUNXI_FUNCTION(0x0, "gpio_in"),
1124 SUNXI_FUNCTION(0x1, "gpio_out"),
1125 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
1126 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
1127 SUNXI_FUNCTION(0x0, "gpio_in"),
1128 SUNXI_FUNCTION(0x1, "gpio_out"),
1129 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
1130 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
1131 SUNXI_FUNCTION(0x0, "gpio_in"),
1132 SUNXI_FUNCTION(0x1, "gpio_out"),
1133 SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
1134 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
1135 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
1136 SUNXI_FUNCTION(0x0, "gpio_in"),
1137 SUNXI_FUNCTION(0x1, "gpio_out"),
1138 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
1139 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
1140 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
1141 SUNXI_FUNCTION(0x0, "gpio_in"),
1142 SUNXI_FUNCTION(0x1, "gpio_out"),
1143 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
1144 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
1145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
1146 SUNXI_FUNCTION(0x0, "gpio_in"),
1147 SUNXI_FUNCTION(0x1, "gpio_out"),
1148 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
1149 SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */
1150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
1151 SUNXI_FUNCTION(0x0, "gpio_in"),
1152 SUNXI_FUNCTION(0x1, "gpio_out"),
1153 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
1154 SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */
1155 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
1156 SUNXI_FUNCTION(0x0, "gpio_in"),
1157 SUNXI_FUNCTION(0x1, "gpio_out"),
1158 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
1159 SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */
1160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
1161 SUNXI_FUNCTION(0x0, "gpio_in"),
1162 SUNXI_FUNCTION(0x1, "gpio_out"),
1163 SUNXI_FUNCTION(0x2, "i2s"), /* DO */
1164 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
1165 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
1166 SUNXI_FUNCTION(0x0, "gpio_in"),
1167 SUNXI_FUNCTION(0x1, "gpio_out"),
1168 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
1169 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
1170 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
1171 SUNXI_FUNCTION(0x0, "gpio_in"),
1172 SUNXI_FUNCTION(0x1, "gpio_out"),
1173 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
1174 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
1175 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
1176 SUNXI_FUNCTION(0x0, "gpio_in"),
1177 SUNXI_FUNCTION(0x1, "gpio_out"),
1178 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
1179 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
1180 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
1181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
1182 SUNXI_FUNCTION(0x0, "gpio_in"),
1183 SUNXI_FUNCTION(0x1, "gpio_out"),
1184 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
1185 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
1186 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
1187 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
1188 SUNXI_FUNCTION(0x0, "gpio_in"),
1189 SUNXI_FUNCTION(0x1, "gpio_out"),
1190 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
1191 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
1192 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
1193 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
1194 SUNXI_FUNCTION(0x0, "gpio_in"),
1195 SUNXI_FUNCTION(0x1, "gpio_out"),
1196 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
1197 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
1198 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
1199 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
1200 SUNXI_FUNCTION(0x0, "gpio_in"),
1201 SUNXI_FUNCTION(0x1, "gpio_out"),
1202 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
1203 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
1204 SUNXI_FUNCTION(0x0, "gpio_in"),
1205 SUNXI_FUNCTION(0x1, "gpio_out"),
1206 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
1207 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
1208 SUNXI_FUNCTION(0x0, "gpio_in"),
1209 SUNXI_FUNCTION(0x1, "gpio_out"),
1210 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
1211 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
1212 SUNXI_FUNCTION(0x0, "gpio_in"),
1213 SUNXI_FUNCTION(0x1, "gpio_out"),
1214 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
1215 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
1216 SUNXI_FUNCTION(0x0, "gpio_in"),
1217 SUNXI_FUNCTION(0x1, "gpio_out"),
1218 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
1219 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
1220 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
1221 SUNXI_FUNCTION(0x0, "gpio_in"),
1222 SUNXI_FUNCTION(0x1, "gpio_out"),
1223 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
1224 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
1225 /* Hole */
1226 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
1227 SUNXI_FUNCTION(0x0, "gpio_in"),
1228 SUNXI_FUNCTION(0x1, "gpio_out"),
1229 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
1230 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
1231 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
1232 SUNXI_FUNCTION(0x0, "gpio_in"),
1233 SUNXI_FUNCTION(0x1, "gpio_out"),
1234 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
1235 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
1236 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
1237 SUNXI_FUNCTION(0x0, "gpio_in"),
1238 SUNXI_FUNCTION(0x1, "gpio_out"),
1239 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
1240 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
1241 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
1242 SUNXI_FUNCTION(0x0, "gpio_in"),
1243 SUNXI_FUNCTION(0x1, "gpio_out"),
1244 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
1245 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
1246 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
1247 SUNXI_FUNCTION(0x0, "gpio_in"),
1248 SUNXI_FUNCTION(0x1, "gpio_out"),
1249 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
1250 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
1251 SUNXI_FUNCTION(0x0, "gpio_in"),
1252 SUNXI_FUNCTION(0x1, "gpio_out"),
1253 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
1254 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
1255 SUNXI_FUNCTION(0x0, "gpio_in"),
1256 SUNXI_FUNCTION(0x1, "gpio_out"),
1257 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
1258 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
1259 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
1260 SUNXI_FUNCTION(0x0, "gpio_in"),
1261 SUNXI_FUNCTION(0x1, "gpio_out"),
1262 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
1263 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
1264 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
1265 SUNXI_FUNCTION(0x0, "gpio_in"),
1266 SUNXI_FUNCTION(0x1, "gpio_out"),
1267 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
1268 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
1269 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
1270 SUNXI_FUNCTION(0x0, "gpio_in"),
1271 SUNXI_FUNCTION(0x1, "gpio_out"),
1272 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
1273 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
1274 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
1275 SUNXI_FUNCTION(0x0, "gpio_in"),
1276 SUNXI_FUNCTION(0x1, "gpio_out"),
1277 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
1278 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
1279 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
1280 SUNXI_FUNCTION(0x0, "gpio_in"),
1281 SUNXI_FUNCTION(0x1, "gpio_out"),
1282 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
1283 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
1284 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
1285 SUNXI_FUNCTION(0x0, "gpio_in"),
1286 SUNXI_FUNCTION(0x1, "gpio_out"),
1287 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
1288 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
1289 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
1290 SUNXI_FUNCTION(0x0, "gpio_in"),
1291 SUNXI_FUNCTION(0x1, "gpio_out"),
1292 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
1293 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
1294 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
1295 SUNXI_FUNCTION(0x0, "gpio_in"),
1296 SUNXI_FUNCTION(0x1, "gpio_out"),
1297 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
1298 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
1299 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
1300 SUNXI_FUNCTION(0x0, "gpio_in"),
1301 SUNXI_FUNCTION(0x1, "gpio_out"),
1302 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
1303 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
1304 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
1305 SUNXI_FUNCTION(0x0, "gpio_in"),
1306 SUNXI_FUNCTION(0x1, "gpio_out"),
1307 SUNXI_FUNCTION(0x2, "nand0"), /* NWP */
1308 SUNXI_FUNCTION(0x4, "uart3")), /* TX */
1309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
1310 SUNXI_FUNCTION(0x0, "gpio_in"),
1311 SUNXI_FUNCTION(0x1, "gpio_out"),
1312 SUNXI_FUNCTION(0x2, "nand0"), /* NCE2 */
1313 SUNXI_FUNCTION(0x4, "uart3")), /* RX */
1314 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
1315 SUNXI_FUNCTION(0x0, "gpio_in"),
1316 SUNXI_FUNCTION(0x1, "gpio_out"),
1317 SUNXI_FUNCTION(0x2, "nand0"), /* NCE3 */
1318 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
1319 SUNXI_FUNCTION(0x4, "uart3")), /* CTS */
1320 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
1321 SUNXI_FUNCTION(0x0, "gpio_in"),
1322 SUNXI_FUNCTION(0x1, "gpio_out"),
1323 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
1324 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
1325 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
1326 /* Hole */
1327 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
1328 SUNXI_FUNCTION(0x0, "gpio_in"),
1329 SUNXI_FUNCTION(0x1, "gpio_out"),
1330 SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */
1331 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
1332 SUNXI_FUNCTION(0x0, "gpio_in"),
1333 SUNXI_FUNCTION(0x1, "gpio_out"),
1334 SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */
1335 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
1336 SUNXI_FUNCTION(0x0, "gpio_in"),
1337 SUNXI_FUNCTION(0x1, "gpio_out"),
1338 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
1339 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
1340 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
1341 SUNXI_FUNCTION(0x0, "gpio_in"),
1342 SUNXI_FUNCTION(0x1, "gpio_out"),
1343 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
1344 SUNXI_FUNCTION(0x3, "uart2")), /* RX */
1345 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
1346 SUNXI_FUNCTION(0x0, "gpio_in"),
1347 SUNXI_FUNCTION(0x1, "gpio_out"),
1348 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
1349 SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
1350 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
1351 SUNXI_FUNCTION(0x0, "gpio_in"),
1352 SUNXI_FUNCTION(0x1, "gpio_out"),
1353 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
1354 SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
1355 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
1356 SUNXI_FUNCTION(0x0, "gpio_in"),
1357 SUNXI_FUNCTION(0x1, "gpio_out"),
1358 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
1359 SUNXI_FUNCTION(0x3, "emac")), /* ECRS */
1360 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
1361 SUNXI_FUNCTION(0x0, "gpio_in"),
1362 SUNXI_FUNCTION(0x1, "gpio_out"),
1363 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
1364 SUNXI_FUNCTION(0x3, "emac")), /* ECOL */
1365 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
1366 SUNXI_FUNCTION(0x0, "gpio_in"),
1367 SUNXI_FUNCTION(0x1, "gpio_out"),
1368 SUNXI_FUNCTION(0x2, "lcd0")), /* D8 */
1369 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
1370 SUNXI_FUNCTION(0x0, "gpio_in"),
1371 SUNXI_FUNCTION(0x1, "gpio_out"),
1372 SUNXI_FUNCTION(0x2, "lcd0")), /* D9 */
1373 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
1374 SUNXI_FUNCTION(0x0, "gpio_in"),
1375 SUNXI_FUNCTION(0x1, "gpio_out"),
1376 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
1377 SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */
1378 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
1379 SUNXI_FUNCTION(0x0, "gpio_in"),
1380 SUNXI_FUNCTION(0x1, "gpio_out"),
1381 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
1382 SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */
1383 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
1384 SUNXI_FUNCTION(0x0, "gpio_in"),
1385 SUNXI_FUNCTION(0x1, "gpio_out"),
1386 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
1387 SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */
1388 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
1389 SUNXI_FUNCTION(0x0, "gpio_in"),
1390 SUNXI_FUNCTION(0x1, "gpio_out"),
1391 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
1392 SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */
1393 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
1394 SUNXI_FUNCTION(0x0, "gpio_in"),
1395 SUNXI_FUNCTION(0x1, "gpio_out"),
1396 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
1397 SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */
1398 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
1399 SUNXI_FUNCTION(0x0, "gpio_in"),
1400 SUNXI_FUNCTION(0x1, "gpio_out"),
1401 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
1402 SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */
1403 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
1404 SUNXI_FUNCTION(0x0, "gpio_in"),
1405 SUNXI_FUNCTION(0x1, "gpio_out"),
1406 SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
1407 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
1408 SUNXI_FUNCTION(0x0, "gpio_in"),
1409 SUNXI_FUNCTION(0x1, "gpio_out"),
1410 SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
1411 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
1412 SUNXI_FUNCTION(0x0, "gpio_in"),
1413 SUNXI_FUNCTION(0x1, "gpio_out"),
1414 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
1415 SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */
1416 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
1417 SUNXI_FUNCTION(0x0, "gpio_in"),
1418 SUNXI_FUNCTION(0x1, "gpio_out"),
1419 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
1420 SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */
1421 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
1422 SUNXI_FUNCTION(0x0, "gpio_in"),
1423 SUNXI_FUNCTION(0x1, "gpio_out"),
1424 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
1425 SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */
1426 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
1427 SUNXI_FUNCTION(0x0, "gpio_in"),
1428 SUNXI_FUNCTION(0x1, "gpio_out"),
1429 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
1430 SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */
1431 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
1432 SUNXI_FUNCTION(0x0, "gpio_in"),
1433 SUNXI_FUNCTION(0x1, "gpio_out"),
1434 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
1435 SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */
1436 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
1437 SUNXI_FUNCTION(0x0, "gpio_in"),
1438 SUNXI_FUNCTION(0x1, "gpio_out"),
1439 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
1440 SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */
1441 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
1442 SUNXI_FUNCTION(0x0, "gpio_in"),
1443 SUNXI_FUNCTION(0x1, "gpio_out"),
1444 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
1445 SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */
1446 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
1447 SUNXI_FUNCTION(0x0, "gpio_in"),
1448 SUNXI_FUNCTION(0x1, "gpio_out"),
1449 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
1450 SUNXI_FUNCTION(0x3, "emac")), /* ETXERR */
1451 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
1452 SUNXI_FUNCTION(0x0, "gpio_in"),
1453 SUNXI_FUNCTION(0x1, "gpio_out"),
1454 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
1455 SUNXI_FUNCTION(0x3, "emac")), /* EMDC */
1456 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
1457 SUNXI_FUNCTION(0x0, "gpio_in"),
1458 SUNXI_FUNCTION(0x1, "gpio_out"),
1459 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
1460 SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */
1461 /* Hole */
1462 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
1463 SUNXI_FUNCTION(0x0, "gpio_in"),
1464 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
1465 SUNXI_FUNCTION(0x3, "csi0"), /* PCK */
1466 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
1467 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
1468 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
1469 SUNXI_FUNCTION(0x0, "gpio_in"),
1470 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
1471 SUNXI_FUNCTION(0x3, "csi0"), /* CK */
1472 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
1473 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
1474 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
1475 SUNXI_FUNCTION(0x0, "gpio_in"),
1476 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
1477 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
1478 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
1479 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
1480 SUNXI_FUNCTION(0x0, "gpio_in"),
1481 SUNXI_FUNCTION(0x1, "gpio_out"),
1482 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
1483 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
1484 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
1485 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
1486 SUNXI_FUNCTION(0x0, "gpio_in"),
1487 SUNXI_FUNCTION(0x1, "gpio_out"),
1488 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
1489 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
1490 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
1491 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
1492 SUNXI_FUNCTION(0x0, "gpio_in"),
1493 SUNXI_FUNCTION(0x1, "gpio_out"),
1494 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
1495 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
1496 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
1497 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
1498 SUNXI_FUNCTION(0x0, "gpio_in"),
1499 SUNXI_FUNCTION(0x1, "gpio_out"),
1500 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
1501 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
1502 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
1503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
1504 SUNXI_FUNCTION(0x0, "gpio_in"),
1505 SUNXI_FUNCTION(0x1, "gpio_out"),
1506 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
1507 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
1508 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
1509 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
1510 SUNXI_FUNCTION(0x0, "gpio_in"),
1511 SUNXI_FUNCTION(0x1, "gpio_out"),
1512 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
1513 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
1514 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
1515 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
1516 SUNXI_FUNCTION(0x0, "gpio_in"),
1517 SUNXI_FUNCTION(0x1, "gpio_out"),
1518 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
1519 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
1520 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
1521 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
1522 SUNXI_FUNCTION(0x0, "gpio_in"),
1523 SUNXI_FUNCTION(0x1, "gpio_out"),
1524 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
1525 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
1526 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
1527 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
1528 SUNXI_FUNCTION(0x0, "gpio_in"),
1529 SUNXI_FUNCTION(0x1, "gpio_out"),
1530 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
1531 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
1532 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
1533 /* Hole */
1534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
1535 SUNXI_FUNCTION(0x0, "gpio_in"),
1536 SUNXI_FUNCTION(0x1, "gpio_out"),
1537 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
1538 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
1539 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
1540 SUNXI_FUNCTION(0x0, "gpio_in"),
1541 SUNXI_FUNCTION(0x1, "gpio_out"),
1542 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
1543 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
1544 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
1545 SUNXI_FUNCTION(0x0, "gpio_in"),
1546 SUNXI_FUNCTION(0x1, "gpio_out"),
1547 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
1548 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
1549 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
1550 SUNXI_FUNCTION(0x0, "gpio_in"),
1551 SUNXI_FUNCTION(0x1, "gpio_out"),
1552 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
1553 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
1554 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
1555 SUNXI_FUNCTION(0x0, "gpio_in"),
1556 SUNXI_FUNCTION(0x1, "gpio_out"),
1557 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
1558 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
1559 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
1560 SUNXI_FUNCTION(0x0, "gpio_in"),
1561 SUNXI_FUNCTION(0x1, "gpio_out"),
1562 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
1563 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
1564 /* Hole */
1565 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
1566 SUNXI_FUNCTION(0x0, "gpio_in"),
1567 SUNXI_FUNCTION(0x2, "gps"), /* CLK */
1568 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
1569 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
1570 SUNXI_FUNCTION(0x0, "gpio_in"),
1571 SUNXI_FUNCTION(0x2, "gps"), /* SIGN */
1572 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
1573 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
1574 SUNXI_FUNCTION(0x0, "gpio_in"),
1575 SUNXI_FUNCTION(0x2, "gps"), /* MAG */
1576 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
1577 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
1578 SUNXI_FUNCTION(0x0, "gpio_in"),
1579 SUNXI_FUNCTION(0x1, "gpio_out"),
1580 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
1581 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
1582 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
1583 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
1584 SUNXI_FUNCTION(0x0, "gpio_in"),
1585 SUNXI_FUNCTION(0x1, "gpio_out"),
1586 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
1587 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
1588 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
1589 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
1590 SUNXI_FUNCTION(0x0, "gpio_in"),
1591 SUNXI_FUNCTION(0x1, "gpio_out"),
1592 SUNXI_FUNCTION(0x2, "mmc1"), /* DO */
1593 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
1594 SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */
1595 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
1596 SUNXI_FUNCTION(0x0, "gpio_in"),
1597 SUNXI_FUNCTION(0x1, "gpio_out"),
1598 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
1599 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
1600 SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
1601 SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */
1602 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
1603 SUNXI_FUNCTION(0x0, "gpio_in"),
1604 SUNXI_FUNCTION(0x1, "gpio_out"),
1605 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
1606 SUNXI_FUNCTION(0x5, "uart2"), /* TX */
1607 SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */
1608 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
1609 SUNXI_FUNCTION(0x0, "gpio_in"),
1610 SUNXI_FUNCTION(0x1, "gpio_out"),
1611 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
1612 SUNXI_FUNCTION(0x5, "uart2"), /* RX */
1613 SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */
1614 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
1615 SUNXI_FUNCTION(0x0, "gpio_in"),
1616 SUNXI_FUNCTION(0x1, "gpio_out"),
1617 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
1618 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
1619 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
1620 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
1621 SUNXI_FUNCTION(0x0, "gpio_in"),
1622 SUNXI_FUNCTION(0x1, "gpio_out"),
1623 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
1624 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
1625 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
1626 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
1627 SUNXI_FUNCTION(0x0, "gpio_in"),
1628 SUNXI_FUNCTION(0x1, "gpio_out"),
1629 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1630 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
1631 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
1632 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
1633 SUNXI_FUNCTION(0x0, "gpio_in"),
1634 SUNXI_FUNCTION(0x1, "gpio_out"),
1635 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
1636 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
1637 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
1638 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG13,
1639 SUNXI_FUNCTION(0x0, "gpio_in"),
1640 SUNXI_FUNCTION(0x1, "gpio_out"),
1641 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
1642 SUNXI_FUNCTION(0x3, "uart3"), /* PWM1 */
1643 SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
1644 SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
1645 };
1646
1007 static const struct sunxi_desc_pin sun5i_a13_pins[] = { 1647 static const struct sunxi_desc_pin sun5i_a13_pins[] = {
1008 /* Hole */ 1648 /* Hole */
1009 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, 1649 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
1010 SUNXI_FUNCTION(0x0, "gpio_in"), 1650 SUNXI_FUNCTION(0x0, "gpio_in"),
1011 SUNXI_FUNCTION(0x1, "gpio_out"), 1651 SUNXI_FUNCTION(0x1, "gpio_out"),
1012 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ 1652 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
1013 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, 1653 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
1014 SUNXI_FUNCTION(0x0, "gpio_in"), 1654 SUNXI_FUNCTION(0x0, "gpio_in"),
1015 SUNXI_FUNCTION(0x1, "gpio_out"), 1655 SUNXI_FUNCTION(0x1, "gpio_out"),
1016 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ 1656 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
1017 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, 1657 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
1018 SUNXI_FUNCTION(0x0, "gpio_in"), 1658 SUNXI_FUNCTION(0x0, "gpio_in"),
1019 SUNXI_FUNCTION(0x1, "gpio_out"), 1659 SUNXI_FUNCTION(0x1, "gpio_out"),
1020 SUNXI_FUNCTION(0x2, "pwm"), 1660 SUNXI_FUNCTION(0x2, "pwm"),
1021 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */ 1661 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
1022 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, 1662 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
1023 SUNXI_FUNCTION(0x0, "gpio_in"), 1663 SUNXI_FUNCTION(0x0, "gpio_in"),
1024 SUNXI_FUNCTION(0x1, "gpio_out"), 1664 SUNXI_FUNCTION(0x1, "gpio_out"),
1025 SUNXI_FUNCTION(0x2, "ir0"), /* TX */ 1665 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
1026 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */ 1666 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
1027 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, 1667 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
1028 SUNXI_FUNCTION(0x0, "gpio_in"), 1668 SUNXI_FUNCTION(0x0, "gpio_in"),
1029 SUNXI_FUNCTION(0x1, "gpio_out"), 1669 SUNXI_FUNCTION(0x1, "gpio_out"),
1030 SUNXI_FUNCTION(0x2, "ir0"), /* RX */ 1670 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
1031 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */ 1671 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
1032 /* Hole */ 1672 /* Hole */
1033 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, 1673 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
1034 SUNXI_FUNCTION(0x0, "gpio_in"), 1674 SUNXI_FUNCTION(0x0, "gpio_in"),
1035 SUNXI_FUNCTION(0x1, "gpio_out"), 1675 SUNXI_FUNCTION(0x1, "gpio_out"),
1036 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */ 1676 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
1037 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ 1677 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
1038 /* Hole */ 1678 /* Hole */
1039 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, 1679 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
1040 SUNXI_FUNCTION(0x0, "gpio_in"), 1680 SUNXI_FUNCTION(0x0, "gpio_in"),
1041 SUNXI_FUNCTION(0x1, "gpio_out"), 1681 SUNXI_FUNCTION(0x1, "gpio_out"),
1042 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ 1682 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
1043 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, 1683 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
1044 SUNXI_FUNCTION(0x0, "gpio_in"), 1684 SUNXI_FUNCTION(0x0, "gpio_in"),
1045 SUNXI_FUNCTION(0x1, "gpio_out"), 1685 SUNXI_FUNCTION(0x1, "gpio_out"),
1046 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ 1686 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
1047 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, 1687 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
1048 SUNXI_FUNCTION(0x0, "gpio_in"), 1688 SUNXI_FUNCTION(0x0, "gpio_in"),
1049 SUNXI_FUNCTION(0x1, "gpio_out"), 1689 SUNXI_FUNCTION(0x1, "gpio_out"),
1050 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ 1690 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
1051 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, 1691 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
1052 SUNXI_FUNCTION(0x0, "gpio_in"), 1692 SUNXI_FUNCTION(0x0, "gpio_in"),
1053 SUNXI_FUNCTION(0x1, "gpio_out"), 1693 SUNXI_FUNCTION(0x1, "gpio_out"),
1054 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ 1694 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
1055 /* Hole */ 1695 /* Hole */
1056 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, 1696 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
1057 SUNXI_FUNCTION(0x0, "gpio_in"), 1697 SUNXI_FUNCTION(0x0, "gpio_in"),
1058 SUNXI_FUNCTION(0x1, "gpio_out"), 1698 SUNXI_FUNCTION(0x1, "gpio_out"),
1059 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ 1699 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
1060 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ 1700 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
1061 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, 1701 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
1062 SUNXI_FUNCTION(0x0, "gpio_in"), 1702 SUNXI_FUNCTION(0x0, "gpio_in"),
1063 SUNXI_FUNCTION(0x1, "gpio_out"), 1703 SUNXI_FUNCTION(0x1, "gpio_out"),
1064 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ 1704 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
1065 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ 1705 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
1066 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, 1706 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
1067 SUNXI_FUNCTION(0x0, "gpio_in"), 1707 SUNXI_FUNCTION(0x0, "gpio_in"),
1068 SUNXI_FUNCTION(0x1, "gpio_out"), 1708 SUNXI_FUNCTION(0x1, "gpio_out"),
1069 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ 1709 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
1070 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ 1710 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
1071 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, 1711 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
1072 SUNXI_FUNCTION(0x0, "gpio_in"), 1712 SUNXI_FUNCTION(0x0, "gpio_in"),
1073 SUNXI_FUNCTION(0x1, "gpio_out"), 1713 SUNXI_FUNCTION(0x1, "gpio_out"),
1074 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */ 1714 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
1075 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ 1715 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
1076 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, 1716 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
1077 SUNXI_FUNCTION(0x0, "gpio_in"), 1717 SUNXI_FUNCTION(0x0, "gpio_in"),
1078 SUNXI_FUNCTION(0x1, "gpio_out"), 1718 SUNXI_FUNCTION(0x1, "gpio_out"),
1079 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ 1719 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
1080 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, 1720 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
1081 SUNXI_FUNCTION(0x0, "gpio_in"), 1721 SUNXI_FUNCTION(0x0, "gpio_in"),
1082 SUNXI_FUNCTION(0x1, "gpio_out"), 1722 SUNXI_FUNCTION(0x1, "gpio_out"),
1083 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */ 1723 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
1084 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, 1724 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
1085 SUNXI_FUNCTION(0x0, "gpio_in"), 1725 SUNXI_FUNCTION(0x0, "gpio_in"),
1086 SUNXI_FUNCTION(0x1, "gpio_out"), 1726 SUNXI_FUNCTION(0x1, "gpio_out"),
1087 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ 1727 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
1088 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ 1728 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
1089 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, 1729 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
1090 SUNXI_FUNCTION(0x0, "gpio_in"), 1730 SUNXI_FUNCTION(0x0, "gpio_in"),
1091 SUNXI_FUNCTION(0x1, "gpio_out"), 1731 SUNXI_FUNCTION(0x1, "gpio_out"),
1092 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ 1732 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
1093 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ 1733 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
1094 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, 1734 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
1095 SUNXI_FUNCTION(0x0, "gpio_in"), 1735 SUNXI_FUNCTION(0x0, "gpio_in"),
1096 SUNXI_FUNCTION(0x1, "gpio_out"), 1736 SUNXI_FUNCTION(0x1, "gpio_out"),
1097 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ 1737 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
1098 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ 1738 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
1099 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, 1739 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
1100 SUNXI_FUNCTION(0x0, "gpio_in"), 1740 SUNXI_FUNCTION(0x0, "gpio_in"),
1101 SUNXI_FUNCTION(0x1, "gpio_out"), 1741 SUNXI_FUNCTION(0x1, "gpio_out"),
1102 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ 1742 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
1103 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ 1743 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
1104 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, 1744 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
1105 SUNXI_FUNCTION(0x0, "gpio_in"), 1745 SUNXI_FUNCTION(0x0, "gpio_in"),
1106 SUNXI_FUNCTION(0x1, "gpio_out"), 1746 SUNXI_FUNCTION(0x1, "gpio_out"),
1107 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ 1747 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
1108 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ 1748 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
1109 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, 1749 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
1110 SUNXI_FUNCTION(0x0, "gpio_in"), 1750 SUNXI_FUNCTION(0x0, "gpio_in"),
1111 SUNXI_FUNCTION(0x1, "gpio_out"), 1751 SUNXI_FUNCTION(0x1, "gpio_out"),
1112 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ 1752 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
1113 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ 1753 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
1114 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, 1754 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
1115 SUNXI_FUNCTION(0x0, "gpio_in"), 1755 SUNXI_FUNCTION(0x0, "gpio_in"),
1116 SUNXI_FUNCTION(0x1, "gpio_out"), 1756 SUNXI_FUNCTION(0x1, "gpio_out"),
1117 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ 1757 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
1118 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ 1758 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
1119 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, 1759 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
1120 SUNXI_FUNCTION(0x0, "gpio_in"), 1760 SUNXI_FUNCTION(0x0, "gpio_in"),
1121 SUNXI_FUNCTION(0x1, "gpio_out"), 1761 SUNXI_FUNCTION(0x1, "gpio_out"),
1122 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ 1762 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
1123 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ 1763 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
1124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, 1764 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
1125 SUNXI_FUNCTION(0x0, "gpio_in"), 1765 SUNXI_FUNCTION(0x0, "gpio_in"),
1126 SUNXI_FUNCTION(0x1, "gpio_out"), 1766 SUNXI_FUNCTION(0x1, "gpio_out"),
1127 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ 1767 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
1128 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ 1768 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
1129 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, 1769 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
1130 SUNXI_FUNCTION(0x0, "gpio_in"), 1770 SUNXI_FUNCTION(0x0, "gpio_in"),
1131 SUNXI_FUNCTION(0x1, "gpio_out"), 1771 SUNXI_FUNCTION(0x1, "gpio_out"),
1132 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ 1772 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
1133 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ 1773 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
1134 /* Hole */ 1774 /* Hole */
1135 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, 1775 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
1136 SUNXI_FUNCTION(0x0, "gpio_in"), 1776 SUNXI_FUNCTION(0x0, "gpio_in"),
1137 SUNXI_FUNCTION(0x1, "gpio_out"), 1777 SUNXI_FUNCTION(0x1, "gpio_out"),
1138 SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */ 1778 SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
1139 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */ 1779 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
1140 /* Hole */ 1780 /* Hole */
1141 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, 1781 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
1142 SUNXI_FUNCTION(0x0, "gpio_in"), 1782 SUNXI_FUNCTION(0x0, "gpio_in"),
1143 SUNXI_FUNCTION(0x1, "gpio_out"), 1783 SUNXI_FUNCTION(0x1, "gpio_out"),
1144 SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */ 1784 SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */
1145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, 1785 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
1146 SUNXI_FUNCTION(0x0, "gpio_in"), 1786 SUNXI_FUNCTION(0x0, "gpio_in"),
1147 SUNXI_FUNCTION(0x1, "gpio_out"), 1787 SUNXI_FUNCTION(0x1, "gpio_out"),
1148 SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */ 1788 SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */
1149 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, 1789 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
1150 SUNXI_FUNCTION(0x0, "gpio_in"), 1790 SUNXI_FUNCTION(0x0, "gpio_in"),
1151 SUNXI_FUNCTION(0x1, "gpio_out"), 1791 SUNXI_FUNCTION(0x1, "gpio_out"),
1152 SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */ 1792 SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */
1153 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, 1793 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
1154 SUNXI_FUNCTION(0x0, "gpio_in"), 1794 SUNXI_FUNCTION(0x0, "gpio_in"),
1155 SUNXI_FUNCTION(0x1, "gpio_out"), 1795 SUNXI_FUNCTION(0x1, "gpio_out"),
1156 SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */ 1796 SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */
1157 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, 1797 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
1158 SUNXI_FUNCTION(0x0, "gpio_in"), 1798 SUNXI_FUNCTION(0x0, "gpio_in"),
1159 SUNXI_FUNCTION(0x1, "gpio_out"), 1799 SUNXI_FUNCTION(0x1, "gpio_out"),
1160 SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */ 1800 SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */
1161 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, 1801 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
1162 SUNXI_FUNCTION(0x0, "gpio_in"), 1802 SUNXI_FUNCTION(0x0, "gpio_in"),
1163 SUNXI_FUNCTION(0x1, "gpio_out"), 1803 SUNXI_FUNCTION(0x1, "gpio_out"),
1164 SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */ 1804 SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */
1165 /* Hole */ 1805 /* Hole */
1166 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, 1806 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
1167 SUNXI_FUNCTION(0x0, "gpio_in"), 1807 SUNXI_FUNCTION(0x0, "gpio_in"),
1168 SUNXI_FUNCTION(0x1, "gpio_out"), 1808 SUNXI_FUNCTION(0x1, "gpio_out"),
1169 SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */ 1809 SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
1170 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, 1810 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
1171 SUNXI_FUNCTION(0x0, "gpio_in"), 1811 SUNXI_FUNCTION(0x0, "gpio_in"),
1172 SUNXI_FUNCTION(0x1, "gpio_out"), 1812 SUNXI_FUNCTION(0x1, "gpio_out"),
1173 SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */ 1813 SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
1174 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, 1814 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
1175 SUNXI_FUNCTION(0x0, "gpio_in"), 1815 SUNXI_FUNCTION(0x0, "gpio_in"),
1176 SUNXI_FUNCTION(0x1, "gpio_out"), 1816 SUNXI_FUNCTION(0x1, "gpio_out"),
1177 SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */ 1817 SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
1178 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, 1818 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
1179 SUNXI_FUNCTION(0x0, "gpio_in"), 1819 SUNXI_FUNCTION(0x0, "gpio_in"),
1180 SUNXI_FUNCTION(0x1, "gpio_out"), 1820 SUNXI_FUNCTION(0x1, "gpio_out"),
1181 SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */ 1821 SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
1182 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, 1822 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
1183 SUNXI_FUNCTION(0x0, "gpio_in"), 1823 SUNXI_FUNCTION(0x0, "gpio_in"),
1184 SUNXI_FUNCTION(0x1, "gpio_out"), 1824 SUNXI_FUNCTION(0x1, "gpio_out"),
1185 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */ 1825 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
1186 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, 1826 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
1187 SUNXI_FUNCTION(0x0, "gpio_in"), 1827 SUNXI_FUNCTION(0x0, "gpio_in"),
1188 SUNXI_FUNCTION(0x1, "gpio_out"), 1828 SUNXI_FUNCTION(0x1, "gpio_out"),
1189 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */ 1829 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
1190 /* Hole */ 1830 /* Hole */
1191 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, 1831 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
1192 SUNXI_FUNCTION(0x0, "gpio_in"), 1832 SUNXI_FUNCTION(0x0, "gpio_in"),
1193 SUNXI_FUNCTION(0x1, "gpio_out"), 1833 SUNXI_FUNCTION(0x1, "gpio_out"),
1194 SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */ 1834 SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
1195 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, 1835 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
1196 SUNXI_FUNCTION(0x0, "gpio_in"), 1836 SUNXI_FUNCTION(0x0, "gpio_in"),
1197 SUNXI_FUNCTION(0x1, "gpio_out"), 1837 SUNXI_FUNCTION(0x1, "gpio_out"),
1198 SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */ 1838 SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
1199 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, 1839 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
1200 SUNXI_FUNCTION(0x0, "gpio_in"), 1840 SUNXI_FUNCTION(0x0, "gpio_in"),
1201 SUNXI_FUNCTION(0x1, "gpio_out"), 1841 SUNXI_FUNCTION(0x1, "gpio_out"),
1202 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */ 1842 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
1203 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, 1843 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
1204 SUNXI_FUNCTION(0x0, "gpio_in"), 1844 SUNXI_FUNCTION(0x0, "gpio_in"),
1205 SUNXI_FUNCTION(0x1, "gpio_out"), 1845 SUNXI_FUNCTION(0x1, "gpio_out"),
1206 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */ 1846 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
1207 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, 1847 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
1208 SUNXI_FUNCTION(0x0, "gpio_in"), 1848 SUNXI_FUNCTION(0x0, "gpio_in"),
1209 SUNXI_FUNCTION(0x1, "gpio_out"), 1849 SUNXI_FUNCTION(0x1, "gpio_out"),
1210 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */ 1850 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
1211 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, 1851 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
1212 SUNXI_FUNCTION(0x0, "gpio_in"), 1852 SUNXI_FUNCTION(0x0, "gpio_in"),
1213 SUNXI_FUNCTION(0x1, "gpio_out"), 1853 SUNXI_FUNCTION(0x1, "gpio_out"),
1214 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */ 1854 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
1215 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, 1855 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
1216 SUNXI_FUNCTION(0x0, "gpio_in"), 1856 SUNXI_FUNCTION(0x0, "gpio_in"),
1217 SUNXI_FUNCTION(0x1, "gpio_out"), 1857 SUNXI_FUNCTION(0x1, "gpio_out"),
1218 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */ 1858 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
1219 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, 1859 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
1220 SUNXI_FUNCTION(0x0, "gpio_in"), 1860 SUNXI_FUNCTION(0x0, "gpio_in"),
1221 SUNXI_FUNCTION(0x1, "gpio_out"), 1861 SUNXI_FUNCTION(0x1, "gpio_out"),
1222 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */ 1862 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
1223 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, 1863 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
1224 SUNXI_FUNCTION(0x0, "gpio_in"), 1864 SUNXI_FUNCTION(0x0, "gpio_in"),
1225 SUNXI_FUNCTION(0x1, "gpio_out"), 1865 SUNXI_FUNCTION(0x1, "gpio_out"),
1226 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */ 1866 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
1227 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, 1867 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
1228 SUNXI_FUNCTION(0x0, "gpio_in"), 1868 SUNXI_FUNCTION(0x0, "gpio_in"),
1229 SUNXI_FUNCTION(0x1, "gpio_out"), 1869 SUNXI_FUNCTION(0x1, "gpio_out"),
1230 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */ 1870 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
1231 /* Hole */ 1871 /* Hole */
1232 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, 1872 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
1233 SUNXI_FUNCTION(0x0, "gpio_in"), 1873 SUNXI_FUNCTION(0x0, "gpio_in"),
1234 SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */ 1874 SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */
1235 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */ 1875 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
1236 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */ 1876 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
1237 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, 1877 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
1238 SUNXI_FUNCTION(0x0, "gpio_in"), 1878 SUNXI_FUNCTION(0x0, "gpio_in"),
1239 SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */ 1879 SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */
1240 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */ 1880 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
1241 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */ 1881 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
1242 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, 1882 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
1243 SUNXI_FUNCTION(0x0, "gpio_in"), 1883 SUNXI_FUNCTION(0x0, "gpio_in"),
1244 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */ 1884 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
1245 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */ 1885 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
1246 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, 1886 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
1247 SUNXI_FUNCTION(0x0, "gpio_in"), 1887 SUNXI_FUNCTION(0x0, "gpio_in"),
1248 SUNXI_FUNCTION(0x1, "gpio_out"), 1888 SUNXI_FUNCTION(0x1, "gpio_out"),
1249 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */ 1889 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
1250 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */ 1890 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
1251 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, 1891 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
1252 SUNXI_FUNCTION(0x0, "gpio_in"), 1892 SUNXI_FUNCTION(0x0, "gpio_in"),
1253 SUNXI_FUNCTION(0x1, "gpio_out"), 1893 SUNXI_FUNCTION(0x1, "gpio_out"),
1254 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */ 1894 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
1255 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */ 1895 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
1256 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, 1896 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
1257 SUNXI_FUNCTION(0x0, "gpio_in"), 1897 SUNXI_FUNCTION(0x0, "gpio_in"),
1258 SUNXI_FUNCTION(0x1, "gpio_out"), 1898 SUNXI_FUNCTION(0x1, "gpio_out"),
1259 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ 1899 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
1260 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */ 1900 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
1261 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, 1901 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
1262 SUNXI_FUNCTION(0x0, "gpio_in"), 1902 SUNXI_FUNCTION(0x0, "gpio_in"),
1263 SUNXI_FUNCTION(0x1, "gpio_out"), 1903 SUNXI_FUNCTION(0x1, "gpio_out"),
1264 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */ 1904 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
1265 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */ 1905 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
1266 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, 1906 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
1267 SUNXI_FUNCTION(0x0, "gpio_in"), 1907 SUNXI_FUNCTION(0x0, "gpio_in"),
1268 SUNXI_FUNCTION(0x1, "gpio_out"), 1908 SUNXI_FUNCTION(0x1, "gpio_out"),
1269 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */ 1909 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
1270 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */ 1910 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
1271 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, 1911 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
1272 SUNXI_FUNCTION(0x0, "gpio_in"), 1912 SUNXI_FUNCTION(0x0, "gpio_in"),
1273 SUNXI_FUNCTION(0x1, "gpio_out"), 1913 SUNXI_FUNCTION(0x1, "gpio_out"),
1274 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */ 1914 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
1275 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */ 1915 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
1276 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, 1916 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
1277 SUNXI_FUNCTION(0x0, "gpio_in"), 1917 SUNXI_FUNCTION(0x0, "gpio_in"),
1278 SUNXI_FUNCTION(0x1, "gpio_out"), 1918 SUNXI_FUNCTION(0x1, "gpio_out"),
1279 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */ 1919 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
1280 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */ 1920 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
1281 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, 1921 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
1282 SUNXI_FUNCTION(0x0, "gpio_in"), 1922 SUNXI_FUNCTION(0x0, "gpio_in"),
1283 SUNXI_FUNCTION(0x1, "gpio_out"), 1923 SUNXI_FUNCTION(0x1, "gpio_out"),
1284 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */ 1924 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
1285 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 1925 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
1286 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, 1926 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
1287 SUNXI_FUNCTION(0x0, "gpio_in"), 1927 SUNXI_FUNCTION(0x0, "gpio_in"),
1288 SUNXI_FUNCTION(0x1, "gpio_out"), 1928 SUNXI_FUNCTION(0x1, "gpio_out"),
1289 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */ 1929 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
1290 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 1930 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
1291 /* Hole */ 1931 /* Hole */
1292 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, 1932 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
1293 SUNXI_FUNCTION(0x0, "gpio_in"), 1933 SUNXI_FUNCTION(0x0, "gpio_in"),
1294 SUNXI_FUNCTION(0x1, "gpio_out"), 1934 SUNXI_FUNCTION(0x1, "gpio_out"),
1295 SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */ 1935 SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */
1296 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, 1936 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
1297 SUNXI_FUNCTION(0x0, "gpio_in"), 1937 SUNXI_FUNCTION(0x0, "gpio_in"),
1298 SUNXI_FUNCTION(0x1, "gpio_out"), 1938 SUNXI_FUNCTION(0x1, "gpio_out"),
1299 SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */ 1939 SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */
1300 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, 1940 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
1301 SUNXI_FUNCTION(0x0, "gpio_in"), 1941 SUNXI_FUNCTION(0x0, "gpio_in"),
1302 SUNXI_FUNCTION(0x1, "gpio_out"), 1942 SUNXI_FUNCTION(0x1, "gpio_out"),
1303 SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */ 1943 SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */
1304 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, 1944 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
1305 SUNXI_FUNCTION(0x0, "gpio_in"), 1945 SUNXI_FUNCTION(0x0, "gpio_in"),
1306 SUNXI_FUNCTION(0x1, "gpio_out"), 1946 SUNXI_FUNCTION(0x1, "gpio_out"),
1307 SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */ 1947 SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */
1308 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, 1948 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
1309 SUNXI_FUNCTION(0x0, "gpio_in"), 1949 SUNXI_FUNCTION(0x0, "gpio_in"),
1310 SUNXI_FUNCTION(0x1, "gpio_out"), 1950 SUNXI_FUNCTION(0x1, "gpio_out"),
1311 SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */ 1951 SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */
1312 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, 1952 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
1313 SUNXI_FUNCTION(0x0, "gpio_in"), 1953 SUNXI_FUNCTION(0x0, "gpio_in"),
1314 SUNXI_FUNCTION(0x1, "gpio_out"), 1954 SUNXI_FUNCTION(0x1, "gpio_out"),
1315 SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */ 1955 SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */
1316 /* Hole */ 1956 /* Hole */
1317 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, 1957 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
1318 SUNXI_FUNCTION(0x0, "gpio_in"), 1958 SUNXI_FUNCTION(0x0, "gpio_in"),
1319 SUNXI_FUNCTION(0x1, "gpio_out"), 1959 SUNXI_FUNCTION(0x1, "gpio_out"),
1320 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */ 1960 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
1321 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, 1961 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
1322 SUNXI_FUNCTION(0x0, "gpio_in"), 1962 SUNXI_FUNCTION(0x0, "gpio_in"),
1323 SUNXI_FUNCTION(0x1, "gpio_out"), 1963 SUNXI_FUNCTION(0x1, "gpio_out"),
1324 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */ 1964 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
1325 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, 1965 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
1326 SUNXI_FUNCTION(0x0, "gpio_in"), 1966 SUNXI_FUNCTION(0x0, "gpio_in"),
1327 SUNXI_FUNCTION(0x1, "gpio_out"), 1967 SUNXI_FUNCTION(0x1, "gpio_out"),
1328 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */ 1968 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
1329 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, 1969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
1330 SUNXI_FUNCTION(0x0, "gpio_in"), 1970 SUNXI_FUNCTION(0x0, "gpio_in"),
1331 SUNXI_FUNCTION(0x1, "gpio_out"), 1971 SUNXI_FUNCTION(0x1, "gpio_out"),
1332 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ 1972 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
1333 SUNXI_FUNCTION(0x4, "uart1"), /* TX */ 1973 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
1334 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */ 1974 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
1335 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, 1975 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
1336 SUNXI_FUNCTION(0x0, "gpio_in"), 1976 SUNXI_FUNCTION(0x0, "gpio_in"),
1337 SUNXI_FUNCTION(0x1, "gpio_out"), 1977 SUNXI_FUNCTION(0x1, "gpio_out"),
1338 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ 1978 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
1339 SUNXI_FUNCTION(0x4, "uart1"), /* RX */ 1979 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
1340 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */ 1980 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
1341 /* Hole */ 1981 /* Hole */
1342 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, 1982 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
1343 SUNXI_FUNCTION(0x0, "gpio_in"), 1983 SUNXI_FUNCTION(0x0, "gpio_in"),
1344 SUNXI_FUNCTION(0x1, "gpio_out"), 1984 SUNXI_FUNCTION(0x1, "gpio_out"),
1345 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ 1985 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
1346 SUNXI_FUNCTION(0x3, "uart3"), /* TX */ 1986 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
1347 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */ 1987 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
1348 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, 1988 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
1349 SUNXI_FUNCTION(0x0, "gpio_in"), 1989 SUNXI_FUNCTION(0x0, "gpio_in"),
1350 SUNXI_FUNCTION(0x1, "gpio_out"), 1990 SUNXI_FUNCTION(0x1, "gpio_out"),
1351 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ 1991 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
1352 SUNXI_FUNCTION(0x3, "uart3"), /* RX */ 1992 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
1353 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */ 1993 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
1354 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, 1994 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
1355 SUNXI_FUNCTION(0x0, "gpio_in"), 1995 SUNXI_FUNCTION(0x0, "gpio_in"),
1356 SUNXI_FUNCTION(0x1, "gpio_out"), 1996 SUNXI_FUNCTION(0x1, "gpio_out"),
1357 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ 1997 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1358 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ 1998 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
1359 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */ 1999 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
1360 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12, 2000 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
1361 SUNXI_FUNCTION(0x0, "gpio_in"), 2001 SUNXI_FUNCTION(0x0, "gpio_in"),
1362 SUNXI_FUNCTION(0x1, "gpio_out"), 2002 SUNXI_FUNCTION(0x1, "gpio_out"),
1363 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ 2003 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
1364 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ 2004 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
1365 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ 2005 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
1366 }; 2006 };
1367 2007
1368 static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { 2008 static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
1369 .pins = sun4i_a10_pins, 2009 .pins = sun4i_a10_pins,
1370 .npins = ARRAY_SIZE(sun4i_a10_pins), 2010 .npins = ARRAY_SIZE(sun4i_a10_pins),
2011 };
2012
2013 static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = {
2014 .pins = sun5i_a10s_pins,
2015 .npins = ARRAY_SIZE(sun5i_a10s_pins),
1371 }; 2016 };
1372 2017
1373 static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = { 2018 static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
1374 .pins = sun5i_a13_pins, 2019 .pins = sun5i_a13_pins,
1375 .npins = ARRAY_SIZE(sun5i_a13_pins), 2020 .npins = ARRAY_SIZE(sun5i_a13_pins),
1376 }; 2021 };
1377 2022
1378 #endif /* __PINCTRL_SUNXI_PINS_H */ 2023 #endif /* __PINCTRL_SUNXI_PINS_H */
1379 2024
drivers/pinctrl/pinctrl-sunxi.c
Diff comments   View file @ ac68936
1 /* 1 /*
2 * Allwinner A1X SoCs pinctrl driver. 2 * Allwinner A1X SoCs pinctrl driver.
3 * 3 *
4 * Copyright (C) 2012 Maxime Ripard 4 * Copyright (C) 2012 Maxime Ripard
5 * 5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com> 6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 * 7 *
8 * This file is licensed under the terms of the GNU General Public 8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any 9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied. 10 * warranty of any kind, whether express or implied.
11 */ 11 */
12 12
13 #include <linux/io.h> 13 #include <linux/io.h>
14 #include <linux/clk.h> 14 #include <linux/clk.h>
15 #include <linux/gpio.h> 15 #include <linux/gpio.h>
16 #include <linux/irqdomain.h> 16 #include <linux/irqdomain.h>
17 #include <linux/module.h> 17 #include <linux/module.h>
18 #include <linux/of.h> 18 #include <linux/of.h>
19 #include <linux/of_address.h> 19 #include <linux/of_address.h>
20 #include <linux/of_device.h> 20 #include <linux/of_device.h>
21 #include <linux/of_irq.h> 21 #include <linux/of_irq.h>
22 #include <linux/pinctrl/consumer.h> 22 #include <linux/pinctrl/consumer.h>
23 #include <linux/pinctrl/machine.h> 23 #include <linux/pinctrl/machine.h>
24 #include <linux/pinctrl/pinctrl.h> 24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinconf-generic.h> 25 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/pinctrl/pinmux.h> 26 #include <linux/pinctrl/pinmux.h>
27 #include <linux/platform_device.h> 27 #include <linux/platform_device.h>
28 #include <linux/slab.h> 28 #include <linux/slab.h>
29 29
30 #include "core.h" 30 #include "core.h"
31 #include "pinctrl-sunxi.h" 31 #include "pinctrl-sunxi.h"
32 #include "pinctrl-sunxi-pins.h" 32 #include "pinctrl-sunxi-pins.h"
33 33
34 static struct sunxi_pinctrl_group * 34 static struct sunxi_pinctrl_group *
35 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 35 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
36 { 36 {
37 int i; 37 int i;
38 38
39 for (i = 0; i < pctl->ngroups; i++) { 39 for (i = 0; i < pctl->ngroups; i++) {
40 struct sunxi_pinctrl_group *grp = pctl->groups + i; 40 struct sunxi_pinctrl_group *grp = pctl->groups + i;
41 41
42 if (!strcmp(grp->name, group)) 42 if (!strcmp(grp->name, group))
43 return grp; 43 return grp;
44 } 44 }
45 45
46 return NULL; 46 return NULL;
47 } 47 }
48 48
49 static struct sunxi_pinctrl_function * 49 static struct sunxi_pinctrl_function *
50 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, 50 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
51 const char *name) 51 const char *name)
52 { 52 {
53 struct sunxi_pinctrl_function *func = pctl->functions; 53 struct sunxi_pinctrl_function *func = pctl->functions;
54 int i; 54 int i;
55 55
56 for (i = 0; i < pctl->nfunctions; i++) { 56 for (i = 0; i < pctl->nfunctions; i++) {
57 if (!func[i].name) 57 if (!func[i].name)
58 break; 58 break;
59 59
60 if (!strcmp(func[i].name, name)) 60 if (!strcmp(func[i].name, name))
61 return func + i; 61 return func + i;
62 } 62 }
63 63
64 return NULL; 64 return NULL;
65 } 65 }
66 66
67 static struct sunxi_desc_function * 67 static struct sunxi_desc_function *
68 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, 68 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
69 const char *pin_name, 69 const char *pin_name,
70 const char *func_name) 70 const char *func_name)
71 { 71 {
72 int i; 72 int i;
73 73
74 for (i = 0; i < pctl->desc->npins; i++) { 74 for (i = 0; i < pctl->desc->npins; i++) {
75 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 75 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
76 76
77 if (!strcmp(pin->pin.name, pin_name)) { 77 if (!strcmp(pin->pin.name, pin_name)) {
78 struct sunxi_desc_function *func = pin->functions; 78 struct sunxi_desc_function *func = pin->functions;
79 79
80 while (func->name) { 80 while (func->name) {
81 if (!strcmp(func->name, func_name)) 81 if (!strcmp(func->name, func_name))
82 return func; 82 return func;
83 83
84 func++; 84 func++;
85 } 85 }
86 } 86 }
87 } 87 }
88 88
89 return NULL; 89 return NULL;
90 } 90 }
91 91
92 static struct sunxi_desc_function * 92 static struct sunxi_desc_function *
93 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl, 93 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
94 const u16 pin_num, 94 const u16 pin_num,
95 const char *func_name) 95 const char *func_name)
96 { 96 {
97 int i; 97 int i;
98 98
99 for (i = 0; i < pctl->desc->npins; i++) { 99 for (i = 0; i < pctl->desc->npins; i++) {
100 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 100 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
101 101
102 if (pin->pin.number == pin_num) { 102 if (pin->pin.number == pin_num) {
103 struct sunxi_desc_function *func = pin->functions; 103 struct sunxi_desc_function *func = pin->functions;
104 104
105 while (func->name) { 105 while (func->name) {
106 if (!strcmp(func->name, func_name)) 106 if (!strcmp(func->name, func_name))
107 return func; 107 return func;
108 108
109 func++; 109 func++;
110 } 110 }
111 } 111 }
112 } 112 }
113 113
114 return NULL; 114 return NULL;
115 } 115 }
116 116
117 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 117 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
118 { 118 {
119 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 119 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
120 120
121 return pctl->ngroups; 121 return pctl->ngroups;
122 } 122 }
123 123
124 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, 124 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
125 unsigned group) 125 unsigned group)
126 { 126 {
127 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 127 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
128 128
129 return pctl->groups[group].name; 129 return pctl->groups[group].name;
130 } 130 }
131 131
132 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 132 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
133 unsigned group, 133 unsigned group,
134 const unsigned **pins, 134 const unsigned **pins,
135 unsigned *num_pins) 135 unsigned *num_pins)
136 { 136 {
137 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 137 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
138 138
139 *pins = (unsigned *)&pctl->groups[group].pin; 139 *pins = (unsigned *)&pctl->groups[group].pin;
140 *num_pins = 1; 140 *num_pins = 1;
141 141
142 return 0; 142 return 0;
143 } 143 }
144 144
145 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 145 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
146 struct device_node *node, 146 struct device_node *node,
147 struct pinctrl_map **map, 147 struct pinctrl_map **map,
148 unsigned *num_maps) 148 unsigned *num_maps)
149 { 149 {
150 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 150 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
151 unsigned long *pinconfig; 151 unsigned long *pinconfig;
152 struct property *prop; 152 struct property *prop;
153 const char *function; 153 const char *function;
154 const char *group; 154 const char *group;
155 int ret, nmaps, i = 0; 155 int ret, nmaps, i = 0;
156 u32 val; 156 u32 val;
157 157
158 *map = NULL; 158 *map = NULL;
159 *num_maps = 0; 159 *num_maps = 0;
160 160
161 ret = of_property_read_string(node, "allwinner,function", &function); 161 ret = of_property_read_string(node, "allwinner,function", &function);
162 if (ret) { 162 if (ret) {
163 dev_err(pctl->dev, 163 dev_err(pctl->dev,
164 "missing allwinner,function property in node %s\n", 164 "missing allwinner,function property in node %s\n",
165 node->name); 165 node->name);
166 return -EINVAL; 166 return -EINVAL;
167 } 167 }
168 168
169 nmaps = of_property_count_strings(node, "allwinner,pins") * 2; 169 nmaps = of_property_count_strings(node, "allwinner,pins") * 2;
170 if (nmaps < 0) { 170 if (nmaps < 0) {
171 dev_err(pctl->dev, 171 dev_err(pctl->dev,
172 "missing allwinner,pins property in node %s\n", 172 "missing allwinner,pins property in node %s\n",
173 node->name); 173 node->name);
174 return -EINVAL; 174 return -EINVAL;
175 } 175 }
176 176
177 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL); 177 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
178 if (!map) 178 if (!map)
179 return -ENOMEM; 179 return -ENOMEM;
180 180
181 of_property_for_each_string(node, "allwinner,pins", prop, group) { 181 of_property_for_each_string(node, "allwinner,pins", prop, group) {
182 struct sunxi_pinctrl_group *grp = 182 struct sunxi_pinctrl_group *grp =
183 sunxi_pinctrl_find_group_by_name(pctl, group); 183 sunxi_pinctrl_find_group_by_name(pctl, group);
184 int j = 0, configlen = 0; 184 int j = 0, configlen = 0;
185 185
186 if (!grp) { 186 if (!grp) {
187 dev_err(pctl->dev, "unknown pin %s", group); 187 dev_err(pctl->dev, "unknown pin %s", group);
188 continue; 188 continue;
189 } 189 }
190 190
191 if (!sunxi_pinctrl_desc_find_function_by_name(pctl, 191 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
192 grp->name, 192 grp->name,
193 function)) { 193 function)) {
194 dev_err(pctl->dev, "unsupported function %s on pin %s", 194 dev_err(pctl->dev, "unsupported function %s on pin %s",
195 function, group); 195 function, group);
196 continue; 196 continue;
197 } 197 }
198 198
199 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; 199 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
200 (*map)[i].data.mux.group = group; 200 (*map)[i].data.mux.group = group;
201 (*map)[i].data.mux.function = function; 201 (*map)[i].data.mux.function = function;
202 202
203 i++; 203 i++;
204 204
205 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; 205 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
206 (*map)[i].data.configs.group_or_pin = group; 206 (*map)[i].data.configs.group_or_pin = group;
207 207
208 if (of_find_property(node, "allwinner,drive", NULL)) 208 if (of_find_property(node, "allwinner,drive", NULL))
209 configlen++; 209 configlen++;
210 if (of_find_property(node, "allwinner,pull", NULL)) 210 if (of_find_property(node, "allwinner,pull", NULL))
211 configlen++; 211 configlen++;
212 212
213 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL); 213 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
214 214
215 if (!of_property_read_u32(node, "allwinner,drive", &val)) { 215 if (!of_property_read_u32(node, "allwinner,drive", &val)) {
216 u16 strength = (val + 1) * 10; 216 u16 strength = (val + 1) * 10;
217 pinconfig[j++] = 217 pinconfig[j++] =
218 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, 218 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
219 strength); 219 strength);
220 } 220 }
221 221
222 if (!of_property_read_u32(node, "allwinner,pull", &val)) { 222 if (!of_property_read_u32(node, "allwinner,pull", &val)) {
223 enum pin_config_param pull = PIN_CONFIG_END; 223 enum pin_config_param pull = PIN_CONFIG_END;
224 if (val == 1) 224 if (val == 1)
225 pull = PIN_CONFIG_BIAS_PULL_UP; 225 pull = PIN_CONFIG_BIAS_PULL_UP;
226 else if (val == 2) 226 else if (val == 2)
227 pull = PIN_CONFIG_BIAS_PULL_DOWN; 227 pull = PIN_CONFIG_BIAS_PULL_DOWN;
228 pinconfig[j++] = pinconf_to_config_packed(pull, 0); 228 pinconfig[j++] = pinconf_to_config_packed(pull, 0);
229 } 229 }
230 230
231 (*map)[i].data.configs.configs = pinconfig; 231 (*map)[i].data.configs.configs = pinconfig;
232 (*map)[i].data.configs.num_configs = configlen; 232 (*map)[i].data.configs.num_configs = configlen;
233 233
234 i++; 234 i++;
235 } 235 }
236 236
237 *num_maps = nmaps; 237 *num_maps = nmaps;
238 238
239 return 0; 239 return 0;
240 } 240 }
241 241
242 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, 242 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
243 struct pinctrl_map *map, 243 struct pinctrl_map *map,
244 unsigned num_maps) 244 unsigned num_maps)
245 { 245 {
246 int i; 246 int i;
247 247
248 for (i = 0; i < num_maps; i++) { 248 for (i = 0; i < num_maps; i++) {
249 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) 249 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
250 kfree(map[i].data.configs.configs); 250 kfree(map[i].data.configs.configs);
251 } 251 }
252 252
253 kfree(map); 253 kfree(map);
254 } 254 }
255 255
256 static const struct pinctrl_ops sunxi_pctrl_ops = { 256 static const struct pinctrl_ops sunxi_pctrl_ops = {
257 .dt_node_to_map = sunxi_pctrl_dt_node_to_map, 257 .dt_node_to_map = sunxi_pctrl_dt_node_to_map,
258 .dt_free_map = sunxi_pctrl_dt_free_map, 258 .dt_free_map = sunxi_pctrl_dt_free_map,
259 .get_groups_count = sunxi_pctrl_get_groups_count, 259 .get_groups_count = sunxi_pctrl_get_groups_count,
260 .get_group_name = sunxi_pctrl_get_group_name, 260 .get_group_name = sunxi_pctrl_get_group_name,
261 .get_group_pins = sunxi_pctrl_get_group_pins, 261 .get_group_pins = sunxi_pctrl_get_group_pins,
262 }; 262 };
263 263
264 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, 264 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
265 unsigned group, 265 unsigned group,
266 unsigned long *config) 266 unsigned long *config)
267 { 267 {
268 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 268 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
269 269
270 *config = pctl->groups[group].config; 270 *config = pctl->groups[group].config;
271 271
272 return 0; 272 return 0;
273 } 273 }
274 274
275 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, 275 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
276 unsigned group, 276 unsigned group,
277 unsigned long config) 277 unsigned long config)
278 { 278 {
279 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 279 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
280 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 280 struct sunxi_pinctrl_group *g = &pctl->groups[group];
281 u32 val, mask; 281 u32 val, mask;
282 u16 strength; 282 u16 strength;
283 u8 dlevel; 283 u8 dlevel;
284 284
285 switch (pinconf_to_config_param(config)) { 285 switch (pinconf_to_config_param(config)) {
286 case PIN_CONFIG_DRIVE_STRENGTH: 286 case PIN_CONFIG_DRIVE_STRENGTH:
287 strength = pinconf_to_config_argument(config); 287 strength = pinconf_to_config_argument(config);
288 if (strength > 40) 288 if (strength > 40)
289 return -EINVAL; 289 return -EINVAL;
290 /* 290 /*
291 * We convert from mA to what the register expects: 291 * We convert from mA to what the register expects:
292 * 0: 10mA 292 * 0: 10mA
293 * 1: 20mA 293 * 1: 20mA
294 * 2: 30mA 294 * 2: 30mA
295 * 3: 40mA 295 * 3: 40mA
296 */ 296 */
297 dlevel = strength / 10 - 1; 297 dlevel = strength / 10 - 1;
298 val = readl(pctl->membase + sunxi_dlevel_reg(g->pin)); 298 val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
299 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin); 299 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
300 writel((val & ~mask) | dlevel << sunxi_dlevel_offset(g->pin), 300 writel((val & ~mask) | dlevel << sunxi_dlevel_offset(g->pin),
301 pctl->membase + sunxi_dlevel_reg(g->pin)); 301 pctl->membase + sunxi_dlevel_reg(g->pin));
302 break; 302 break;
303 case PIN_CONFIG_BIAS_PULL_UP: 303 case PIN_CONFIG_BIAS_PULL_UP:
304 val = readl(pctl->membase + sunxi_pull_reg(g->pin)); 304 val = readl(pctl->membase + sunxi_pull_reg(g->pin));
305 mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); 305 mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
306 writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin), 306 writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
307 pctl->membase + sunxi_pull_reg(g->pin)); 307 pctl->membase + sunxi_pull_reg(g->pin));
308 break; 308 break;
309 case PIN_CONFIG_BIAS_PULL_DOWN: 309 case PIN_CONFIG_BIAS_PULL_DOWN:
310 val = readl(pctl->membase + sunxi_pull_reg(g->pin)); 310 val = readl(pctl->membase + sunxi_pull_reg(g->pin));
311 mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); 311 mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
312 writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin), 312 writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
313 pctl->membase + sunxi_pull_reg(g->pin)); 313 pctl->membase + sunxi_pull_reg(g->pin));
314 break; 314 break;
315 default: 315 default:
316 break; 316 break;
317 } 317 }
318 318
319 /* cache the config value */ 319 /* cache the config value */
320 g->config = config; 320 g->config = config;
321 321
322 return 0; 322 return 0;
323 } 323 }
324 324
325 static const struct pinconf_ops sunxi_pconf_ops = { 325 static const struct pinconf_ops sunxi_pconf_ops = {
326 .pin_config_group_get = sunxi_pconf_group_get, 326 .pin_config_group_get = sunxi_pconf_group_get,
327 .pin_config_group_set = sunxi_pconf_group_set, 327 .pin_config_group_set = sunxi_pconf_group_set,
328 }; 328 };
329 329
330 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 330 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
331 { 331 {
332 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 332 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
333 333
334 return pctl->nfunctions; 334 return pctl->nfunctions;
335 } 335 }
336 336
337 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, 337 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
338 unsigned function) 338 unsigned function)
339 { 339 {
340 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 340 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
341 341
342 return pctl->functions[function].name; 342 return pctl->functions[function].name;
343 } 343 }
344 344
345 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, 345 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
346 unsigned function, 346 unsigned function,
347 const char * const **groups, 347 const char * const **groups,
348 unsigned * const num_groups) 348 unsigned * const num_groups)
349 { 349 {
350 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 350 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
351 351
352 *groups = pctl->functions[function].groups; 352 *groups = pctl->functions[function].groups;
353 *num_groups = pctl->functions[function].ngroups; 353 *num_groups = pctl->functions[function].ngroups;
354 354
355 return 0; 355 return 0;
356 } 356 }
357 357
358 static void sunxi_pmx_set(struct pinctrl_dev *pctldev, 358 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
359 unsigned pin, 359 unsigned pin,
360 u8 config) 360 u8 config)
361 { 361 {
362 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 362 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
363 363
364 u32 val = readl(pctl->membase + sunxi_mux_reg(pin)); 364 u32 val = readl(pctl->membase + sunxi_mux_reg(pin));
365 u32 mask = MUX_PINS_MASK << sunxi_mux_offset(pin); 365 u32 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
366 writel((val & ~mask) | config << sunxi_mux_offset(pin), 366 writel((val & ~mask) | config << sunxi_mux_offset(pin),
367 pctl->membase + sunxi_mux_reg(pin)); 367 pctl->membase + sunxi_mux_reg(pin));
368 } 368 }
369 369
370 static int sunxi_pmx_enable(struct pinctrl_dev *pctldev, 370 static int sunxi_pmx_enable(struct pinctrl_dev *pctldev,
371 unsigned function, 371 unsigned function,
372 unsigned group) 372 unsigned group)
373 { 373 {
374 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 374 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
375 struct sunxi_pinctrl_group *g = pctl->groups + group; 375 struct sunxi_pinctrl_group *g = pctl->groups + group;
376 struct sunxi_pinctrl_function *func = pctl->functions + function; 376 struct sunxi_pinctrl_function *func = pctl->functions + function;
377 struct sunxi_desc_function *desc = 377 struct sunxi_desc_function *desc =
378 sunxi_pinctrl_desc_find_function_by_name(pctl, 378 sunxi_pinctrl_desc_find_function_by_name(pctl,
379 g->name, 379 g->name,
380 func->name); 380 func->name);
381 381
382 if (!desc) 382 if (!desc)
383 return -EINVAL; 383 return -EINVAL;
384 384
385 sunxi_pmx_set(pctldev, g->pin, desc->muxval); 385 sunxi_pmx_set(pctldev, g->pin, desc->muxval);
386 386
387 return 0; 387 return 0;
388 } 388 }
389 389
390 static int 390 static int
391 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 391 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
392 struct pinctrl_gpio_range *range, 392 struct pinctrl_gpio_range *range,
393 unsigned offset, 393 unsigned offset,
394 bool input) 394 bool input)
395 { 395 {
396 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 396 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
397 struct sunxi_desc_function *desc; 397 struct sunxi_desc_function *desc;
398 const char *func; 398 const char *func;
399 399
400 if (input) 400 if (input)
401 func = "gpio_in"; 401 func = "gpio_in";
402 else 402 else
403 func = "gpio_out"; 403 func = "gpio_out";
404 404
405 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func); 405 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
406 if (!desc) 406 if (!desc)
407 return -EINVAL; 407 return -EINVAL;
408 408
409 sunxi_pmx_set(pctldev, offset, desc->muxval); 409 sunxi_pmx_set(pctldev, offset, desc->muxval);
410 410
411 return 0; 411 return 0;
412 } 412 }
413 413
414 static const struct pinmux_ops sunxi_pmx_ops = { 414 static const struct pinmux_ops sunxi_pmx_ops = {
415 .get_functions_count = sunxi_pmx_get_funcs_cnt, 415 .get_functions_count = sunxi_pmx_get_funcs_cnt,
416 .get_function_name = sunxi_pmx_get_func_name, 416 .get_function_name = sunxi_pmx_get_func_name,
417 .get_function_groups = sunxi_pmx_get_func_groups, 417 .get_function_groups = sunxi_pmx_get_func_groups,
418 .enable = sunxi_pmx_enable, 418 .enable = sunxi_pmx_enable,
419 .gpio_set_direction = sunxi_pmx_gpio_set_direction, 419 .gpio_set_direction = sunxi_pmx_gpio_set_direction,
420 }; 420 };
421 421
422 static struct pinctrl_desc sunxi_pctrl_desc = { 422 static struct pinctrl_desc sunxi_pctrl_desc = {
423 .confops = &sunxi_pconf_ops, 423 .confops = &sunxi_pconf_ops,
424 .pctlops = &sunxi_pctrl_ops, 424 .pctlops = &sunxi_pctrl_ops,
425 .pmxops = &sunxi_pmx_ops, 425 .pmxops = &sunxi_pmx_ops,
426 }; 426 };
427 427
428 static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset) 428 static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset)
429 { 429 {
430 return pinctrl_request_gpio(chip->base + offset); 430 return pinctrl_request_gpio(chip->base + offset);
431 } 431 }
432 432
433 static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset) 433 static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset)
434 { 434 {
435 pinctrl_free_gpio(chip->base + offset); 435 pinctrl_free_gpio(chip->base + offset);
436 } 436 }
437 437
438 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, 438 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
439 unsigned offset) 439 unsigned offset)
440 { 440 {
441 return pinctrl_gpio_direction_input(chip->base + offset); 441 return pinctrl_gpio_direction_input(chip->base + offset);
442 } 442 }
443 443
444 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) 444 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
445 { 445 {
446 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); 446 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
447 447
448 u32 reg = sunxi_data_reg(offset); 448 u32 reg = sunxi_data_reg(offset);
449 u8 index = sunxi_data_offset(offset); 449 u8 index = sunxi_data_offset(offset);
450 u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; 450 u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
451 451
452 return val; 452 return val;
453 } 453 }
454 454
455 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, 455 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
456 unsigned offset, int value) 456 unsigned offset, int value)
457 { 457 {
458 return pinctrl_gpio_direction_output(chip->base + offset); 458 return pinctrl_gpio_direction_output(chip->base + offset);
459 } 459 }
460 460
461 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, 461 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
462 unsigned offset, int value) 462 unsigned offset, int value)
463 { 463 {
464 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); 464 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
465 u32 reg = sunxi_data_reg(offset); 465 u32 reg = sunxi_data_reg(offset);
466 u8 index = sunxi_data_offset(offset); 466 u8 index = sunxi_data_offset(offset);
467 467
468 writel((value & DATA_PINS_MASK) << index, pctl->membase + reg); 468 writel((value & DATA_PINS_MASK) << index, pctl->membase + reg);
469 } 469 }
470 470
471 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, 471 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
472 const struct of_phandle_args *gpiospec, 472 const struct of_phandle_args *gpiospec,
473 u32 *flags) 473 u32 *flags)
474 { 474 {
475 int pin, base; 475 int pin, base;
476 476
477 base = PINS_PER_BANK * gpiospec->args[0]; 477 base = PINS_PER_BANK * gpiospec->args[0];
478 pin = base + gpiospec->args[1]; 478 pin = base + gpiospec->args[1];
479 479
480 if (pin > (gc->base + gc->ngpio)) 480 if (pin > (gc->base + gc->ngpio))
481 return -EINVAL; 481 return -EINVAL;
482 482
483 if (flags) 483 if (flags)
484 *flags = gpiospec->args[2]; 484 *flags = gpiospec->args[2];
485 485
486 return pin; 486 return pin;
487 } 487 }
488 488
489 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 489 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
490 { 490 {
491 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); 491 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
492 struct sunxi_desc_function *desc; 492 struct sunxi_desc_function *desc;
493 493
494 if (offset > chip->ngpio) 494 if (offset > chip->ngpio)
495 return -ENXIO; 495 return -ENXIO;
496 496
497 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq"); 497 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq");
498 if (!desc) 498 if (!desc)
499 return -EINVAL; 499 return -EINVAL;
500 500
501 pctl->irq_array[desc->irqnum] = offset; 501 pctl->irq_array[desc->irqnum] = offset;
502 502
503 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", 503 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
504 chip->label, offset + chip->base, desc->irqnum); 504 chip->label, offset + chip->base, desc->irqnum);
505 505
506 return irq_find_mapping(pctl->domain, desc->irqnum); 506 return irq_find_mapping(pctl->domain, desc->irqnum);
507 } 507 }
508 508
509 static struct gpio_chip sunxi_pinctrl_gpio_chip = { 509 static struct gpio_chip sunxi_pinctrl_gpio_chip = {
510 .owner = THIS_MODULE, 510 .owner = THIS_MODULE,
511 .request = sunxi_pinctrl_gpio_request, 511 .request = sunxi_pinctrl_gpio_request,
512 .free = sunxi_pinctrl_gpio_free, 512 .free = sunxi_pinctrl_gpio_free,
513 .direction_input = sunxi_pinctrl_gpio_direction_input, 513 .direction_input = sunxi_pinctrl_gpio_direction_input,
514 .direction_output = sunxi_pinctrl_gpio_direction_output, 514 .direction_output = sunxi_pinctrl_gpio_direction_output,
515 .get = sunxi_pinctrl_gpio_get, 515 .get = sunxi_pinctrl_gpio_get,
516 .set = sunxi_pinctrl_gpio_set, 516 .set = sunxi_pinctrl_gpio_set,
517 .of_xlate = sunxi_pinctrl_gpio_of_xlate, 517 .of_xlate = sunxi_pinctrl_gpio_of_xlate,
518 .to_irq = sunxi_pinctrl_gpio_to_irq, 518 .to_irq = sunxi_pinctrl_gpio_to_irq,
519 .of_gpio_n_cells = 3, 519 .of_gpio_n_cells = 3,
520 .can_sleep = 0, 520 .can_sleep = 0,
521 }; 521 };
522 522
523 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, 523 static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
524 unsigned int type) 524 unsigned int type)
525 { 525 {
526 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 526 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
527 u32 reg = sunxi_irq_cfg_reg(d->hwirq); 527 u32 reg = sunxi_irq_cfg_reg(d->hwirq);
528 u8 index = sunxi_irq_cfg_offset(d->hwirq); 528 u8 index = sunxi_irq_cfg_offset(d->hwirq);
529 u8 mode; 529 u8 mode;
530 530
531 switch (type) { 531 switch (type) {
532 case IRQ_TYPE_EDGE_RISING: 532 case IRQ_TYPE_EDGE_RISING:
533 mode = IRQ_EDGE_RISING; 533 mode = IRQ_EDGE_RISING;
534 break; 534 break;
535 case IRQ_TYPE_EDGE_FALLING: 535 case IRQ_TYPE_EDGE_FALLING:
536 mode = IRQ_EDGE_FALLING; 536 mode = IRQ_EDGE_FALLING;
537 break; 537 break;
538 case IRQ_TYPE_EDGE_BOTH: 538 case IRQ_TYPE_EDGE_BOTH:
539 mode = IRQ_EDGE_BOTH; 539 mode = IRQ_EDGE_BOTH;
540 break; 540 break;
541 case IRQ_TYPE_LEVEL_HIGH: 541 case IRQ_TYPE_LEVEL_HIGH:
542 mode = IRQ_LEVEL_HIGH; 542 mode = IRQ_LEVEL_HIGH;
543 break; 543 break;
544 case IRQ_TYPE_LEVEL_LOW: 544 case IRQ_TYPE_LEVEL_LOW:
545 mode = IRQ_LEVEL_LOW; 545 mode = IRQ_LEVEL_LOW;
546 break; 546 break;
547 default: 547 default:
548 return -EINVAL; 548 return -EINVAL;
549 } 549 }
550 550
551 writel((mode & IRQ_CFG_IRQ_MASK) << index, pctl->membase + reg); 551 writel((mode & IRQ_CFG_IRQ_MASK) << index, pctl->membase + reg);
552 552
553 return 0; 553 return 0;
554 } 554 }
555 555
556 static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d) 556 static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d)
557 { 557 {
558 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 558 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
559 u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq); 559 u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq);
560 u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq); 560 u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq);
561 u32 status_reg = sunxi_irq_status_reg(d->hwirq); 561 u32 status_reg = sunxi_irq_status_reg(d->hwirq);
562 u8 status_idx = sunxi_irq_status_offset(d->hwirq); 562 u8 status_idx = sunxi_irq_status_offset(d->hwirq);
563 u32 val; 563 u32 val;
564 564
565 /* Mask the IRQ */ 565 /* Mask the IRQ */
566 val = readl(pctl->membase + ctrl_reg); 566 val = readl(pctl->membase + ctrl_reg);
567 writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg); 567 writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg);
568 568
569 /* Clear the IRQ */ 569 /* Clear the IRQ */
570 writel(1 << status_idx, pctl->membase + status_reg); 570 writel(1 << status_idx, pctl->membase + status_reg);
571 } 571 }
572 572
573 static void sunxi_pinctrl_irq_mask(struct irq_data *d) 573 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
574 { 574 {
575 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 575 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
576 u32 reg = sunxi_irq_ctrl_reg(d->hwirq); 576 u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
577 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 577 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
578 u32 val; 578 u32 val;
579 579
580 /* Mask the IRQ */ 580 /* Mask the IRQ */
581 val = readl(pctl->membase + reg); 581 val = readl(pctl->membase + reg);
582 writel(val & ~(1 << idx), pctl->membase + reg); 582 writel(val & ~(1 << idx), pctl->membase + reg);
583 } 583 }
584 584
585 static void sunxi_pinctrl_irq_unmask(struct irq_data *d) 585 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
586 { 586 {
587 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 587 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
588 struct sunxi_desc_function *func; 588 struct sunxi_desc_function *func;
589 u32 reg = sunxi_irq_ctrl_reg(d->hwirq); 589 u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
590 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 590 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
591 u32 val; 591 u32 val;
592 592
593 func = sunxi_pinctrl_desc_find_function_by_pin(pctl, 593 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
594 pctl->irq_array[d->hwirq], 594 pctl->irq_array[d->hwirq],
595 "irq"); 595 "irq");
596 596
597 /* Change muxing to INT mode */ 597 /* Change muxing to INT mode */
598 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); 598 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
599 599
600 /* Unmask the IRQ */ 600 /* Unmask the IRQ */
601 val = readl(pctl->membase + reg); 601 val = readl(pctl->membase + reg);
602 writel(val | (1 << idx), pctl->membase + reg); 602 writel(val | (1 << idx), pctl->membase + reg);
603 } 603 }
604 604
605 static struct irq_chip sunxi_pinctrl_irq_chip = { 605 static struct irq_chip sunxi_pinctrl_irq_chip = {
606 .irq_mask = sunxi_pinctrl_irq_mask, 606 .irq_mask = sunxi_pinctrl_irq_mask,
607 .irq_mask_ack = sunxi_pinctrl_irq_mask_ack, 607 .irq_mask_ack = sunxi_pinctrl_irq_mask_ack,
608 .irq_unmask = sunxi_pinctrl_irq_unmask, 608 .irq_unmask = sunxi_pinctrl_irq_unmask,
609 .irq_set_type = sunxi_pinctrl_irq_set_type, 609 .irq_set_type = sunxi_pinctrl_irq_set_type,
610 }; 610 };
611 611
612 static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc) 612 static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
613 { 613 {
614 struct sunxi_pinctrl *pctl = irq_get_handler_data(irq); 614 struct sunxi_pinctrl *pctl = irq_get_handler_data(irq);
615 const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG); 615 const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG);
616 616
617 /* Clear all interrupts */ 617 /* Clear all interrupts */
618 writel(reg, pctl->membase + IRQ_STATUS_REG); 618 writel(reg, pctl->membase + IRQ_STATUS_REG);
619 619
620 if (reg) { 620 if (reg) {
621 int irqoffset; 621 int irqoffset;
622 622
623 for_each_set_bit(irqoffset, &reg, SUNXI_IRQ_NUMBER) { 623 for_each_set_bit(irqoffset, &reg, SUNXI_IRQ_NUMBER) {
624 int pin_irq = irq_find_mapping(pctl->domain, irqoffset); 624 int pin_irq = irq_find_mapping(pctl->domain, irqoffset);
625 generic_handle_irq(pin_irq); 625 generic_handle_irq(pin_irq);
626 } 626 }
627 } 627 }
628 } 628 }
629 629
630 static struct of_device_id sunxi_pinctrl_match[] = { 630 static struct of_device_id sunxi_pinctrl_match[] = {
631 { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data }, 631 { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data },
632 { .compatible = "allwinner,sun5i-a10s-pinctrl", .data = (void *)&sun5i_a10s_pinctrl_data },
632 { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data }, 633 { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
633 {} 634 {}
634 }; 635 };
635 MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match); 636 MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match);
636 637
637 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, 638 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
638 const char *name) 639 const char *name)
639 { 640 {
640 struct sunxi_pinctrl_function *func = pctl->functions; 641 struct sunxi_pinctrl_function *func = pctl->functions;
641 642
642 while (func->name) { 643 while (func->name) {
643 /* function already there */ 644 /* function already there */
644 if (strcmp(func->name, name) == 0) { 645 if (strcmp(func->name, name) == 0) {
645 func->ngroups++; 646 func->ngroups++;
646 return -EEXIST; 647 return -EEXIST;
647 } 648 }
648 func++; 649 func++;
649 } 650 }
650 651
651 func->name = name; 652 func->name = name;
652 func->ngroups = 1; 653 func->ngroups = 1;
653 654
654 pctl->nfunctions++; 655 pctl->nfunctions++;
655 656
656 return 0; 657 return 0;
657 } 658 }
658 659
659 static int sunxi_pinctrl_build_state(struct platform_device *pdev) 660 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
660 { 661 {
661 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); 662 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
662 int i; 663 int i;
663 664
664 pctl->ngroups = pctl->desc->npins; 665 pctl->ngroups = pctl->desc->npins;
665 666
666 /* Allocate groups */ 667 /* Allocate groups */
667 pctl->groups = devm_kzalloc(&pdev->dev, 668 pctl->groups = devm_kzalloc(&pdev->dev,
668 pctl->ngroups * sizeof(*pctl->groups), 669 pctl->ngroups * sizeof(*pctl->groups),
669 GFP_KERNEL); 670 GFP_KERNEL);
670 if (!pctl->groups) 671 if (!pctl->groups)
671 return -ENOMEM; 672 return -ENOMEM;
672 673
673 for (i = 0; i < pctl->desc->npins; i++) { 674 for (i = 0; i < pctl->desc->npins; i++) {
674 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 675 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
675 struct sunxi_pinctrl_group *group = pctl->groups + i; 676 struct sunxi_pinctrl_group *group = pctl->groups + i;
676 677
677 group->name = pin->pin.name; 678 group->name = pin->pin.name;
678 group->pin = pin->pin.number; 679 group->pin = pin->pin.number;
679 } 680 }
680 681
681 /* 682 /*
682 * We suppose that we won't have any more functions than pins, 683 * We suppose that we won't have any more functions than pins,
683 * we'll reallocate that later anyway 684 * we'll reallocate that later anyway
684 */ 685 */
685 pctl->functions = devm_kzalloc(&pdev->dev, 686 pctl->functions = devm_kzalloc(&pdev->dev,
686 pctl->desc->npins * sizeof(*pctl->functions), 687 pctl->desc->npins * sizeof(*pctl->functions),
687 GFP_KERNEL); 688 GFP_KERNEL);
688 if (!pctl->functions) 689 if (!pctl->functions)
689 return -ENOMEM; 690 return -ENOMEM;
690 691
691 /* Count functions and their associated groups */ 692 /* Count functions and their associated groups */
692 for (i = 0; i < pctl->desc->npins; i++) { 693 for (i = 0; i < pctl->desc->npins; i++) {
693 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 694 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
694 struct sunxi_desc_function *func = pin->functions; 695 struct sunxi_desc_function *func = pin->functions;
695 696
696 while (func->name) { 697 while (func->name) {
697 sunxi_pinctrl_add_function(pctl, func->name); 698 sunxi_pinctrl_add_function(pctl, func->name);
698 func++; 699 func++;
699 } 700 }
700 } 701 }
701 702
702 pctl->functions = krealloc(pctl->functions, 703 pctl->functions = krealloc(pctl->functions,
703 pctl->nfunctions * sizeof(*pctl->functions), 704 pctl->nfunctions * sizeof(*pctl->functions),
704 GFP_KERNEL); 705 GFP_KERNEL);
705 706
706 for (i = 0; i < pctl->desc->npins; i++) { 707 for (i = 0; i < pctl->desc->npins; i++) {
707 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 708 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
708 struct sunxi_desc_function *func = pin->functions; 709 struct sunxi_desc_function *func = pin->functions;
709 710
710 while (func->name) { 711 while (func->name) {
711 struct sunxi_pinctrl_function *func_item; 712 struct sunxi_pinctrl_function *func_item;
712 const char **func_grp; 713 const char **func_grp;
713 714
714 func_item = sunxi_pinctrl_find_function_by_name(pctl, 715 func_item = sunxi_pinctrl_find_function_by_name(pctl,
715 func->name); 716 func->name);
716 if (!func_item) 717 if (!func_item)
717 return -EINVAL; 718 return -EINVAL;
718 719
719 if (!func_item->groups) { 720 if (!func_item->groups) {
720 func_item->groups = 721 func_item->groups =
721 devm_kzalloc(&pdev->dev, 722 devm_kzalloc(&pdev->dev,
722 func_item->ngroups * sizeof(*func_item->groups), 723 func_item->ngroups * sizeof(*func_item->groups),
723 GFP_KERNEL); 724 GFP_KERNEL);
724 if (!func_item->groups) 725 if (!func_item->groups)
725 return -ENOMEM; 726 return -ENOMEM;
726 } 727 }
727 728
728 func_grp = func_item->groups; 729 func_grp = func_item->groups;
729 while (*func_grp) 730 while (*func_grp)
730 func_grp++; 731 func_grp++;
731 732
732 *func_grp = pin->pin.name; 733 *func_grp = pin->pin.name;
733 func++; 734 func++;
734 } 735 }
735 } 736 }
736 737
737 return 0; 738 return 0;
738 } 739 }
739 740
740 static int sunxi_pinctrl_probe(struct platform_device *pdev) 741 static int sunxi_pinctrl_probe(struct platform_device *pdev)
741 { 742 {
742 struct device_node *node = pdev->dev.of_node; 743 struct device_node *node = pdev->dev.of_node;
743 const struct of_device_id *device; 744 const struct of_device_id *device;
744 struct pinctrl_pin_desc *pins; 745 struct pinctrl_pin_desc *pins;
745 struct sunxi_pinctrl *pctl; 746 struct sunxi_pinctrl *pctl;
746 int i, ret, last_pin; 747 int i, ret, last_pin;
747 struct clk *clk; 748 struct clk *clk;
748 749
749 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 750 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
750 if (!pctl) 751 if (!pctl)
751 return -ENOMEM; 752 return -ENOMEM;
752 platform_set_drvdata(pdev, pctl); 753 platform_set_drvdata(pdev, pctl);
753 754
754 pctl->membase = of_iomap(node, 0); 755 pctl->membase = of_iomap(node, 0);
755 if (!pctl->membase) 756 if (!pctl->membase)
756 return -ENOMEM; 757 return -ENOMEM;
757 758
758 device = of_match_device(sunxi_pinctrl_match, &pdev->dev); 759 device = of_match_device(sunxi_pinctrl_match, &pdev->dev);
759 if (!device) 760 if (!device)
760 return -ENODEV; 761 return -ENODEV;
761 762
762 pctl->desc = (struct sunxi_pinctrl_desc *)device->data; 763 pctl->desc = (struct sunxi_pinctrl_desc *)device->data;
763 764
764 ret = sunxi_pinctrl_build_state(pdev); 765 ret = sunxi_pinctrl_build_state(pdev);
765 if (ret) { 766 if (ret) {
766 dev_err(&pdev->dev, "dt probe failed: %d\n", ret); 767 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
767 return ret; 768 return ret;
768 } 769 }
769 770
770 pins = devm_kzalloc(&pdev->dev, 771 pins = devm_kzalloc(&pdev->dev,
771 pctl->desc->npins * sizeof(*pins), 772 pctl->desc->npins * sizeof(*pins),
772 GFP_KERNEL); 773 GFP_KERNEL);
773 if (!pins) 774 if (!pins)
774 return -ENOMEM; 775 return -ENOMEM;
775 776
776 for (i = 0; i < pctl->desc->npins; i++) 777 for (i = 0; i < pctl->desc->npins; i++)
777 pins[i] = pctl->desc->pins[i].pin; 778 pins[i] = pctl->desc->pins[i].pin;
778 779
779 sunxi_pctrl_desc.name = dev_name(&pdev->dev); 780 sunxi_pctrl_desc.name = dev_name(&pdev->dev);
780 sunxi_pctrl_desc.owner = THIS_MODULE; 781 sunxi_pctrl_desc.owner = THIS_MODULE;
781 sunxi_pctrl_desc.pins = pins; 782 sunxi_pctrl_desc.pins = pins;
782 sunxi_pctrl_desc.npins = pctl->desc->npins; 783 sunxi_pctrl_desc.npins = pctl->desc->npins;
783 pctl->dev = &pdev->dev; 784 pctl->dev = &pdev->dev;
784 pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc, 785 pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc,
785 &pdev->dev, pctl); 786 &pdev->dev, pctl);
786 if (!pctl->pctl_dev) { 787 if (!pctl->pctl_dev) {
787 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 788 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
788 return -EINVAL; 789 return -EINVAL;
789 } 790 }
790 791
791 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 792 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
792 if (!pctl->chip) { 793 if (!pctl->chip) {
793 ret = -ENOMEM; 794 ret = -ENOMEM;
794 goto pinctrl_error; 795 goto pinctrl_error;
795 } 796 }
796 797
797 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; 798 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
798 pctl->chip = &sunxi_pinctrl_gpio_chip; 799 pctl->chip = &sunxi_pinctrl_gpio_chip;
799 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK); 800 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK);
800 pctl->chip->label = dev_name(&pdev->dev); 801 pctl->chip->label = dev_name(&pdev->dev);
801 pctl->chip->dev = &pdev->dev; 802 pctl->chip->dev = &pdev->dev;
802 pctl->chip->base = 0; 803 pctl->chip->base = 0;
803 804
804 ret = gpiochip_add(pctl->chip); 805 ret = gpiochip_add(pctl->chip);
805 if (ret) 806 if (ret)
806 goto pinctrl_error; 807 goto pinctrl_error;
807 808
808 for (i = 0; i < pctl->desc->npins; i++) { 809 for (i = 0; i < pctl->desc->npins; i++) {
809 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 810 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
810 811
811 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 812 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
812 pin->pin.number, 813 pin->pin.number,
813 pin->pin.number, 1); 814 pin->pin.number, 1);
814 if (ret) 815 if (ret)
815 goto gpiochip_error; 816 goto gpiochip_error;
816 } 817 }
817 818
818 clk = devm_clk_get(&pdev->dev, NULL); 819 clk = devm_clk_get(&pdev->dev, NULL);
819 if (IS_ERR(clk)) { 820 if (IS_ERR(clk)) {
820 ret = PTR_ERR(clk); 821 ret = PTR_ERR(clk);
821 goto gpiochip_error; 822 goto gpiochip_error;
822 } 823 }
823 824
824 clk_prepare_enable(clk); 825 clk_prepare_enable(clk);
825 826
826 pctl->irq = irq_of_parse_and_map(node, 0); 827 pctl->irq = irq_of_parse_and_map(node, 0);
827 if (!pctl->irq) { 828 if (!pctl->irq) {
828 ret = -EINVAL; 829 ret = -EINVAL;
829 goto gpiochip_error; 830 goto gpiochip_error;
830 } 831 }
831 832
832 pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER, 833 pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER,
833 &irq_domain_simple_ops, NULL); 834 &irq_domain_simple_ops, NULL);
834 if (!pctl->domain) { 835 if (!pctl->domain) {
835 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 836 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
836 ret = -ENOMEM; 837 ret = -ENOMEM;
837 goto gpiochip_error; 838 goto gpiochip_error;
838 } 839 }
839 840
840 for (i = 0; i < SUNXI_IRQ_NUMBER; i++) { 841 for (i = 0; i < SUNXI_IRQ_NUMBER; i++) {
841 int irqno = irq_create_mapping(pctl->domain, i); 842 int irqno = irq_create_mapping(pctl->domain, i);
842 843
843 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip, 844 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip,
844 handle_simple_irq); 845 handle_simple_irq);
845 irq_set_chip_data(irqno, pctl); 846 irq_set_chip_data(irqno, pctl);
846 }; 847 };
847 848
848 irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler); 849 irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler);
849 irq_set_handler_data(pctl->irq, pctl); 850 irq_set_handler_data(pctl->irq, pctl);
850 851
851 dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); 852 dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
852 853
853 return 0; 854 return 0;
854 855
855 gpiochip_error: 856 gpiochip_error:
856 if (gpiochip_remove(pctl->chip)) 857 if (gpiochip_remove(pctl->chip))
857 dev_err(&pdev->dev, "failed to remove gpio chip\n"); 858 dev_err(&pdev->dev, "failed to remove gpio chip\n");
858 pinctrl_error: 859 pinctrl_error:
859 pinctrl_unregister(pctl->pctl_dev); 860 pinctrl_unregister(pctl->pctl_dev);
860 return ret; 861 return ret;
861 } 862 }
862 863
863 static struct platform_driver sunxi_pinctrl_driver = { 864 static struct platform_driver sunxi_pinctrl_driver = {
864 .probe = sunxi_pinctrl_probe, 865 .probe = sunxi_pinctrl_probe,
865 .driver = { 866 .driver = {
866 .name = "sunxi-pinctrl", 867 .name = "sunxi-pinctrl",
867 .owner = THIS_MODULE, 868 .owner = THIS_MODULE,
868 .of_match_table = sunxi_pinctrl_match, 869 .of_match_table = sunxi_pinctrl_match,
869 }, 870 },
870 }; 871 };
871 module_platform_driver(sunxi_pinctrl_driver); 872 module_platform_driver(sunxi_pinctrl_driver);
872 873
873 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com"); 874 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
874 MODULE_DESCRIPTION("Allwinner A1X pinctrl driver"); 875 MODULE_DESCRIPTION("Allwinner A1X pinctrl driver");
875 MODULE_LICENSE("GPL"); 876 MODULE_LICENSE("GPL");
876 877