Doug / smarc-fsl-linux-kernel

Download as
Browse Code ยป

Commit ac68936652819dad1e5decefddb1c7fc1d7bc364

Authored by Maxime Ripard
Committed by Linus Walleij
1 parent 44abb933f7
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

pinctrl: sunxi: Add Allwinner A10s pins 

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Showing 2 changed files with 646 additions and 0 deletions Side-by-side Diff

drivers/pinctrl/pinctrl-sunxi-pins.h
Diff comments   View file @ ac68936
... ... @@ -1004,6 +1004,646 @@
1004 1004 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
1005 1005 };
1006 1006  
  1007 +static const struct sunxi_desc_pin sun5i_a10s_pins[] = {
  1008 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
  1009 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1010 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1011 + SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
  1012 + SUNXI_FUNCTION(0x3, "ts0"), /* CLK */
  1013 + SUNXI_FUNCTION(0x5, "keypad")), /* IN0 */
  1014 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
  1015 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1016 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1017 + SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
  1018 + SUNXI_FUNCTION(0x3, "ts0"), /* ERR */
  1019 + SUNXI_FUNCTION(0x5, "keypad")), /* IN1 */
  1020 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
  1021 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1022 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1023 + SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
  1024 + SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */
  1025 + SUNXI_FUNCTION(0x5, "keypad")), /* IN2 */
  1026 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
  1027 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1028 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1029 + SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
  1030 + SUNXI_FUNCTION(0x3, "ts0"), /* DLVD */
  1031 + SUNXI_FUNCTION(0x5, "keypad")), /* IN3 */
  1032 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
  1033 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1034 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1035 + SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
  1036 + SUNXI_FUNCTION(0x3, "ts0"), /* D0 */
  1037 + SUNXI_FUNCTION(0x5, "keypad")), /* IN4 */
  1038 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
  1039 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1040 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1041 + SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
  1042 + SUNXI_FUNCTION(0x3, "ts0"), /* D1 */
  1043 + SUNXI_FUNCTION(0x5, "keypad")), /* IN5 */
  1044 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
  1045 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1046 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1047 + SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
  1048 + SUNXI_FUNCTION(0x3, "ts0"), /* D2 */
  1049 + SUNXI_FUNCTION(0x5, "keypad")), /* IN6 */
  1050 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
  1051 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1052 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1053 + SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
  1054 + SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
  1055 + SUNXI_FUNCTION(0x5, "keypad")), /* IN7 */
  1056 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
  1057 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1058 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1059 + SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
  1060 + SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
  1061 + SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
  1062 + SUNXI_FUNCTION(0x5, "keypad")), /* OUT0 */
  1063 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
  1064 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1065 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1066 + SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
  1067 + SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
  1068 + SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
  1069 + SUNXI_FUNCTION(0x5, "keypad")), /* OUT1 */
  1070 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
  1071 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1072 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1073 + SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
  1074 + SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
  1075 + SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
  1076 + SUNXI_FUNCTION(0x5, "keypad")), /* OUT2 */
  1077 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
  1078 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1079 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1080 + SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
  1081 + SUNXI_FUNCTION(0x3, "ts0"), /* D7 */
  1082 + SUNXI_FUNCTION(0x4, "uart1"), /* RING */
  1083 + SUNXI_FUNCTION(0x5, "keypad")), /* OUT3 */
  1084 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
  1085 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1086 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1087 + SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
  1088 + SUNXI_FUNCTION(0x3, "uart1"), /* TX */
  1089 + SUNXI_FUNCTION(0x5, "keypad")), /* OUT4 */
  1090 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
  1091 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1092 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1093 + SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
  1094 + SUNXI_FUNCTION(0x3, "uart1"), /* RX */
  1095 + SUNXI_FUNCTION(0x5, "keypad")), /* OUT5 */
  1096 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
  1097 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1098 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1099 + SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
  1100 + SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
  1101 + SUNXI_FUNCTION(0x4, "uart3"), /* TX */
  1102 + SUNXI_FUNCTION(0x5, "keypad")), /* OUT6 */
  1103 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
  1104 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1105 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1106 + SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
  1107 + SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
  1108 + SUNXI_FUNCTION(0x4, "uart3"), /* RX */
  1109 + SUNXI_FUNCTION(0x5, "keypad")), /* OUT7 */
  1110 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
  1111 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1112 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1113 + SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
  1114 + SUNXI_FUNCTION(0x3, "uart2")), /* TX */
  1115 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
  1116 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1117 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1118 + SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
  1119 + SUNXI_FUNCTION(0x3, "uart2"), /* RX */
  1120 + SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
  1121 + /* Hole */
  1122 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
  1123 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1124 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1125 + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
  1126 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
  1127 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1128 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1129 + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
  1130 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
  1131 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1132 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1133 + SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
  1134 + SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
  1135 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
  1136 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1137 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1138 + SUNXI_FUNCTION(0x2, "ir0"), /* TX */
  1139 + SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
  1140 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
  1141 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1142 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1143 + SUNXI_FUNCTION(0x2, "ir0"), /* RX */
  1144 + SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
  1145 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
  1146 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1147 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1148 + SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
  1149 + SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */
  1150 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
  1151 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1152 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1153 + SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
  1154 + SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */
  1155 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
  1156 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1157 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1158 + SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
  1159 + SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */
  1160 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
  1161 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1162 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1163 + SUNXI_FUNCTION(0x2, "i2s"), /* DO */
  1164 + SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
  1165 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
  1166 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1167 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1168 + SUNXI_FUNCTION(0x2, "i2s"), /* DI */
  1169 + SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
  1170 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
  1171 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1172 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1173 + SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
  1174 + SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
  1175 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
  1176 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1177 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1178 + SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
  1179 + SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
  1180 + SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
  1181 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
  1182 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1183 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1184 + SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
  1185 + SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
  1186 + SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
  1187 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
  1188 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1189 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1190 + SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
  1191 + SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
  1192 + SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
  1193 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
  1194 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1195 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1196 + SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
  1197 + SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
  1198 + SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
  1199 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
  1200 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1201 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1202 + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
  1203 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
  1204 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1205 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1206 + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
  1207 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
  1208 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1209 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1210 + SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
  1211 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
  1212 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1213 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1214 + SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
  1215 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
  1216 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1217 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1218 + SUNXI_FUNCTION(0x2, "uart0"), /* TX */
  1219 + SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
  1220 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
  1221 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1222 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1223 + SUNXI_FUNCTION(0x2, "uart0"), /* RX */
  1224 + SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
  1225 + /* Hole */
  1226 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
  1227 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1228 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1229 + SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
  1230 + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
  1231 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
  1232 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1233 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1234 + SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
  1235 + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
  1236 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
  1237 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1238 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1239 + SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
  1240 + SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
  1241 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
  1242 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1243 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1244 + SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
  1245 + SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
  1246 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
  1247 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1248 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1249 + SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
  1250 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
  1251 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1252 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1253 + SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
  1254 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
  1255 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1256 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1257 + SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
  1258 + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
  1259 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
  1260 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1261 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1262 + SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
  1263 + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
  1264 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
  1265 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1266 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1267 + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
  1268 + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
  1269 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
  1270 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1271 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1272 + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
  1273 + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
  1274 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
  1275 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1276 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1277 + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
  1278 + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
  1279 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
  1280 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1281 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1282 + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
  1283 + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
  1284 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
  1285 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1286 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1287 + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
  1288 + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
  1289 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
  1290 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1291 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1292 + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
  1293 + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
  1294 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
  1295 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1296 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1297 + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
  1298 + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
  1299 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
  1300 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1301 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1302 + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
  1303 + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
  1304 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
  1305 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1306 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1307 + SUNXI_FUNCTION(0x2, "nand0"), /* NWP */
  1308 + SUNXI_FUNCTION(0x4, "uart3")), /* TX */
  1309 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
  1310 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1311 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1312 + SUNXI_FUNCTION(0x2, "nand0"), /* NCE2 */
  1313 + SUNXI_FUNCTION(0x4, "uart3")), /* RX */
  1314 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
  1315 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1316 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1317 + SUNXI_FUNCTION(0x2, "nand0"), /* NCE3 */
  1318 + SUNXI_FUNCTION(0x3, "uart2"), /* TX */
  1319 + SUNXI_FUNCTION(0x4, "uart3")), /* CTS */
  1320 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
  1321 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1322 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1323 + SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
  1324 + SUNXI_FUNCTION(0x3, "uart2"), /* RX */
  1325 + SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
  1326 + /* Hole */
  1327 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
  1328 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1329 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1330 + SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */
  1331 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
  1332 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1333 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1334 + SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */
  1335 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
  1336 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1337 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1338 + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
  1339 + SUNXI_FUNCTION(0x3, "uart2")), /* TX */
  1340 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
  1341 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1342 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1343 + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
  1344 + SUNXI_FUNCTION(0x3, "uart2")), /* RX */
  1345 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
  1346 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1347 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1348 + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
  1349 + SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
  1350 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
  1351 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1352 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1353 + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
  1354 + SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
  1355 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
  1356 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1357 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1358 + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
  1359 + SUNXI_FUNCTION(0x3, "emac")), /* ECRS */
  1360 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
  1361 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1362 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1363 + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
  1364 + SUNXI_FUNCTION(0x3, "emac")), /* ECOL */
  1365 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
  1366 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1367 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1368 + SUNXI_FUNCTION(0x2, "lcd0")), /* D8 */
  1369 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
  1370 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1371 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1372 + SUNXI_FUNCTION(0x2, "lcd0")), /* D9 */
  1373 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
  1374 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1375 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1376 + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
  1377 + SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */
  1378 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
  1379 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1380 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1381 + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
  1382 + SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */
  1383 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
  1384 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1385 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1386 + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
  1387 + SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */
  1388 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
  1389 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1390 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1391 + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
  1392 + SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */
  1393 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
  1394 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1395 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1396 + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
  1397 + SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */
  1398 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
  1399 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1400 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1401 + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
  1402 + SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */
  1403 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
  1404 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1405 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1406 + SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
  1407 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
  1408 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1409 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1410 + SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
  1411 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
  1412 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1413 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1414 + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
  1415 + SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */
  1416 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
  1417 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1418 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1419 + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
  1420 + SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */
  1421 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
  1422 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1423 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1424 + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
  1425 + SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */
  1426 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
  1427 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1428 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1429 + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
  1430 + SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */
  1431 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
  1432 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1433 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1434 + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
  1435 + SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */
  1436 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
  1437 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1438 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1439 + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
  1440 + SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */
  1441 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
  1442 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1443 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1444 + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
  1445 + SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */
  1446 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
  1447 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1448 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1449 + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
  1450 + SUNXI_FUNCTION(0x3, "emac")), /* ETXERR */
  1451 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
  1452 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1453 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1454 + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
  1455 + SUNXI_FUNCTION(0x3, "emac")), /* EMDC */
  1456 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
  1457 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1458 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1459 + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
  1460 + SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */
  1461 + /* Hole */
  1462 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
  1463 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1464 + SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
  1465 + SUNXI_FUNCTION(0x3, "csi0"), /* PCK */
  1466 + SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
  1467 + SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
  1468 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
  1469 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1470 + SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
  1471 + SUNXI_FUNCTION(0x3, "csi0"), /* CK */
  1472 + SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
  1473 + SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
  1474 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
  1475 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1476 + SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
  1477 + SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
  1478 + SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
  1479 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
  1480 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1481 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1482 + SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
  1483 + SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
  1484 + SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
  1485 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
  1486 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1487 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1488 + SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
  1489 + SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
  1490 + SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
  1491 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
  1492 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1493 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1494 + SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
  1495 + SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
  1496 + SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
  1497 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
  1498 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1499 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1500 + SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
  1501 + SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
  1502 + SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
  1503 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
  1504 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1505 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1506 + SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
  1507 + SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
  1508 + SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
  1509 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
  1510 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1511 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1512 + SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
  1513 + SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
  1514 + SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
  1515 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
  1516 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1517 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1518 + SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
  1519 + SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
  1520 + SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
  1521 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
  1522 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1523 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1524 + SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
  1525 + SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
  1526 + SUNXI_FUNCTION(0x4, "uart1")), /* TX */
  1527 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
  1528 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1529 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1530 + SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
  1531 + SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
  1532 + SUNXI_FUNCTION(0x4, "uart1")), /* RX */
  1533 + /* Hole */
  1534 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
  1535 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1536 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1537 + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
  1538 + SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
  1539 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
  1540 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1541 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1542 + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
  1543 + SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
  1544 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
  1545 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1546 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1547 + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
  1548 + SUNXI_FUNCTION(0x4, "uart0")), /* TX */
  1549 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
  1550 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1551 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1552 + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
  1553 + SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
  1554 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
  1555 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1556 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1557 + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
  1558 + SUNXI_FUNCTION(0x4, "uart0")), /* RX */
  1559 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
  1560 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1561 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1562 + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
  1563 + SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
  1564 + /* Hole */
  1565 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
  1566 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1567 + SUNXI_FUNCTION(0x2, "gps"), /* CLK */
  1568 + SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
  1569 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
  1570 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1571 + SUNXI_FUNCTION(0x2, "gps"), /* SIGN */
  1572 + SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
  1573 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
  1574 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1575 + SUNXI_FUNCTION(0x2, "gps"), /* MAG */
  1576 + SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
  1577 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
  1578 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1579 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1580 + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
  1581 + SUNXI_FUNCTION(0x4, "uart1"), /* TX */
  1582 + SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
  1583 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
  1584 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1585 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1586 + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
  1587 + SUNXI_FUNCTION(0x4, "uart1"), /* RX */
  1588 + SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
  1589 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
  1590 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1591 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1592 + SUNXI_FUNCTION(0x2, "mmc1"), /* DO */
  1593 + SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
  1594 + SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */
  1595 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
  1596 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1597 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1598 + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
  1599 + SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
  1600 + SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
  1601 + SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */
  1602 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
  1603 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1604 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1605 + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
  1606 + SUNXI_FUNCTION(0x5, "uart2"), /* TX */
  1607 + SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */
  1608 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
  1609 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1610 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1611 + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
  1612 + SUNXI_FUNCTION(0x5, "uart2"), /* RX */
  1613 + SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */
  1614 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
  1615 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1616 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1617 + SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
  1618 + SUNXI_FUNCTION(0x3, "uart3"), /* TX */
  1619 + SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
  1620 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
  1621 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1622 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1623 + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
  1624 + SUNXI_FUNCTION(0x3, "uart3"), /* RX */
  1625 + SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
  1626 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
  1627 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1628 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1629 + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
  1630 + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
  1631 + SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
  1632 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
  1633 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1634 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1635 + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
  1636 + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
  1637 + SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
  1638 + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG13,
  1639 + SUNXI_FUNCTION(0x0, "gpio_in"),
  1640 + SUNXI_FUNCTION(0x1, "gpio_out"),
  1641 + SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
  1642 + SUNXI_FUNCTION(0x3, "uart3"), /* PWM1 */
  1643 + SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
  1644 + SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
  1645 +};
  1646 +
1007 1647 static const struct sunxi_desc_pin sun5i_a13_pins[] = {
1008 1648 /* Hole */
1009 1649 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
... ... @@ -1368,6 +2008,11 @@
1368 2008 static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
1369 2009 .pins = sun4i_a10_pins,
1370 2010 .npins = ARRAY_SIZE(sun4i_a10_pins),
  2011 +};
  2012 +
  2013 +static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = {
  2014 + .pins = sun5i_a10s_pins,
  2015 + .npins = ARRAY_SIZE(sun5i_a10s_pins),
1371 2016 };
1372 2017  
1373 2018 static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
drivers/pinctrl/pinctrl-sunxi.c
Diff comments   View file @ ac68936
... ... @@ -629,6 +629,7 @@
629 629  
630 630 static struct of_device_id sunxi_pinctrl_match[] = {
631 631 { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data },
  632 + { .compatible = "allwinner,sun5i-a10s-pinctrl", .data = (void *)&sun5i_a10s_pinctrl_data },
632 633 { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
633 634 {}
634 635 };