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Commit adb3789264c4e8567113a0e764ad30ce6e8737f3

Authored by Deng-Cheng Zhu
Committed by Ralf Baechle
1 parent ed1197f931
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

MIPS: Fix ISA level which causes secondary cache init bypassing and more 

The commit a96102be70 introduced set_isa() where compatible ISA info is
also set aside from the one gets passed in. It means, for example, 1004K
will have MIPS_CPU_ISA_M32R2/M32R1/II/I flags. This leads to things like
the following inappropriate:

if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
    c->isa_level == MIPS_CPU_ISA_M32R2 ||
    c->isa_level == MIPS_CPU_ISA_M64R1 ||
    c->isa_level == MIPS_CPU_ISA_M64R2)

This patch fixes it.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Showing 4 changed files with 7 additions and 13 deletions Side-by-side Diff

arch/mips/kernel/cpu-probe.c
Diff comments   View file @ adb3789
... ... @@ -1226,10 +1226,8 @@
1226 1226 if (c->options & MIPS_CPU_FPU) {
1227 1227 c->fpu_id = cpu_get_fpu_id();
1228 1228  
1229   - if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1230   - c->isa_level == MIPS_CPU_ISA_M32R2 ||
1231   - c->isa_level == MIPS_CPU_ISA_M64R1 ||
1232   - c->isa_level == MIPS_CPU_ISA_M64R2) {
  1229 + if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
  1230 + MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1233 1231 if (c->fpu_id & MIPS_FPIR_3D)
1234 1232 c->ases |= MIPS_ASE_MIPS3D;
1235 1233 }
arch/mips/kernel/traps.c
Diff comments   View file @ adb3789
... ... @@ -1571,7 +1571,7 @@
1571 1571 #ifdef CONFIG_64BIT
1572 1572 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1573 1573 #endif
1574   - if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
  1574 + if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
1575 1575 status_set |= ST0_XX;
1576 1576 if (cpu_has_dsp)
1577 1577 status_set |= ST0_MX;
arch/mips/mm/c-r4k.c
Diff comments   View file @ adb3789
... ... @@ -1247,10 +1247,8 @@
1247 1247 return;
1248 1248  
1249 1249 default:
1250   - if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1251   - c->isa_level == MIPS_CPU_ISA_M32R2 ||
1252   - c->isa_level == MIPS_CPU_ISA_M64R1 ||
1253   - c->isa_level == MIPS_CPU_ISA_M64R2) {
  1250 + if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
  1251 + MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1254 1252 #ifdef CONFIG_MIPS_CPU_SCACHE
1255 1253 if (mips_sc_init ()) {
1256 1254 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
arch/mips/mm/sc-mips.c
Diff comments   View file @ adb3789
... ... @@ -98,10 +98,8 @@
98 98 c->scache.flags |= MIPS_CACHE_NOT_PRESENT;
99 99  
100 100 /* Ignore anything but MIPSxx processors */
101   - if (c->isa_level != MIPS_CPU_ISA_M32R1 &&
102   - c->isa_level != MIPS_CPU_ISA_M32R2 &&
103   - c->isa_level != MIPS_CPU_ISA_M64R1 &&
104   - c->isa_level != MIPS_CPU_ISA_M64R2)
  101 + if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
  102 + MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)))
105 103 return 0;
106 104  
107 105 /* Does this MIPS32/MIPS64 CPU have a config2 register? */