powerpc/8xx: mfspr SPRN_TBRx in lieu of mftb/mftbu is not supported

Commit beb2dc0a7a84be003ce54e98b95d65cc66e6e536 breaks the MPC8xx which seems to not support using mfspr SPRN_TBRx instead of mftb/mftbu despite what is written in the reference manual. This patch reverts to the use of mftb/mftbu when CONFIG_8xx is selected. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>

powerpc/8xx: mfspr SPRN_TBRx in lieu of mftb/mftbu is not supported
Commit beb2dc0a7a84be003ce54e98b95d65cc66e6e536 breaks the MPC8xx which seems to not support using mfspr SPRN_TBRx instead of mftb/mftbu despite what is written in the reference manual. This patch reverts to the use of mftb/mftbu when CONFIG_8xx is selected. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
LEROY Christophe · Scott Wood
1 parent cbf8a358be
Showing 5 changed files with 37 additions and 0 deletions Side-by-side Diff
arch/powerpc/boot/util.S
arch/powerpc/include/asm/ppc_asm.h
arch/powerpc/include/asm/reg.h
arch/powerpc/include/asm/timex.h
arch/powerpc/kernel/vdso32/gettimeofday.S
@@ -71,18 +71,32 @@
 	add	r4,r4,r5
 	addi	r4,r4,-1
 	divw	r4,r4,r5	/* BUS ticks */
+#ifdef CONFIG_8xx
+1:	mftbu	r5
+	mftb	r6
+	mftbu	r7
+#else
 1:	mfspr	r5, SPRN_TBRU
 	mfspr	r6, SPRN_TBRL
 	mfspr	r7, SPRN_TBRU
+#endif
 	cmpw	0,r5,r7
 	bne	1b		/* Get [synced] base time */
 	addc	r9,r6,r4	/* Compute end time */
 	addze	r8,r5
+#ifdef CONFIG_8xx
+2:	mftbu	r5
+#else
 2:	mfspr	r5, SPRN_TBRU
+#endif
 	cmpw	0,r5,r8
 	blt	2b
 	bgt	3f
+#ifdef CONFIG_8xx
+	mftb	r6
+#else
 	mfspr	r6, SPRN_TBRL
+#endif
 	cmpw	0,r6,r9
 	blt	2b
 3:	blr
@@ -366,6 +366,8 @@
 	cmpwi dest,0;			\
 	beq-  90b;			\
 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
+#elif defined(CONFIG_8xx)
+#define MFTB(dest)			mftb dest
 #else
 #define MFTB(dest)			mfspr dest, SPRN_TBRL
 #endif
@@ -1174,12 +1174,19 @@
  
 #else /* __powerpc64__ */
  
+#if defined(CONFIG_8xx)
 #define mftbl()		({unsigned long rval;	\
+			asm volatile("mftbl %0" : "=r" (rval)); rval;})
+#define mftbu()		({unsigned long rval;	\
+			asm volatile("mftbu %0" : "=r" (rval)); rval;})
+#else
+#define mftbl()		({unsigned long rval;	\
 			asm volatile("mfspr %0, %1" : "=r" (rval) : \
 				"i" (SPRN_TBRL)); rval;})
 #define mftbu()		({unsigned long rval;	\
 			asm volatile("mfspr %0, %1" : "=r" (rval) : \
 				"i" (SPRN_TBRU)); rval;})
+#endif
 #endif /* !__powerpc64__ */
  
 #define mttbl(v)	asm volatile("mttbl %0":: "r"(v))
@@ -29,7 +29,11 @@
 	ret = 0;
  
 	__asm__ __volatile__(
+#ifdef CONFIG_8xx
+		"97:	mftb %0\n"
+#else
 		"97:	mfspr %0, %2\n"
+#endif
 		"99:\n"
 		".section __ftr_fixup,\"a\"\n"
 		".align 2\n"
  
@@ -41,7 +45,11 @@
 		"	.long 0\n"
 		"	.long 0\n"
 		".previous"
+#ifdef CONFIG_8xx
+		: "=r" (ret) : "i" (CPU_FTR_601));
+#else
 		: "=r" (ret) : "i" (CPU_FTR_601), "i" (SPRN_TBRL));
+#endif
 	return ret;
 #endif
 }
@@ -232,9 +232,15 @@
 	lwz	r6,(CFG_TB_ORIG_STAMP+4)(r9)
  
 	/* Get a stable TB value */
+#ifdef CONFIG_8xx
+2:	mftbu	r3
+	mftbl	r4
+	mftbu	r0
+#else
 2:	mfspr	r3, SPRN_TBRU
 	mfspr	r4, SPRN_TBRL
 	mfspr	r0, SPRN_TBRU
+#endif
 	cmplw	cr0,r3,r0
 	bne-	2b
...	...	@@ -71,18 +71,32 @@
71	71	add r4,r4,r5
72	72	addi r4,r4,-1
73	73	divw r4,r4,r5 /* BUS ticks */
	74	+#ifdef CONFIG_8xx
	75	+1: mftbu r5
	76	+ mftb r6
	77	+ mftbu r7
	78	+#else
74	79	1: mfspr r5, SPRN_TBRU
75	80	mfspr r6, SPRN_TBRL
76	81	mfspr r7, SPRN_TBRU
	82	+#endif
77	83	cmpw 0,r5,r7
78	84	bne 1b /* Get [synced] base time */
79	85	addc r9,r6,r4 /* Compute end time */
80	86	addze r8,r5
	87	+#ifdef CONFIG_8xx
	88	+2: mftbu r5
	89	+#else
81	90	2: mfspr r5, SPRN_TBRU
	91	+#endif
82	92	cmpw 0,r5,r8
83	93	blt 2b
84	94	bgt 3f
	95	+#ifdef CONFIG_8xx
	96	+ mftb r6
	97	+#else
85	98	mfspr r6, SPRN_TBRL
	99	+#endif
86	100	cmpw 0,r6,r9
87	101	blt 2b
88	102	3: blr
...	...	@@ -366,6 +366,8 @@
366	366	cmpwi dest,0; \
367	367	beq- 90b; \
368	368	END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
	369	+#elif defined(CONFIG_8xx)
	370	+#define MFTB(dest) mftb dest
369	371	#else
370	372	#define MFTB(dest) mfspr dest, SPRN_TBRL
371	373	#endif
...	...	@@ -1174,12 +1174,19 @@
1174	1174
1175	1175	#else /* __powerpc64__ */
1176	1176
	1177	+#if defined(CONFIG_8xx)
1177	1178	#define mftbl() ({unsigned long rval; \
	1179	+ asm volatile("mftbl %0" : "=r" (rval)); rval;})
	1180	+#define mftbu() ({unsigned long rval; \
	1181	+ asm volatile("mftbu %0" : "=r" (rval)); rval;})
	1182	+#else
	1183	+#define mftbl() ({unsigned long rval; \
1178	1184	asm volatile("mfspr %0, %1" : "=r" (rval) : \
1179	1185	"i" (SPRN_TBRL)); rval;})
1180	1186	#define mftbu() ({unsigned long rval; \
1181	1187	asm volatile("mfspr %0, %1" : "=r" (rval) : \
1182	1188	"i" (SPRN_TBRU)); rval;})
	1189	+#endif
1183	1190	#endif /* !__powerpc64__ */
1184	1191
1185	1192	#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
...	...	@@ -29,7 +29,11 @@
29	29	ret = 0;
30	30
31	31	__asm__ __volatile__(
	32	+#ifdef CONFIG_8xx
	33	+ "97: mftb %0\n"
	34	+#else
32	35	"97: mfspr %0, %2\n"
	36	+#endif
33	37	"99:\n"
34	38	".section __ftr_fixup,\"a\"\n"
35	39	".align 2\n"
36	40
...	...	@@ -41,7 +45,11 @@
41	45	" .long 0\n"
42	46	" .long 0\n"
43	47	".previous"
	48	+#ifdef CONFIG_8xx
	49	+ : "=r" (ret) : "i" (CPU_FTR_601));
	50	+#else
44	51	: "=r" (ret) : "i" (CPU_FTR_601), "i" (SPRN_TBRL));
	52	+#endif
45	53	return ret;
46	54	#endif
47	55	}
...	...	@@ -232,9 +232,15 @@
232	232	lwz r6,(CFG_TB_ORIG_STAMP+4)(r9)
233	233
234	234	/* Get a stable TB value */
	235	+#ifdef CONFIG_8xx
	236	+2: mftbu r3
	237	+ mftbl r4
	238	+ mftbu r0
	239	+#else
235	240	2: mfspr r3, SPRN_TBRU
236	241	mfspr r4, SPRN_TBRL
237	242	mfspr r0, SPRN_TBRU
	243	+#endif
238	244	cmplw cr0,r3,r0
239	245	bne- 2b
240	246