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Commit aea686b47c0cf97e0c6941799b523b6df87fc234

Authored by Vipin Kumar
Committed by David Woodhouse
1 parent 4cbe1bf07a
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

mtd: nand/fsmc: Read only 512 + 13 bytes for 8bit NAND devices 

The ECC logic of FSMC works on 512 bytes data + 13 bytes ECC to generate error
indices of up to 8 incorrect bits. The FSMC driver reads 14 instead of 13 oob
bytes to accommodate for 16 bit device as well.

Unfortunately, the internal ecc state machine gets corrupted for 8 bit devices
reading 512 + 14 bytes of data resulting in error indices not getting reported.

Fix this by reading 14 bytes only for 16 bit devices

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>

Showing 1 changed file with 3 additions and 1 deletions Side-by-side Diff

drivers/mtd/nand/fsmc_nand.c
Diff comments   View file @ aea686b
... ... @@ -549,7 +549,9 @@
549 549 * to read at least 13 bytes even in case of 16 bit NAND
550 550 * devices
551 551 */
552   - len = roundup(len, 2);
  552 + if (chip->options & NAND_BUSWIDTH_16)
  553 + len = roundup(len, 2);
  554 +
553 555 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
554 556 chip->read_buf(mtd, oob + j, len);
555 557 j += len;