ARM: davinci: dm644x: add support for v4l2 video display

Add functions to register various video devices like venc, osd, vpbe and the v4l2 display driver for dm644x. Change dm644x_init_video() to make room for display related configuration. Register the vpfe or vpbe devices only if valid display configuration is provided to make sure boards without video support dont erroneously register video devices. Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>

ARM: davinci: dm644x: add support for v4l2 video display
Add functions to register various video devices like venc, osd, vpbe and the v4l2 display driver for dm644x. Change dm644x_init_video() to make room for display related configuration. Register the vpfe or vpbe devices only if valid display configuration is provided to make sure boards without video support dont erroneously register video devices. Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Manjunath Hadli · Sekhar Nori
1 parent 12db9588ff
Showing 3 changed files with 161 additions and 15 deletions Side-by-side Diff
arch/arm/mach-davinci/board-dm644x-evm.c
arch/arm/mach-davinci/davinci.h
arch/arm/mach-davinci/dm644x.c
@@ -696,7 +696,7 @@
 	evm_init_i2c();
  
 	davinci_setup_mmc(0, &dm6446evm_mmc_config);
-	dm644x_init_video(&dm644xevm_capture_cfg);
+	dm644x_init_video(&dm644xevm_capture_cfg, NULL);
  
 	davinci_serial_init(&uart_config);
 	dm644x_init_asp(&dm644x_evm_snd_data);
@@ -29,9 +29,15 @@
  
 #include <media/davinci/vpfe_capture.h>
 #include <media/davinci/vpif_types.h>
+#include <media/davinci/vpss.h>
+#include <media/davinci/vpbe_types.h>
+#include <media/davinci/vpbe_venc.h>
+#include <media/davinci/vpbe.h>
+#include <media/davinci/vpbe_osd.h>
  
 #define DAVINCI_SYSTEM_MODULE_BASE	0x01c40000
 #define SYSMOD_VIDCLKCTL		0x38
+#define SYSMOD_VPSS_CLKCTL		0x44
 #define SYSMOD_VDD3P3VPWDN		0x48
 #define SYSMOD_VSCLKDIS			0x6c
 #define SYSMOD_PUPDCTL1			0x7c
@@ -83,7 +89,7 @@
 /* DM644x function declarations */
 void __init dm644x_init(void);
 void __init dm644x_init_asp(struct snd_platform_data *pdata);
-int __init dm644x_init_video(struct vpfe_config *);
+int __init dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
  
 /* DM646x function declarations */
 void __init dm646x_init(void);
@@ -627,7 +627,7 @@
 	},
 };
  
-static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
+static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
 static struct resource dm644x_ccdc_resource[] = {
 	/* CCDC Base address */
 	{
@@ -643,7 +643,7 @@
 	.num_resources  = ARRAY_SIZE(dm644x_ccdc_resource),
 	.resource       = dm644x_ccdc_resource,
 	.dev = {
-		.dma_mask               = &vpfe_capture_dma_mask,
+		.dma_mask               = &dm644x_video_dma_mask,
 		.coherent_dma_mask      = DMA_BIT_MASK(32),
 	},
 };
  
@@ -654,11 +654,138 @@
 	.num_resources	= ARRAY_SIZE(dm644x_vpfe_resources),
 	.resource	= dm644x_vpfe_resources,
 	.dev = {
-		.dma_mask		= &vpfe_capture_dma_mask,
+		.dma_mask		= &dm644x_video_dma_mask,
 		.coherent_dma_mask	= DMA_BIT_MASK(32),
 	},
 };
  
+#define DM644X_OSD_BASE		0x01c72600
+
+static struct resource dm644x_osd_resources[] = {
+	{
+		.start	= DM644X_OSD_BASE,
+		.end	= DM644X_OSD_BASE + 0x1ff,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct osd_platform_data dm644x_osd_data = {
+	.vpbe_type     = VPBE_VERSION_1,
+};
+
+static struct platform_device dm644x_osd_dev = {
+	.name		= VPBE_OSD_SUBDEV_NAME,
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(dm644x_osd_resources),
+	.resource	= dm644x_osd_resources,
+	.dev		= {
+		.dma_mask		= &dm644x_video_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+		.platform_data		= &dm644x_osd_data,
+	},
+};
+
+#define DM644X_VENC_BASE		0x01c72400
+
+static struct resource dm644x_venc_resources[] = {
+	{
+		.start	= DM644X_VENC_BASE,
+		.end	= DM644X_VENC_BASE + 0x17f,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+#define DM644X_VPSS_MUXSEL_PLL2_MODE          BIT(0)
+#define DM644X_VPSS_MUXSEL_VPBECLK_MODE       BIT(1)
+#define DM644X_VPSS_VENCLKEN                  BIT(3)
+#define DM644X_VPSS_DACCLKEN                  BIT(4)
+
+static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
+				   unsigned int mode)
+{
+	int ret = 0;
+	u32 v = DM644X_VPSS_VENCLKEN;
+
+	switch (type) {
+	case VPBE_ENC_STD:
+		v |= DM644X_VPSS_DACCLKEN;
+		writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
+		break;
+	case VPBE_ENC_DV_PRESET:
+		switch (mode) {
+		case V4L2_DV_480P59_94:
+		case V4L2_DV_576P50:
+			v |= DM644X_VPSS_MUXSEL_PLL2_MODE |
+			     DM644X_VPSS_DACCLKEN;
+			writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
+			break;
+		case V4L2_DV_720P60:
+		case V4L2_DV_1080I60:
+		case V4L2_DV_1080P30:
+			/*
+			 * For HD, use external clock source since
+			 * HD requires higher clock rate
+			 */
+			v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
+			writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
+			break;
+		default:
+			ret = -EINVAL;
+			break;
+		}
+		break;
+	default:
+		ret  = -EINVAL;
+	}
+
+	return ret;
+}
+
+static struct resource dm644x_v4l2_disp_resources[] = {
+	{
+		.start	= IRQ_VENCINT,
+		.end	= IRQ_VENCINT,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device dm644x_vpbe_display = {
+	.name		= "vpbe-v4l2",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(dm644x_v4l2_disp_resources),
+	.resource	= dm644x_v4l2_disp_resources,
+	.dev		= {
+		.dma_mask		= &dm644x_video_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+};
+
+static struct venc_platform_data dm644x_venc_pdata = {
+	.venc_type	= VPBE_VERSION_1,
+	.setup_clock	= dm644x_venc_setup_clock,
+};
+
+static struct platform_device dm644x_venc_dev = {
+	.name		= VPBE_VENC_SUBDEV_NAME,
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(dm644x_venc_resources),
+	.resource	= dm644x_venc_resources,
+	.dev		= {
+		.dma_mask		= &dm644x_video_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+		.platform_data		= &dm644x_venc_pdata,
+	},
+};
+
+static struct platform_device dm644x_vpbe_dev = {
+	.name		= "vpbe_controller",
+	.id		= -1,
+	.dev		= {
+		.dma_mask		= &dm644x_video_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+};
+
 /*----------------------------------------------------------------------*/
  
 static struct map_desc dm644x_io_desc[] = {
  
  
  
@@ -786,17 +913,30 @@
 	davinci_map_sysmod();
 }
  
-int __init dm644x_init_video(struct vpfe_config *vpfe_cfg)
+int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
+				struct vpbe_config *vpbe_cfg)
 {
-	dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
+	if (vpfe_cfg || vpbe_cfg)
+		platform_device_register(&dm644x_vpss_device);
  
-	/* Add ccdc clock aliases */
-	clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL);
-	clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL);
+	if (vpfe_cfg) {
+		dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
+		platform_device_register(&dm644x_ccdc_dev);
+		platform_device_register(&dm644x_vpfe_dev);
+		/* Add ccdc clock aliases */
+		clk_add_alias("master", dm644x_ccdc_dev.name,
+			      "vpss_master", NULL);
+		clk_add_alias("slave", dm644x_ccdc_dev.name,
+			      "vpss_slave", NULL);
+	}
  
-	platform_device_register(&dm644x_vpss_device);
-	platform_device_register(&dm644x_ccdc_dev);
-	platform_device_register(&dm644x_vpfe_dev);
+	if (vpbe_cfg) {
+		dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
+		platform_device_register(&dm644x_osd_dev);
+		platform_device_register(&dm644x_venc_dev);
+		platform_device_register(&dm644x_vpbe_dev);
+		platform_device_register(&dm644x_vpbe_display);
+	}
  
 	return 0;
 }
...	...	@@ -696,7 +696,7 @@
696	696	evm_init_i2c();
697	697
698	698	davinci_setup_mmc(0, &dm6446evm_mmc_config);
699		- dm644x_init_video(&dm644xevm_capture_cfg);
	699	+ dm644x_init_video(&dm644xevm_capture_cfg, NULL);
700	700
701	701	davinci_serial_init(&uart_config);
702	702	dm644x_init_asp(&dm644x_evm_snd_data);
...	...	@@ -29,9 +29,15 @@
29	29
30	30	#include <media/davinci/vpfe_capture.h>
31	31	#include <media/davinci/vpif_types.h>
	32	+#include <media/davinci/vpss.h>
	33	+#include <media/davinci/vpbe_types.h>
	34	+#include <media/davinci/vpbe_venc.h>
	35	+#include <media/davinci/vpbe.h>
	36	+#include <media/davinci/vpbe_osd.h>
32	37
33	38	#define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000
34	39	#define SYSMOD_VIDCLKCTL 0x38
	40	+#define SYSMOD_VPSS_CLKCTL 0x44
35	41	#define SYSMOD_VDD3P3VPWDN 0x48
36	42	#define SYSMOD_VSCLKDIS 0x6c
37	43	#define SYSMOD_PUPDCTL1 0x7c
...	...	@@ -83,7 +89,7 @@
83	89	/* DM644x function declarations */
84	90	void __init dm644x_init(void);
85	91	void __init dm644x_init_asp(struct snd_platform_data *pdata);
86		-int __init dm644x_init_video(struct vpfe_config *);
	92	+int __init dm644x_init_video(struct vpfe_config , struct vpbe_config );
87	93
88	94	/* DM646x function declarations */
89	95	void __init dm646x_init(void);
...	...	@@ -627,7 +627,7 @@
627	627	},
628	628	};
629	629
630		-static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
	630	+static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
631	631	static struct resource dm644x_ccdc_resource[] = {
632	632	/* CCDC Base address */
633	633	{
...	...	@@ -643,7 +643,7 @@
643	643	.num_resources = ARRAY_SIZE(dm644x_ccdc_resource),
644	644	.resource = dm644x_ccdc_resource,
645	645	.dev = {
646		- .dma_mask = &vpfe_capture_dma_mask,
	646	+ .dma_mask = &dm644x_video_dma_mask,
647	647	.coherent_dma_mask = DMA_BIT_MASK(32),
648	648	},
649	649	};
650	650
...	...	@@ -654,11 +654,138 @@
654	654	.num_resources = ARRAY_SIZE(dm644x_vpfe_resources),
655	655	.resource = dm644x_vpfe_resources,
656	656	.dev = {
657		- .dma_mask = &vpfe_capture_dma_mask,
	657	+ .dma_mask = &dm644x_video_dma_mask,
658	658	.coherent_dma_mask = DMA_BIT_MASK(32),
659	659	},
660	660	};
661	661
	662	+#define DM644X_OSD_BASE 0x01c72600
	663	+
	664	+static struct resource dm644x_osd_resources[] = {
	665	+ {
	666	+ .start = DM644X_OSD_BASE,
	667	+ .end = DM644X_OSD_BASE + 0x1ff,
	668	+ .flags = IORESOURCE_MEM,
	669	+ },
	670	+};
	671	+
	672	+static struct osd_platform_data dm644x_osd_data = {
	673	+ .vpbe_type = VPBE_VERSION_1,
	674	+};
	675	+
	676	+static struct platform_device dm644x_osd_dev = {
	677	+ .name = VPBE_OSD_SUBDEV_NAME,
	678	+ .id = -1,
	679	+ .num_resources = ARRAY_SIZE(dm644x_osd_resources),
	680	+ .resource = dm644x_osd_resources,
	681	+ .dev = {
	682	+ .dma_mask = &dm644x_video_dma_mask,
	683	+ .coherent_dma_mask = DMA_BIT_MASK(32),
	684	+ .platform_data = &dm644x_osd_data,
	685	+ },
	686	+};
	687	+
	688	+#define DM644X_VENC_BASE 0x01c72400
	689	+
	690	+static struct resource dm644x_venc_resources[] = {
	691	+ {
	692	+ .start = DM644X_VENC_BASE,
	693	+ .end = DM644X_VENC_BASE + 0x17f,
	694	+ .flags = IORESOURCE_MEM,
	695	+ },
	696	+};
	697	+
	698	+#define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0)
	699	+#define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1)
	700	+#define DM644X_VPSS_VENCLKEN BIT(3)
	701	+#define DM644X_VPSS_DACCLKEN BIT(4)
	702	+
	703	+static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
	704	+ unsigned int mode)
	705	+{
	706	+ int ret = 0;
	707	+ u32 v = DM644X_VPSS_VENCLKEN;
	708	+
	709	+ switch (type) {
	710	+ case VPBE_ENC_STD:
	711	+ v \|= DM644X_VPSS_DACCLKEN;
	712	+ writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
	713	+ break;
	714	+ case VPBE_ENC_DV_PRESET:
	715	+ switch (mode) {
	716	+ case V4L2_DV_480P59_94:
	717	+ case V4L2_DV_576P50:
	718	+ v \|= DM644X_VPSS_MUXSEL_PLL2_MODE \|
	719	+ DM644X_VPSS_DACCLKEN;
	720	+ writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
	721	+ break;
	722	+ case V4L2_DV_720P60:
	723	+ case V4L2_DV_1080I60:
	724	+ case V4L2_DV_1080P30:
	725	+ /*
	726	+ * For HD, use external clock source since
	727	+ * HD requires higher clock rate
	728	+ */
	729	+ v \|= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
	730	+ writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
	731	+ break;
	732	+ default:
	733	+ ret = -EINVAL;
	734	+ break;
	735	+ }
	736	+ break;
	737	+ default:
	738	+ ret = -EINVAL;
	739	+ }
	740	+
	741	+ return ret;
	742	+}
	743	+
	744	+static struct resource dm644x_v4l2_disp_resources[] = {
	745	+ {
	746	+ .start = IRQ_VENCINT,
	747	+ .end = IRQ_VENCINT,
	748	+ .flags = IORESOURCE_IRQ,
	749	+ },
	750	+};
	751	+
	752	+static struct platform_device dm644x_vpbe_display = {
	753	+ .name = "vpbe-v4l2",
	754	+ .id = -1,
	755	+ .num_resources = ARRAY_SIZE(dm644x_v4l2_disp_resources),
	756	+ .resource = dm644x_v4l2_disp_resources,
	757	+ .dev = {
	758	+ .dma_mask = &dm644x_video_dma_mask,
	759	+ .coherent_dma_mask = DMA_BIT_MASK(32),
	760	+ },
	761	+};
	762	+
	763	+static struct venc_platform_data dm644x_venc_pdata = {
	764	+ .venc_type = VPBE_VERSION_1,
	765	+ .setup_clock = dm644x_venc_setup_clock,
	766	+};
	767	+
	768	+static struct platform_device dm644x_venc_dev = {
	769	+ .name = VPBE_VENC_SUBDEV_NAME,
	770	+ .id = -1,
	771	+ .num_resources = ARRAY_SIZE(dm644x_venc_resources),
	772	+ .resource = dm644x_venc_resources,
	773	+ .dev = {
	774	+ .dma_mask = &dm644x_video_dma_mask,
	775	+ .coherent_dma_mask = DMA_BIT_MASK(32),
	776	+ .platform_data = &dm644x_venc_pdata,
	777	+ },
	778	+};
	779	+
	780	+static struct platform_device dm644x_vpbe_dev = {
	781	+ .name = "vpbe_controller",
	782	+ .id = -1,
	783	+ .dev = {
	784	+ .dma_mask = &dm644x_video_dma_mask,
	785	+ .coherent_dma_mask = DMA_BIT_MASK(32),
	786	+ },
	787	+};
	788	+
662	789	/----------------------------------------------------------------------/
663	790
664	791	static struct map_desc dm644x_io_desc[] = {
665	792
666	793
667	794
...	...	@@ -786,17 +913,30 @@
786	913	davinci_map_sysmod();
787	914	}
788	915
789		-int __init dm644x_init_video(struct vpfe_config *vpfe_cfg)
	916	+int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
	917	+ struct vpbe_config *vpbe_cfg)
790	918	{
791		- dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
	919	+ if (vpfe_cfg \|\| vpbe_cfg)
	920	+ platform_device_register(&dm644x_vpss_device);
792	921
793		- /* Add ccdc clock aliases */
794		- clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL);
795		- clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL);
	922	+ if (vpfe_cfg) {
	923	+ dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
	924	+ platform_device_register(&dm644x_ccdc_dev);
	925	+ platform_device_register(&dm644x_vpfe_dev);
	926	+ /* Add ccdc clock aliases */
	927	+ clk_add_alias("master", dm644x_ccdc_dev.name,
	928	+ "vpss_master", NULL);
	929	+ clk_add_alias("slave", dm644x_ccdc_dev.name,
	930	+ "vpss_slave", NULL);
	931	+ }
796	932
797		- platform_device_register(&dm644x_vpss_device);
798		- platform_device_register(&dm644x_ccdc_dev);
799		- platform_device_register(&dm644x_vpfe_dev);
	933	+ if (vpbe_cfg) {
	934	+ dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
	935	+ platform_device_register(&dm644x_osd_dev);
	936	+ platform_device_register(&dm644x_venc_dev);
	937	+ platform_device_register(&dm644x_vpbe_dev);
	938	+ platform_device_register(&dm644x_vpbe_display);
	939	+ }
800	940
801	941	return 0;
802	942	}