Commit b1beab48f6148d50fee4a56d741cc3168fe1b995

Authored by Len Brown
1 parent 88b62b915b

intel_idle: stop using driver_data for static flags

The commit, 4202735e8ab6ecfb0381631a0d0b58fefe0bd4e2
(cpuidle: Split cpuidle_state structure and move per-cpu statistics fields)
observed that the MWAIT flags for Cn on every processor to date were the
same, and created get_driver_data() to supply them.

Unfortunately, that assumption is false, going forward.
So here we restore the MWAIT flags to the cpuidle_state table.
However, instead restoring the old "driver_data" field,
we put the flags into the existing "flags" field,
where they probalby should have lived all along.

This patch does not change any operation.

This patch removes 1 of the 3 users of cpuidle_state_usage.driver_data.
Perhaps some day we'll get rid of the other 2.

Signed-off-by: Len Brown <len.brown@intel.com>

Showing 1 changed file with 26 additions and 49 deletions Side-by-side Diff

drivers/idle/intel_idle.c
... ... @@ -109,6 +109,16 @@
109 109 #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000
110 110  
111 111 /*
  112 + * MWAIT takes an 8-bit "hint" in EAX "suggesting"
  113 + * the C-state (top nibble) and sub-state (bottom nibble)
  114 + * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
  115 + *
  116 + * We store the hint at the top of our "flags" for each state.
  117 + */
  118 +#define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
  119 +#define MWAIT2flg(eax) ((eax & 0xFF) << 24)
  120 +
  121 +/*
112 122 * States are indexed by the cstate number,
113 123 * which is also the index into the MWAIT hint array.
114 124 * Thus C0 is a dummy.
115 125  
116 126  
... ... @@ -118,21 +128,21 @@
118 128 { /* MWAIT C1 */
119 129 .name = "C1-NHM",
120 130 .desc = "MWAIT 0x00",
121   - .flags = CPUIDLE_FLAG_TIME_VALID,
  131 + .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
122 132 .exit_latency = 3,
123 133 .target_residency = 6,
124 134 .enter = &intel_idle },
125 135 { /* MWAIT C2 */
126 136 .name = "C3-NHM",
127 137 .desc = "MWAIT 0x10",
128   - .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
  138 + .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
129 139 .exit_latency = 20,
130 140 .target_residency = 80,
131 141 .enter = &intel_idle },
132 142 { /* MWAIT C3 */
133 143 .name = "C6-NHM",
134 144 .desc = "MWAIT 0x20",
135   - .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
  145 + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
136 146 .exit_latency = 200,
137 147 .target_residency = 800,
138 148 .enter = &intel_idle },
139 149  
140 150  
141 151  
... ... @@ -143,28 +153,28 @@
143 153 { /* MWAIT C1 */
144 154 .name = "C1-SNB",
145 155 .desc = "MWAIT 0x00",
146   - .flags = CPUIDLE_FLAG_TIME_VALID,
  156 + .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
147 157 .exit_latency = 1,
148 158 .target_residency = 1,
149 159 .enter = &intel_idle },
150 160 { /* MWAIT C2 */
151 161 .name = "C3-SNB",
152 162 .desc = "MWAIT 0x10",
153   - .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
  163 + .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
154 164 .exit_latency = 80,
155 165 .target_residency = 211,
156 166 .enter = &intel_idle },
157 167 { /* MWAIT C3 */
158 168 .name = "C6-SNB",
159 169 .desc = "MWAIT 0x20",
160   - .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
  170 + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
161 171 .exit_latency = 104,
162 172 .target_residency = 345,
163 173 .enter = &intel_idle },
164 174 { /* MWAIT C4 */
165 175 .name = "C7-SNB",
166 176 .desc = "MWAIT 0x30",
167   - .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
  177 + .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
168 178 .exit_latency = 109,
169 179 .target_residency = 345,
170 180 .enter = &intel_idle },
171 181  
172 182  
173 183  
... ... @@ -175,28 +185,28 @@
175 185 { /* MWAIT C1 */
176 186 .name = "C1-IVB",
177 187 .desc = "MWAIT 0x00",
178   - .flags = CPUIDLE_FLAG_TIME_VALID,
  188 + .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
179 189 .exit_latency = 1,
180 190 .target_residency = 1,
181 191 .enter = &intel_idle },
182 192 { /* MWAIT C2 */
183 193 .name = "C3-IVB",
184 194 .desc = "MWAIT 0x10",
185   - .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
  195 + .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
186 196 .exit_latency = 59,
187 197 .target_residency = 156,
188 198 .enter = &intel_idle },
189 199 { /* MWAIT C3 */
190 200 .name = "C6-IVB",
191 201 .desc = "MWAIT 0x20",
192   - .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
  202 + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
193 203 .exit_latency = 80,
194 204 .target_residency = 300,
195 205 .enter = &intel_idle },
196 206 { /* MWAIT C4 */
197 207 .name = "C7-IVB",
198 208 .desc = "MWAIT 0x30",
199   - .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
  209 + .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
200 210 .exit_latency = 87,
201 211 .target_residency = 300,
202 212 .enter = &intel_idle },
203 213  
... ... @@ -207,14 +217,14 @@
207 217 { /* MWAIT C1 */
208 218 .name = "C1-ATM",
209 219 .desc = "MWAIT 0x00",
210   - .flags = CPUIDLE_FLAG_TIME_VALID,
  220 + .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
211 221 .exit_latency = 1,
212 222 .target_residency = 4,
213 223 .enter = &intel_idle },
214 224 { /* MWAIT C2 */
215 225 .name = "C2-ATM",
216 226 .desc = "MWAIT 0x10",
217   - .flags = CPUIDLE_FLAG_TIME_VALID,
  227 + .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID,
218 228 .exit_latency = 20,
219 229 .target_residency = 80,
220 230 .enter = &intel_idle },
... ... @@ -222,7 +232,7 @@
222 232 { /* MWAIT C4 */
223 233 .name = "C4-ATM",
224 234 .desc = "MWAIT 0x30",
225   - .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
  235 + .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
226 236 .exit_latency = 100,
227 237 .target_residency = 400,
228 238 .enter = &intel_idle },
229 239  
... ... @@ -230,41 +240,12 @@
230 240 { /* MWAIT C6 */
231 241 .name = "C6-ATM",
232 242 .desc = "MWAIT 0x52",
233   - .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
  243 + .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
234 244 .exit_latency = 140,
235 245 .target_residency = 560,
236 246 .enter = &intel_idle },
237 247 };
238 248  
239   -static long get_driver_data(int cstate)
240   -{
241   - int driver_data;
242   - switch (cstate) {
243   -
244   - case 1: /* MWAIT C1 */
245   - driver_data = 0x00;
246   - break;
247   - case 2: /* MWAIT C2 */
248   - driver_data = 0x10;
249   - break;
250   - case 3: /* MWAIT C3 */
251   - driver_data = 0x20;
252   - break;
253   - case 4: /* MWAIT C4 */
254   - driver_data = 0x30;
255   - break;
256   - case 5: /* MWAIT C5 */
257   - driver_data = 0x40;
258   - break;
259   - case 6: /* MWAIT C6 */
260   - driver_data = 0x52;
261   - break;
262   - default:
263   - driver_data = 0x00;
264   - }
265   - return driver_data;
266   -}
267   -
268 249 /**
269 250 * intel_idle
270 251 * @dev: cpuidle_device
... ... @@ -278,8 +259,7 @@
278 259 {
279 260 unsigned long ecx = 1; /* break on interrupt flag */
280 261 struct cpuidle_state *state = &drv->states[index];
281   - struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
282   - unsigned long eax = (unsigned long)cpuidle_get_statedata(state_usage);
  262 + unsigned long eax = flg2MWAIT(state->flags);
283 263 unsigned int cstate;
284 264 int cpu = smp_processor_id();
285 265  
... ... @@ -557,9 +537,6 @@
557 537 /* is the state not enabled? */
558 538 if (cpuidle_state_table[cstate].enter == NULL)
559 539 continue;
560   -
561   - dev->states_usage[dev->state_count].driver_data =
562   - (void *)get_driver_data(cstate);
563 540  
564 541 dev->state_count += 1;
565 542 }