Doug / smarc-fsl-linux-kernel

Download as
Browse Code ยป

Commit b5affb0147cee0ea05d909396f8e389092729236

Authored by Bob Liu
1 parent 22a8262885
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

blackfin: add bf60x to current framework 

This patch added bf60x to current blackfin kernel framework.

Signed-off-by: Bob Liu <lliubbo@gmail.com>

Showing 19 changed files with 840 additions and 146 deletions Side-by-side Diff

arch/blackfin/Kconfig
Diff comments   View file @ b5affb0
... ... @@ -226,6 +226,12 @@
226 226 help
227 227 BF561 Processor Support.
228 228  
  229 +config BF609
  230 + bool "BF609"
  231 + select CLKDEV_LOOKUP
  232 + help
  233 + BF609 Processor Support.
  234 +
229 235 endchoice
230 236  
231 237 config SMP
232 238  
233 239  
234 240  
... ... @@ -251,27 +257,27 @@
251 257  
252 258 config BF_REV_MIN
253 259 int
254   - default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
  260 + default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
255 261 default 2 if (BF537 || BF536 || BF534)
256 262 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
257 263 default 4 if (BF538 || BF539)
258 264  
259 265 config BF_REV_MAX
260 266 int
261   - default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
  267 + default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
262 268 default 3 if (BF537 || BF536 || BF534 || BF54xM)
263 269 default 5 if (BF561 || BF538 || BF539)
264 270 default 6 if (BF533 || BF532 || BF531)
265 271  
266 272 choice
267 273 prompt "Silicon Rev"
268   - default BF_REV_0_0 if (BF51x || BF52x)
  274 + default BF_REV_0_0 if (BF51x || BF52x || BF60x)
269 275 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
270 276 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
271 277  
272 278 config BF_REV_0_0
273 279 bool "0.0"
274   - depends on (BF51x || BF52x || (BF54x && !BF54xM))
  280 + depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
275 281  
276 282 config BF_REV_0_1
277 283 bool "0.1"
... ... @@ -350,6 +356,7 @@
350 356 source "arch/blackfin/mach-bf537/Kconfig"
351 357 source "arch/blackfin/mach-bf538/Kconfig"
352 358 source "arch/blackfin/mach-bf548/Kconfig"
  359 +source "arch/blackfin/mach-bf609/Kconfig"
353 360  
354 361 menu "Board customizations"
355 362  
... ... @@ -379,6 +386,12 @@
379 386 memory region is used to capture NULL pointer references as well
380 387 as some core kernel functions.
381 388  
  389 +config PHY_RAM_BASE_ADDRESS
  390 + hex "Physical RAM Base"
  391 + default 0x0
  392 + help
  393 + set BF609 FPGA physical SRAM base address
  394 +
382 395 config ROM_BASE
383 396 hex "Kernel ROM Base"
384 397 depends on ROMKERNEL
... ... @@ -1051,7 +1064,7 @@
1051 1064 config BFIN_L2_DCACHEABLE
1052 1065 bool "Enable DCACHE for L2 SRAM"
1053 1066 depends on BFIN_DCACHE
1054   - depends on (BF54x || BF561) && !SMP
  1067 + depends on (BF54x || BF561 || BF60x) && !SMP
1055 1068 default n
1056 1069 choice
1057 1070 prompt "L2 SRAM DCACHE policy"
... ... @@ -1077,6 +1090,7 @@
1077 1090 comment "Asynchronous Memory Configuration"
1078 1091  
1079 1092 menu "EBIU_AMGCTL Global Control"
  1093 + depends on !BF60x
1080 1094 config C_AMCKEN
1081 1095 bool "Enable CLKOUT"
1082 1096 default y
... ... @@ -1127,6 +1141,7 @@
1127 1141 endmenu
1128 1142  
1129 1143 menu "EBIU_AMBCTL Control"
  1144 + depends on !BF60x
1130 1145 config BANK_0
1131 1146 hex "Bank 0 (AMBCTL0.L)"
1132 1147 default 0x7BB0
arch/blackfin/Makefile
Diff comments   View file @ b5affb0
... ... @@ -54,6 +54,7 @@
54 54 machine-$(CONFIG_BF549) := bf548
55 55 machine-$(CONFIG_BF549M) := bf548
56 56 machine-$(CONFIG_BF561) := bf561
  57 +machine-$(CONFIG_BF609) := bf609
57 58 MACHINE := $(machine-y)
58 59 export MACHINE
59 60  
... ... @@ -86,6 +87,7 @@
86 87 cpu-$(CONFIG_BF549) := bf549
87 88 cpu-$(CONFIG_BF549M) := bf549m
88 89 cpu-$(CONFIG_BF561) := bf561
  90 +cpu-$(CONFIG_BF609) := bf609
89 91  
90 92 rev-$(CONFIG_BF_REV_0_0) := 0.0
91 93 rev-$(CONFIG_BF_REV_0_1) := 0.1
arch/blackfin/configs/BF609-EZKIT_defconfig
Diff comments   View file @ b5affb0
  1 +CONFIG_EXPERIMENTAL=y
  2 +CONFIG_SYSVIPC=y
  3 +CONFIG_IKCONFIG=y
  4 +CONFIG_IKCONFIG_PROC=y
  5 +CONFIG_LOG_BUF_SHIFT=14
  6 +CONFIG_BLK_DEV_INITRD=y
  7 +CONFIG_EXPERT=y
  8 +# CONFIG_ELF_CORE is not set
  9 +# CONFIG_FUTEX is not set
  10 +# CONFIG_SIGNALFD is not set
  11 +# CONFIG_TIMERFD is not set
  12 +# CONFIG_EVENTFD is not set
  13 +# CONFIG_AIO is not set
  14 +CONFIG_SLAB=y
  15 +CONFIG_MMAP_ALLOW_UNINITIALIZED=y
  16 +CONFIG_MODULES=y
  17 +CONFIG_MODULE_UNLOAD=y
  18 +# CONFIG_LBDAF is not set
  19 +# CONFIG_BLK_DEV_BSG is not set
  20 +# CONFIG_IOSCHED_DEADLINE is not set
  21 +# CONFIG_IOSCHED_CFQ is not set
  22 +CONFIG_PREEMPT_VOLUNTARY=y
  23 +CONFIG_BF609=y
  24 +CONFIG_PINT1_ASSIGN=0x01010000
  25 +CONFIG_PINT2_ASSIGN=0x07000101
  26 +CONFIG_PINT3_ASSIGN=0x02020303
  27 +CONFIG_HIGH_RES_TIMERS=y
  28 +CONFIG_IP_CHECKSUM_L1=y
  29 +CONFIG_SYSCALL_TAB_L1=y
  30 +CONFIG_CPLB_SWITCH_TAB_L1=y
  31 +# CONFIG_APP_STACK_L1 is not set
  32 +# CONFIG_BFIN_INS_LOWOVERHEAD is not set
  33 +CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
  34 +CONFIG_BINFMT_FLAT=y
  35 +CONFIG_BINFMT_ZFLAT=y
  36 +# CONFIG_SUSPEND is not set
  37 +CONFIG_CPU_FREQ=y
  38 +CONFIG_CPU_FREQ_GOV_POWERSAVE=y
  39 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
  40 +CONFIG_NET=y
  41 +CONFIG_PACKET=y
  42 +CONFIG_UNIX=y
  43 +CONFIG_INET=y
  44 +CONFIG_IP_PNP=y
  45 +CONFIG_IP_PNP_DHCP=y
  46 +CONFIG_IP_PNP_BOOTP=y
  47 +CONFIG_IP_PNP_RARP=y
  48 +# CONFIG_IPV6 is not set
  49 +CONFIG_NETFILTER=y
  50 +CONFIG_CAN=y
  51 +CONFIG_CAN_BFIN=y
  52 +CONFIG_IRDA=y
  53 +CONFIG_IRTTY_SIR=y
  54 +# CONFIG_WIRELESS is not set
  55 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
  56 +CONFIG_FW_LOADER=m
  57 +CONFIG_MTD=y
  58 +CONFIG_MTD_CMDLINE_PARTS=y
  59 +CONFIG_MTD_CHAR=y
  60 +CONFIG_MTD_CFI=y
  61 +CONFIG_MTD_CFI_INTELEXT=y
  62 +CONFIG_MTD_CFI_STAA=y
  63 +CONFIG_MTD_COMPLEX_MAPPINGS=y
  64 +CONFIG_MTD_BFIN_BF60x=y
  65 +CONFIG_MTD_M25P80=y
  66 +CONFIG_MTD_UBI=m
  67 +CONFIG_SCSI=y
  68 +CONFIG_BLK_DEV_SD=y
  69 +CONFIG_NETDEVICES=y
  70 +# CONFIG_NET_VENDOR_BROADCOM is not set
  71 +# CONFIG_NET_VENDOR_CHELSIO is not set
  72 +# CONFIG_NET_VENDOR_INTEL is not set
  73 +# CONFIG_NET_VENDOR_MARVELL is not set
  74 +# CONFIG_NET_VENDOR_MICREL is not set
  75 +# CONFIG_NET_VENDOR_MICROCHIP is not set
  76 +# CONFIG_NET_VENDOR_NATSEMI is not set
  77 +# CONFIG_NET_VENDOR_SEEQ is not set
  78 +# CONFIG_NET_VENDOR_SMSC is not set
  79 +CONFIG_STMMAC_ETH=y
  80 +CONFIG_STMMAC_IEEE1588=y
  81 +# CONFIG_WLAN is not set
  82 +# CONFIG_INPUT_MOUSEDEV is not set
  83 +CONFIG_INPUT_EVDEV=y
  84 +# CONFIG_INPUT_KEYBOARD is not set
  85 +# CONFIG_INPUT_MOUSE is not set
  86 +CONFIG_INPUT_MISC=y
  87 +CONFIG_INPUT_BFIN_ROTARY=y
  88 +# CONFIG_SERIO is not set
  89 +# CONFIG_LEGACY_PTYS is not set
  90 +CONFIG_BFIN_SIMPLE_TIMER=m
  91 +CONFIG_BFIN_LINKPORT=y
  92 +# CONFIG_DEVKMEM is not set
  93 +CONFIG_SERIAL_BFIN=y
  94 +CONFIG_SERIAL_BFIN_CONSOLE=y
  95 +CONFIG_SERIAL_BFIN_UART0=y
  96 +# CONFIG_HW_RANDOM is not set
  97 +CONFIG_I2C=y
  98 +CONFIG_I2C_CHARDEV=y
  99 +CONFIG_I2C_BLACKFIN_TWI=y
  100 +CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
  101 +CONFIG_SPI=y
  102 +CONFIG_SPI_BFIN6XX=y
  103 +CONFIG_GPIOLIB=y
  104 +CONFIG_GPIO_SYSFS=y
  105 +# CONFIG_HWMON is not set
  106 +CONFIG_WATCHDOG=y
  107 +CONFIG_BFIN_WDT=y
  108 +CONFIG_SOUND=m
  109 +CONFIG_SND=m
  110 +CONFIG_SND_MIXER_OSS=m
  111 +CONFIG_SND_PCM_OSS=m
  112 +# CONFIG_SND_DRIVERS is not set
  113 +# CONFIG_SND_SPI is not set
  114 +# CONFIG_SND_USB is not set
  115 +CONFIG_SND_SOC=m
  116 +CONFIG_SND_BF6XX_I2S=m
  117 +CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61=m
  118 +CONFIG_SND_SOC_ALL_CODECS=m
  119 +CONFIG_USB=y
  120 +CONFIG_USB_MUSB_HDRC=y
  121 +CONFIG_USB_MUSB_BLACKFIN=y
  122 +CONFIG_USB_STORAGE=y
  123 +CONFIG_USB_GADGET=y
  124 +CONFIG_USB_GADGET_MUSB_HDRC=y
  125 +CONFIG_USB_ZERO=y
  126 +CONFIG_MMC=y
  127 +CONFIG_SDH_BFIN=y
  128 +# CONFIG_IOMMU_SUPPORT is not set
  129 +CONFIG_EXT2_FS=y
  130 +# CONFIG_DNOTIFY is not set
  131 +CONFIG_MSDOS_FS=y
  132 +CONFIG_VFAT_FS=y
  133 +CONFIG_JFFS2_FS=m
  134 +CONFIG_UBIFS_FS=m
  135 +CONFIG_NFS_FS=m
  136 +CONFIG_NFS_V3=y
  137 +CONFIG_NLS_CODEPAGE_437=y
  138 +CONFIG_NLS_ISO8859_1=y
  139 +CONFIG_DEBUG_FS=y
  140 +CONFIG_DEBUG_SHIRQ=y
  141 +CONFIG_DETECT_HUNG_TASK=y
  142 +CONFIG_DEBUG_INFO=y
  143 +CONFIG_FRAME_POINTER=y
  144 +# CONFIG_FTRACE is not set
  145 +CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
  146 +CONFIG_EARLY_PRINTK=y
  147 +CONFIG_CPLB_INFO=y
  148 +CONFIG_BFIN_PSEUDODBG_INSNS=y
  149 +CONFIG_CRYPTO_HMAC=y
  150 +CONFIG_CRYPTO_MD4=y
  151 +CONFIG_CRYPTO_MD5=y
  152 +CONFIG_CRYPTO_ARC4=y
  153 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
arch/blackfin/include/asm/bfin-global.h
Diff comments   View file @ b5affb0
... ... @@ -35,6 +35,11 @@
35 35  
36 36 extern unsigned long get_cclk(void);
37 37 extern unsigned long get_sclk(void);
  38 +#ifdef CONFIG_BF60x
  39 +extern unsigned long get_sclk0(void);
  40 +extern unsigned long get_sclk1(void);
  41 +extern unsigned long get_dramclk(void);
  42 +#endif
38 43 extern unsigned long sclk_to_usecs(unsigned long sclk);
39 44 extern unsigned long usecs_to_sclk(unsigned long usecs);
40 45  
arch/blackfin/include/asm/bfin_dma.h
Diff comments   View file @ b5affb0
... ... @@ -15,12 +15,55 @@
15 15 #define DMAEN 0x0001 /* DMA Channel Enable */
16 16 #define WNR 0x0002 /* Channel Direction (W/R*) */
17 17 #define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
  18 +#define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */
  19 +
  20 +#ifdef CONFIG_BF60x
  21 +
  22 +#define PSIZE_16 0x00000010 /* Transfer Word Size = 16 */
  23 +#define PSIZE_32 0x00000020 /* Transfer Word Size = 32 */
  24 +#define PSIZE_64 0x00000030 /* Transfer Word Size = 32 */
  25 +#define WDSIZE_16 0x00000100 /* Transfer Word Size = 16 */
  26 +#define WDSIZE_32 0x00000200 /* Transfer Word Size = 32 */
  27 +#define WDSIZE_64 0x00000300 /* Transfer Word Size = 32 */
  28 +#define WDSIZE_128 0x00000400 /* Transfer Word Size = 32 */
  29 +#define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */
  30 +#define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */
  31 +#define RESTART 0x00000004 /* DMA Buffer Clear SYNC */
  32 +#define DI_EN_X 0x00100000 /* Data Interrupt Enable in X count */
  33 +#define DI_EN_Y 0x00200000 /* Data Interrupt Enable in Y count */
  34 +#define DI_EN_P 0x00300000 /* Data Interrupt Enable in Peripheral */
  35 +#define DI_EN DI_EN_X /* Data Interrupt Enable */
  36 +#define NDSIZE_0 0x00000000 /* Next Descriptor Size = 1 */
  37 +#define NDSIZE_1 0x00010000 /* Next Descriptor Size = 2 */
  38 +#define NDSIZE_2 0x00020000 /* Next Descriptor Size = 3 */
  39 +#define NDSIZE_3 0x00030000 /* Next Descriptor Size = 4 */
  40 +#define NDSIZE_4 0x00040000 /* Next Descriptor Size = 5 */
  41 +#define NDSIZE_5 0x00050000 /* Next Descriptor Size = 6 */
  42 +#define NDSIZE_6 0x00060000 /* Next Descriptor Size = 7 */
  43 +#define NDSIZE 0x00070000 /* Next Descriptor Size */
  44 +#define NDSIZE_OFFSET 16 /* Next Descriptor Size Offset */
  45 +#define DMAFLOW_LIST 0x00004000 /* Descriptor List Mode */
  46 +#define DMAFLOW_LARGE DMAFLOW_LIST
  47 +#define DMAFLOW_ARRAY 0x00005000 /* Descriptor Array Mode */
  48 +#define DMAFLOW_LIST_DEMAND 0x00006000 /* Descriptor Demand List Mode */
  49 +#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Descriptor Demand Array Mode */
  50 +#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Running Indicator (DFETCH) */
  51 +#define DMA_RUN 0x00000200 /* DMA Channel Running Indicator */
  52 +#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Running Indicator (WAIT TRIG) */
  53 +#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Running Indicator (WAIT ACK) */
  54 +
  55 +#else
  56 +
  57 +#define PSIZE_16 0x0000 /* Transfer Word Size = 16 */
  58 +#define PSIZE_32 0x0000 /* Transfer Word Size = 32 */
18 59 #define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
19 60 #define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
20 61 #define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
21 62 #define RESTART 0x0020 /* DMA Buffer Clear */
22 63 #define DI_SEL 0x0040 /* Data Interrupt Timing Select */
23 64 #define DI_EN 0x0080 /* Data Interrupt Enable */
  65 +#define DI_EN_X 0x00C0 /* Data Interrupt Enable in X count*/
  66 +#define DI_EN_Y 0x0080 /* Data Interrupt Enable in Y count*/
24 67 #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
25 68 #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
26 69 #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
27 70  
28 71  
29 72  
... ... @@ -32,18 +75,26 @@
32 75 #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
33 76 #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
34 77 #define NDSIZE 0x0f00 /* Next Descriptor Size */
35   -#define DMAFLOW 0x7000 /* Flow Control */
36   -#define DMAFLOW_STOP 0x0000 /* Stop Mode */
37   -#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
  78 +#define NDSIZE_OFFSET 8 /* Next Descriptor Size Offset */
38 79 #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
39 80 #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
40 81 #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
  82 +#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
  83 +#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
41 84  
  85 +#endif
  86 +#define DMAFLOW 0x7000 /* Flow Control */
  87 +#define DMAFLOW_STOP 0x0000 /* Stop Mode */
  88 +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
  89 +
42 90 /* DMA_IRQ_STATUS Masks */
43 91 #define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
44 92 #define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
45   -#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
46   -#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
  93 +#ifdef CONFIG_BF60x
  94 +#define DMA_PIRQ 0x0004 /* DMA Peripheral Error Interrupt Status */
  95 +#else
  96 +#define DMA_PIRQ 0
  97 +#endif
47 98  
48 99 /*
49 100 * All Blackfin system MMRs are padded to 32bits even if the register
... ... @@ -57,6 +108,26 @@
57 108 struct bfin_dma_regs {
58 109 u32 next_desc_ptr;
59 110 u32 start_addr;
  111 +#ifdef CONFIG_BF60x
  112 + u32 cfg;
  113 + u32 x_count;
  114 + u32 x_modify;
  115 + u32 y_count;
  116 + u32 y_modify;
  117 + u32 pad1;
  118 + u32 pad2;
  119 + u32 curr_desc_ptr;
  120 + u32 prev_desc_ptr;
  121 + u32 curr_addr;
  122 + u32 irq_status;
  123 + u32 curr_x_count;
  124 + u32 curr_y_count;
  125 + u32 pad3;
  126 + u32 bw_limit_count;
  127 + u32 curr_bw_limit_count;
  128 + u32 bw_monitor_count;
  129 + u32 curr_bw_monitor_count;
  130 +#else
60 131 __BFP(config);
61 132 u32 __pad0;
62 133 __BFP(x_count);
63 134  
... ... @@ -71,8 +142,10 @@
71 142 u32 __pad1;
72 143 __BFP(curr_y_count);
73 144 u32 __pad2;
  145 +#endif
74 146 };
75 147  
  148 +#ifndef CONFIG_BF60x
76 149 /*
77 150 * bfin handshake mdma registers layout
78 151 */
... ... @@ -85,6 +158,7 @@
85 158 __BFP(ecount);
86 159 __BFP(bcount);
87 160 };
  161 +#endif
88 162  
89 163 #undef __BFP
90 164  
arch/blackfin/include/asm/bfin_serial.h
Diff comments   View file @ b5affb0
... ... @@ -18,7 +18,7 @@
18 18 defined(CONFIG_BFIN_UART1_CTSRTS) || \
19 19 defined(CONFIG_BFIN_UART2_CTSRTS) || \
20 20 defined(CONFIG_BFIN_UART3_CTSRTS)
21   -# ifdef BFIN_UART_BF54X_STYLE
  21 +# if defined(BFIN_UART_BF54X_STYLE) || defined(BFIN_UART_BF60X_STYLE)
22 22 # define CONFIG_SERIAL_BFIN_HARD_CTSRTS
23 23 # else
24 24 # define CONFIG_SERIAL_BFIN_CTSRTS
25 25  
26 26  
... ... @@ -58,14 +58,67 @@
58 58 #endif
59 59 };
60 60  
  61 +#ifdef BFIN_UART_BF60X_STYLE
  62 +
  63 +/* UART_CTL Masks */
  64 +#define UCEN 0x1 /* Enable UARTx Clocks */
  65 +#define LOOP_ENA 0x2 /* Loopback Mode Enable */
  66 +#define UMOD_MDB 0x10 /* Enable MDB Mode */
  67 +#define UMOD_IRDA 0x20 /* Enable IrDA Mode */
  68 +#define UMOD_MASK 0x30 /* Uart Mode Mask */
  69 +#define WLS(x) (((x-5) & 0x03) << 8) /* Word Length Select */
  70 +#define WLS_MASK 0x300 /* Word length Select Mask */
  71 +#define STB 0x1000 /* Stop Bits */
  72 +#define STBH 0x2000 /* Half Stop Bits */
  73 +#define PEN 0x4000 /* Parity Enable */
  74 +#define EPS 0x8000 /* Even Parity Select */
  75 +#define STP 0x10000 /* Stick Parity */
  76 +#define FPE 0x20000 /* Force Parity Error On Transmit */
  77 +#define FFE 0x40000 /* Force Framing Error On Transmit */
  78 +#define SB 0x80000 /* Set Break */
  79 +#define LCR_MASK (STP | EPS | PEN | STB | WLS_MASK)
  80 +#define FCPOL 0x400000 /* Flow Control Pin Polarity */
  81 +#define RPOLC 0x800000 /* IrDA RX Polarity Change */
  82 +#define TPOLC 0x1000000 /* IrDA TX Polarity Change */
  83 +#define MRTS 0x2000000 /* Manual Request To Send */
  84 +#define XOFF 0x4000000 /* Transmitter Off */
  85 +#define ARTS 0x8000000 /* Automatic Request To Send */
  86 +#define ACTS 0x10000000 /* Automatic Clear To Send */
  87 +#define RFIT 0x20000000 /* Receive FIFO IRQ Threshold */
  88 +#define RFRT 0x40000000 /* Receive FIFO RTS Threshold */
  89 +
  90 +/* UART_STAT Masks */
  91 +#define DR 0x01 /* Data Ready */
  92 +#define OE 0x02 /* Overrun Error */
  93 +#define PE 0x04 /* Parity Error */
  94 +#define FE 0x08 /* Framing Error */
  95 +#define BI 0x10 /* Break Interrupt */
  96 +#define THRE 0x20 /* THR Empty */
  97 +#define TEMT 0x80 /* TSR and UART_THR Empty */
  98 +#define TFI 0x100 /* Transmission Finished Indicator */
  99 +
  100 +#define ASTKY 0x200 /* Address Sticky */
  101 +#define ADDR 0x400 /* Address bit status */
  102 +#define RO 0x800 /* Reception Ongoing */
  103 +#define SCTS 0x1000 /* Sticky CTS */
  104 +#define CTS 0x10000 /* Clear To Send */
  105 +#define RFCS 0x20000 /* Receive FIFO Count Status */
  106 +
  107 +/* UART_CLOCK Masks */
  108 +#define EDBO 0x80000000 /* Enable Devide by One */
  109 +
  110 +#else /* BFIN_UART_BF60X_STYLE */
  111 +
61 112 /* UART_LCR Masks */
62 113 #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
  114 +#define WLS_MASK 0x03 /* Word length Select Mask */
63 115 #define STB 0x04 /* Stop Bits */
64 116 #define PEN 0x08 /* Parity Enable */
65 117 #define EPS 0x10 /* Even Parity Select */
66 118 #define STP 0x20 /* Stick Parity */
67 119 #define SB 0x40 /* Set Break */
68 120 #define DLAB 0x80 /* Divisor Latch Access */
  121 +#define LCR_MASK (STP | EPS | PEN | STB | WLS_MASK)
69 122  
70 123 /* UART_LSR Masks */
71 124 #define DR 0x01 /* Data Ready */
... ... @@ -77,15 +130,6 @@
77 130 #define TEMT 0x40 /* TSR and UART_THR Empty */
78 131 #define TFI 0x80 /* Transmission Finished Indicator */
79 132  
80   -/* UART_IER Masks */
81   -#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
82   -#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
83   -#define ELSI 0x04 /* Enable RX Status Interrupt */
84   -#define EDSSI 0x08 /* Enable Modem Status Interrupt */
85   -#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
86   -#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
87   -#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
88   -
89 133 /* UART_MCR Masks */
90 134 #define XOFF 0x01 /* Transmitter Off */
91 135 #define MRTS 0x02 /* Manual Request To Send */
92 136  
... ... @@ -103,13 +147,36 @@
103 147  
104 148 /* UART_GCTL Masks */
105 149 #define UCEN 0x01 /* Enable UARTx Clocks */
106   -#define IREN 0x02 /* Enable IrDA Mode */
  150 +#define UMOD_IRDA 0x02 /* Enable IrDA Mode */
  151 +#define UMOD_MASK 0x02 /* Uart Mode Mask */
107 152 #define TPOLC 0x04 /* IrDA TX Polarity Change */
108 153 #define RPOLC 0x08 /* IrDA RX Polarity Change */
109 154 #define FPE 0x10 /* Force Parity Error On Transmit */
110 155 #define FFE 0x20 /* Force Framing Error On Transmit */
111 156  
112   -#ifdef BFIN_UART_BF54X_STYLE
  157 +#endif /* BFIN_UART_BF60X_STYLE */
  158 +
  159 +/* UART_IER Masks */
  160 +#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
  161 +#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
  162 +#define ELSI 0x04 /* Enable RX Status Interrupt */
  163 +#define EDSSI 0x08 /* Enable Modem Status Interrupt */
  164 +#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
  165 +#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
  166 +#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
  167 +
  168 +#if defined(BFIN_UART_BF60X_STYLE)
  169 +# define OFFSET_REDIV 0x00 /* Version ID Register */
  170 +# define OFFSET_CTL 0x04 /* Control Register */
  171 +# define OFFSET_STAT 0x08 /* Status Register */
  172 +# define OFFSET_SCR 0x0C /* SCR Scratch Register */
  173 +# define OFFSET_CLK 0x10 /* Clock Rate Register */
  174 +# define OFFSET_IER 0x14 /* Interrupt Enable Register */
  175 +# define OFFSET_IER_SET 0x18 /* Set Interrupt Enable Register */
  176 +# define OFFSET_IER_CLEAR 0x1C /* Clear Interrupt Enable Register */
  177 +# define OFFSET_RBR 0x20 /* Receive Buffer register */
  178 +# define OFFSET_THR 0x24 /* Transmit Holding register */
  179 +#elif defined(BFIN_UART_BF54X_STYLE)
113 180 # define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
114 181 # define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
115 182 # define OFFSET_GCTL 0x08 /* Global Control Register */
... ... @@ -145,7 +212,23 @@
145 212 */
146 213 #define __BFP(m) u16 m; u16 __pad_##m
147 214 struct bfin_uart_regs {
148   -#ifdef BFIN_UART_BF54X_STYLE
  215 +#if defined(BFIN_UART_BF60X_STYLE)
  216 + u32 revid;
  217 + u32 ctl;
  218 + u32 stat;
  219 + u32 scr;
  220 + u32 clk;
  221 + u32 ier;
  222 + u32 ier_set;
  223 + u32 ier_clear;
  224 + u32 rbr;
  225 + u32 thr;
  226 + u32 taip;
  227 + u32 tsr;
  228 + u32 rsr;
  229 + u32 txdiv;
  230 + u32 rxdiv;
  231 +#elif defined(BFIN_UART_BF54X_STYLE)
149 232 __BFP(dll);
150 233 __BFP(dlh);
151 234 __BFP(gctl);
152 235  
153 236  
154 237  
... ... @@ -182,13 +265,58 @@
182 265 };
183 266 #undef __BFP
184 267  
  268 +#define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase)
  269 +
  270 +/*
185 271 #ifndef port_membase
186 272 # define port_membase(p) 0
187 273 #endif
  274 +*/
  275 +#ifdef BFIN_UART_BF60X_STYLE
188 276  
  277 +#define UART_GET_CHAR(p) bfin_read32(port_membase(p) + OFFSET_RBR)
  278 +#define UART_GET_CLK(p) bfin_read32(port_membase(p) + OFFSET_CLK)
  279 +#define UART_GET_CTL(p) bfin_read32(port_membase(p) + OFFSET_CTL)
  280 +#define UART_GET_GCTL(p) UART_GET_CTL(p)
  281 +#define UART_GET_LCR(p) UART_GET_CTL(p)
  282 +#define UART_GET_MCR(p) UART_GET_CTL(p)
  283 +#define UART_GET_STAT(p) bfin_read32(port_membase(p) + OFFSET_STAT)
  284 +#define UART_GET_MSR(p) UART_GET_STAT(p)
  285 +
  286 +#define UART_PUT_CHAR(p, v) bfin_write32(port_membase(p) + OFFSET_THR, v)
  287 +#define UART_PUT_CLK(p, v) bfin_write32(port_membase(p) + OFFSET_CLK, v)
  288 +#define UART_PUT_CTL(p, v) bfin_write32(port_membase(p) + OFFSET_CTL, v)
  289 +#define UART_PUT_GCTL(p, v) UART_PUT_CTL(p, v)
  290 +#define UART_PUT_LCR(p, v) UART_PUT_CTL(p, v)
  291 +#define UART_PUT_MCR(p, v) UART_PUT_CTL(p, v)
  292 +#define UART_PUT_STAT(p, v) bfin_write32(port_membase(p) + OFFSET_STAT, v)
  293 +
  294 +#define UART_CLEAR_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_CLEAR, v)
  295 +#define UART_GET_IER(p) bfin_read32(port_membase(p) + OFFSET_IER)
  296 +#define UART_SET_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_SET, v)
  297 +
  298 +#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF60x */
  299 +#define UART_SET_DLAB(p) /* MMRs not muxed on BF60x */
  300 +
  301 +#define UART_CLEAR_LSR(p) UART_PUT_STAT(p, -1)
  302 +#define UART_GET_LSR(p) UART_GET_STAT(p)
  303 +#define UART_PUT_LSR(p, v) UART_PUT_STAT(p, v)
  304 +
  305 +/* This handles hard CTS/RTS */
  306 +#define BFIN_UART_CTSRTS_HARD
  307 +#define UART_CLEAR_SCTS(p) UART_PUT_STAT(p, SCTS)
  308 +#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
  309 +#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
  310 +#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
  311 +#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
  312 +#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
  313 +
  314 +#else /* BFIN_UART_BF60X_STYLE */
  315 +
189 316 #define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
190 317 #define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)
191 318 #define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)
  319 +#define UART_GET_CLK(p) ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p))
192 320 #define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL)
193 321 #define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR)
194 322 #define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR)
... ... @@ -197,6 +325,11 @@
197 325 #define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)
198 326 #define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)
199 327 #define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)
  328 +#define UART_PUT_CLK(p, v) do \
  329 +{\
  330 +UART_PUT_DLL(p, v & 0xFF); \
  331 +UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0);
  332 +
200 333 #define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)
201 334 #define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)
202 335 #define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)
203 336  
... ... @@ -233,12 +366,17 @@
233 366 #define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
234 367 #define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
235 368  
  369 +#define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr)
  370 +#define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v))
  371 +
  372 +/*
236 373 #ifndef put_lsr_cache
237 374 # define put_lsr_cache(p, v)
238 375 #endif
239 376 #ifndef get_lsr_cache
240 377 # define get_lsr_cache(p) 0
241 378 #endif
  379 +*/
242 380  
243 381 /* The hardware clears the LSR bits upon read, so we need to cache
244 382 * some of the more fun bits in software so they don't get lost
... ... @@ -267,7 +405,9 @@
267 405 #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
268 406 #define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
269 407  
270   -#endif
  408 +#endif /* BFIN_UART_BF54X_STYLE */
  409 +
  410 +#endif /* BFIN_UART_BF60X_STYLE */
271 411  
272 412 #ifndef BFIN_UART_TX_FIFO_SIZE
273 413 # define BFIN_UART_TX_FIFO_SIZE 2
arch/blackfin/include/asm/dma.h
Diff comments   View file @ b5affb0
... ... @@ -22,12 +22,22 @@
22 22 #define DATA_SIZE_8 0
23 23 #define DATA_SIZE_16 1
24 24 #define DATA_SIZE_32 2
  25 +#ifdef CONFIG_BF60x
  26 +#define DATA_SIZE_64 3
  27 +#endif
25 28  
26 29 #define DMA_FLOW_STOP 0
27 30 #define DMA_FLOW_AUTO 1
  31 +#ifdef CONFIG_BF60x
  32 +#define DMA_FLOW_LIST 4
  33 +#define DMA_FLOW_ARRAY 5
  34 +#define DMA_FLOW_LIST_DEMAND 6
  35 +#define DMA_FLOW_ARRAY_DEMAND 7
  36 +#else
28 37 #define DMA_FLOW_ARRAY 4
29 38 #define DMA_FLOW_SMALL 6
30 39 #define DMA_FLOW_LARGE 7
  40 +#endif
31 41  
32 42 #define DIMENSION_LINEAR 0
33 43 #define DIMENSION_2D 1
34 44  
35 45  
36 46  
37 47  
... ... @@ -36,26 +46,80 @@
36 46 #define DIR_WRITE 1
37 47  
38 48 #define INTR_DISABLE 0
  49 +#ifdef CONFIG_BF60x
  50 +#define INTR_ON_PERI 1
  51 +#endif
39 52 #define INTR_ON_BUF 2
40 53 #define INTR_ON_ROW 3
41 54  
42 55 #define DMA_NOSYNC_KEEP_DMA_BUF 0
43 56 #define DMA_SYNC_RESTART 1
44 57  
  58 +#ifdef DMA_MMR_SIZE_32
  59 +#define DMA_MMR_SIZE_TYPE long
  60 +#define DMA_MMR_READ bfin_read32
  61 +#define DMA_MMR_WRITE bfin_write32
  62 +#else
  63 +#define DMA_MMR_SIZE_TYPE short
  64 +#define DMA_MMR_READ bfin_read16
  65 +#define DMA_MMR_WRITE bfin_write16
  66 +#endif
  67 +
  68 +struct dma_desc_array {
  69 + unsigned long start_addr;
  70 + unsigned DMA_MMR_SIZE_TYPE cfg;
  71 + unsigned DMA_MMR_SIZE_TYPE x_count;
  72 + DMA_MMR_SIZE_TYPE x_modify;
  73 +} __attribute__((packed));
  74 +
45 75 struct dmasg {
46 76 void *next_desc_addr;
47 77 unsigned long start_addr;
48   - unsigned short cfg;
49   - unsigned short x_count;
50   - short x_modify;
51   - unsigned short y_count;
52   - short y_modify;
  78 + unsigned DMA_MMR_SIZE_TYPE cfg;
  79 + unsigned DMA_MMR_SIZE_TYPE x_count;
  80 + DMA_MMR_SIZE_TYPE x_modify;
  81 + unsigned DMA_MMR_SIZE_TYPE y_count;
  82 + DMA_MMR_SIZE_TYPE y_modify;
53 83 } __attribute__((packed));
54 84  
55 85 struct dma_register {
56 86 void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
57 87 unsigned long start_addr; /* DMA Start address register */
  88 +#ifdef CONFIG_BF60x
  89 + unsigned long cfg; /* DMA Configuration register */
58 90  
  91 + unsigned long x_count; /* DMA x_count register */
  92 +
  93 + long x_modify; /* DMA x_modify register */
  94 +
  95 + unsigned long y_count; /* DMA y_count register */
  96 +
  97 + long y_modify; /* DMA y_modify register */
  98 +
  99 + unsigned long reserved;
  100 + unsigned long reserved2;
  101 +
  102 + void *curr_desc_ptr; /* DMA Current Descriptor Pointer
  103 + register */
  104 + void *prev_desc_ptr; /* DMA previous initial Descriptor Pointer
  105 + register */
  106 + unsigned long curr_addr_ptr; /* DMA Current Address Pointer
  107 + register */
  108 + unsigned long irq_status; /* DMA irq status register */
  109 +
  110 + unsigned long curr_x_count; /* DMA Current x-count register */
  111 +
  112 + unsigned long curr_y_count; /* DMA Current y-count register */
  113 +
  114 + unsigned long reserved3;
  115 +
  116 + unsigned long bw_limit_count; /* DMA band width limit count register */
  117 + unsigned long curr_bw_limit_count; /* DMA Current band width limit
  118 + count register */
  119 + unsigned long bw_monitor_count; /* DMA band width limit count register */
  120 + unsigned long curr_bw_monitor_count; /* DMA Current band width limit
  121 + count register */
  122 +#else
59 123 unsigned short cfg; /* DMA Configuration register */
60 124 unsigned short dummy1; /* DMA Configuration register */
61 125  
... ... @@ -92,6 +156,7 @@
92 156 unsigned short dummy9;
93 157  
94 158 unsigned long reserved3;
  159 +#endif
95 160  
96 161 };
97 162  
98 163  
99 164  
100 165  
101 166  
... ... @@ -131,23 +196,23 @@
131 196 {
132 197 dma_ch[channel].regs->curr_desc_ptr = addr;
133 198 }
134   -static inline void set_dma_x_count(unsigned int channel, unsigned short x_count)
  199 +static inline void set_dma_x_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE x_count)
135 200 {
136 201 dma_ch[channel].regs->x_count = x_count;
137 202 }
138   -static inline void set_dma_y_count(unsigned int channel, unsigned short y_count)
  203 +static inline void set_dma_y_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE y_count)
139 204 {
140 205 dma_ch[channel].regs->y_count = y_count;
141 206 }
142   -static inline void set_dma_x_modify(unsigned int channel, short x_modify)
  207 +static inline void set_dma_x_modify(unsigned int channel, DMA_MMR_SIZE_TYPE x_modify)
143 208 {
144 209 dma_ch[channel].regs->x_modify = x_modify;
145 210 }
146   -static inline void set_dma_y_modify(unsigned int channel, short y_modify)
  211 +static inline void set_dma_y_modify(unsigned int channel, DMA_MMR_SIZE_TYPE y_modify)
147 212 {
148 213 dma_ch[channel].regs->y_modify = y_modify;
149 214 }
150   -static inline void set_dma_config(unsigned int channel, unsigned short config)
  215 +static inline void set_dma_config(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE config)
151 216 {
152 217 dma_ch[channel].regs->cfg = config;
153 218 }
154 219  
155 220  
156 221  
157 222  
158 223  
159 224  
... ... @@ -156,23 +221,55 @@
156 221 dma_ch[channel].regs->curr_addr_ptr = addr;
157 222 }
158 223  
159   -static inline unsigned short
  224 +#ifdef CONFIG_BF60x
  225 +static inline unsigned long
  226 +set_bfin_dma_config2(char direction, char flow_mode, char intr_mode,
  227 + char dma_mode, char mem_width, char syncmode, char peri_width)
  228 +{
  229 + unsigned long config = 0;
  230 +
  231 + switch (intr_mode) {
  232 + case INTR_ON_BUF:
  233 + if (dma_mode == DIMENSION_2D)
  234 + config = DI_EN_Y;
  235 + else
  236 + config = DI_EN_X;
  237 + break;
  238 + case INTR_ON_ROW:
  239 + config = DI_EN_X;
  240 + break;
  241 + case INTR_ON_PERI:
  242 + config = DI_EN_P;
  243 + break;
  244 + };
  245 +
  246 + return config | (direction << 1) | (mem_width << 8) | (dma_mode << 26) |
  247 + (flow_mode << 12) | (syncmode << 2) | (peri_width << 4);
  248 +}
  249 +#endif
  250 +
  251 +static inline unsigned DMA_MMR_SIZE_TYPE
160 252 set_bfin_dma_config(char direction, char flow_mode,
161   - char intr_mode, char dma_mode, char width, char syncmode)
  253 + char intr_mode, char dma_mode, char mem_width, char syncmode)
162 254 {
163   - return (direction << 1) | (width << 2) | (dma_mode << 4) |
  255 +#ifdef CONFIG_BF60x
  256 + return set_bfin_dma_config2(direction, flow_mode, intr_mode, dma_mode,
  257 + mem_width, syncmode, mem_width);
  258 +#else
  259 + return (direction << 1) | (mem_width << 2) | (dma_mode << 4) |
164 260 (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5);
  261 +#endif
165 262 }
166 263  
167   -static inline unsigned short get_dma_curr_irqstat(unsigned int channel)
  264 +static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_irqstat(unsigned int channel)
168 265 {
169 266 return dma_ch[channel].regs->irq_status;
170 267 }
171   -static inline unsigned short get_dma_curr_xcount(unsigned int channel)
  268 +static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_xcount(unsigned int channel)
172 269 {
173 270 return dma_ch[channel].regs->curr_x_count;
174 271 }
175   -static inline unsigned short get_dma_curr_ycount(unsigned int channel)
  272 +static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_ycount(unsigned int channel)
176 273 {
177 274 return dma_ch[channel].regs->curr_y_count;
178 275 }
... ... @@ -184,7 +281,7 @@
184 281 {
185 282 return dma_ch[channel].regs->curr_desc_ptr;
186 283 }
187   -static inline unsigned short get_dma_config(unsigned int channel)
  284 +static inline unsigned DMA_MMR_SIZE_TYPE get_dma_config(unsigned int channel)
188 285 {
189 286 return dma_ch[channel].regs->cfg;
190 287 }
... ... @@ -203,8 +300,8 @@
203 300  
204 301 dma_ch[channel].regs->next_desc_ptr = sg;
205 302 dma_ch[channel].regs->cfg =
206   - (dma_ch[channel].regs->cfg & ~(0xf << 8)) |
207   - ((ndsize & 0xf) << 8);
  303 + (dma_ch[channel].regs->cfg & ~NDSIZE) |
  304 + ((ndsize << NDSIZE_OFFSET) & NDSIZE);
208 305 }
209 306  
210 307 static inline int dma_channel_active(unsigned int channel)
... ... @@ -239,7 +336,7 @@
239 336 }
240 337 static inline void clear_dma_irqstat(unsigned int channel)
241 338 {
242   - dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR;
  339 + dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR | DMA_PIRQ;
243 340 }
244 341  
245 342 void *dma_memcpy(void *dest, const void *src, size_t count);
arch/blackfin/include/asm/fixed_code.h
Diff comments   View file @ b5affb0
... ... @@ -29,25 +29,29 @@
29 29 #endif
30 30 #endif
31 31  
32   -#define FIXED_CODE_START 0x400
  32 +#ifndef CONFIG_PHY_RAM_BASE_ADDRESS
  33 +#define CONFIG_PHY_RAM_BASE_ADDRESS 0x0
  34 +#endif
33 35  
34   -#define SIGRETURN_STUB 0x400
  36 +#define FIXED_CODE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
35 37  
36   -#define ATOMIC_SEQS_START 0x410
  38 +#define SIGRETURN_STUB (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
37 39  
38   -#define ATOMIC_XCHG32 0x410
39   -#define ATOMIC_CAS32 0x420
40   -#define ATOMIC_ADD32 0x430
41   -#define ATOMIC_SUB32 0x440
42   -#define ATOMIC_IOR32 0x450
43   -#define ATOMIC_AND32 0x460
44   -#define ATOMIC_XOR32 0x470
  40 +#define ATOMIC_SEQS_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
45 41  
46   -#define ATOMIC_SEQS_END 0x480
  42 +#define ATOMIC_XCHG32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
  43 +#define ATOMIC_CAS32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x420)
  44 +#define ATOMIC_ADD32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x430)
  45 +#define ATOMIC_SUB32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x440)
  46 +#define ATOMIC_IOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x450)
  47 +#define ATOMIC_AND32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x460)
  48 +#define ATOMIC_XOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x470)
47 49  
48   -#define SAFE_USER_INSTRUCTION 0x480
  50 +#define ATOMIC_SEQS_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
49 51  
50   -#define FIXED_CODE_END 0x490
  52 +#define SAFE_USER_INSTRUCTION (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
  53 +
  54 +#define FIXED_CODE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x490)
51 55  
52 56 #endif
arch/blackfin/include/asm/page.h
Diff comments   View file @ b5affb0
... ... @@ -7,14 +7,15 @@
7 7 #ifndef _BLACKFIN_PAGE_H
8 8 #define _BLACKFIN_PAGE_H
9 9  
10   -#include <asm-generic/page.h>
11   -#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)
  10 +#define ARCH_PFN_OFFSET (CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT)
  11 +#define MAP_NR(addr) ((unsigned long)(addr) >> PAGE_SHIFT)
12 12  
13 13 #define VM_DATA_DEFAULT_FLAGS \
14 14 (VM_READ | VM_WRITE | \
15 15 ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \
16 16 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
17 17  
  18 +#include <asm-generic/page.h>
18 19 #include <asm-generic/memory_model.h>
19 20 #include <asm-generic/getorder.h>
20 21  
arch/blackfin/kernel/bfin_dma.c
Diff comments   View file @ b5affb0
... ... @@ -45,9 +45,15 @@
45 45 atomic_set(&dma_ch[i].chan_status, 0);
46 46 dma_ch[i].regs = dma_io_base_addr[i];
47 47 }
  48 +#ifdef CH_MEM_STREAM3_SRC
  49 + /* Mark MEMDMA Channel 3 as requested since we're using it internally */
  50 + request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy");
  51 + request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy");
  52 +#else
48 53 /* Mark MEMDMA Channel 0 as requested since we're using it internally */
49 54 request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy");
50 55 request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy");
  56 +#endif
51 57  
52 58 #if defined(CONFIG_DEB_DMA_URGENT)
53 59 bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE()
... ... @@ -204,6 +210,7 @@
204 210 # ifndef MAX_DMA_SUSPEND_CHANNELS
205 211 # define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS
206 212 # endif
  213 +# ifndef CONFIG_BF60x
207 214 int blackfin_dma_suspend(void)
208 215 {
209 216 int i;
... ... @@ -213,7 +220,6 @@
213 220 printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
214 221 return -EBUSY;
215 222 }
216   -
217 223 if (i < MAX_DMA_SUSPEND_CHANNELS)
218 224 dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
219 225 }
... ... @@ -230,7 +236,6 @@
230 236  
231 237 for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
232 238 dma_ch[i].regs->cfg = 0;
233   -
234 239 if (i < MAX_DMA_SUSPEND_CHANNELS)
235 240 dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
236 241 }
237 242  
... ... @@ -238,7 +243,17 @@
238 243 bfin_write_DMAC_TC_PER(0x0111);
239 244 #endif
240 245 }
  246 +# else
  247 +int blackfin_dma_suspend(void)
  248 +{
  249 + return 0;
  250 +}
  251 +
  252 +void blackfin_dma_resume(void)
  253 +{
  254 +}
241 255 #endif
  256 +#endif
242 257  
243 258 /**
244 259 * blackfin_dma_early_init - minimal DMA init
245 260  
... ... @@ -279,10 +294,10 @@
279 294 src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
280 295 }
281 296  
282   - if (!bfin_read16(&src_ch->cfg))
  297 + if (!DMA_MMR_READ(&src_ch->cfg))
283 298 break;
284   - else if (bfin_read16(&dst_ch->irq_status) & DMA_DONE) {
285   - bfin_write16(&src_ch->cfg, 0);
  299 + else if (DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE) {
  300 + DMA_MMR_WRITE(&src_ch->cfg, 0);
286 301 break;
287 302 }
288 303 }
289 304  
290 305  
291 306  
... ... @@ -295,22 +310,31 @@
295 310  
296 311 /* Destination */
297 312 bfin_write32(&dst_ch->start_addr, dst);
298   - bfin_write16(&dst_ch->x_count, size >> 2);
299   - bfin_write16(&dst_ch->x_modify, 1 << 2);
300   - bfin_write16(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
  313 + DMA_MMR_WRITE(&dst_ch->x_count, size >> 2);
  314 + DMA_MMR_WRITE(&dst_ch->x_modify, 1 << 2);
  315 + DMA_MMR_WRITE(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
301 316  
302 317 /* Source */
303 318 bfin_write32(&src_ch->start_addr, src);
304   - bfin_write16(&src_ch->x_count, size >> 2);
305   - bfin_write16(&src_ch->x_modify, 1 << 2);
306   - bfin_write16(&src_ch->irq_status, DMA_DONE | DMA_ERR);
  319 + DMA_MMR_WRITE(&src_ch->x_count, size >> 2);
  320 + DMA_MMR_WRITE(&src_ch->x_modify, 1 << 2);
  321 + DMA_MMR_WRITE(&src_ch->irq_status, DMA_DONE | DMA_ERR);
307 322  
308 323 /* Enable */
309   - bfin_write16(&src_ch->cfg, DMAEN | WDSIZE_32);
310   - bfin_write16(&dst_ch->cfg, WNR | DI_EN | DMAEN | WDSIZE_32);
  324 + DMA_MMR_WRITE(&src_ch->cfg, DMAEN | WDSIZE_32);
  325 + DMA_MMR_WRITE(&dst_ch->cfg, WNR | DI_EN_X | DMAEN | WDSIZE_32);
311 326  
312 327 /* Since we are atomic now, don't use the workaround ssync */
313 328 __builtin_bfin_ssync();
  329 +
  330 +#ifdef CONFIG_BF60x
  331 + /* Work around a possible MDMA anomaly. Running 2 MDMA channels to
  332 + * transfer DDR data to L1 SRAM may corrupt data.
  333 + * Should be reverted after this issue is root caused.
  334 + */
  335 + while (!(DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE))
  336 + continue;
  337 +#endif
314 338 }
315 339  
316 340 void __init early_dma_memcpy_done(void)
... ... @@ -336,6 +360,42 @@
336 360 __builtin_bfin_ssync();
337 361 }
338 362  
  363 +#ifdef CH_MEM_STREAM3_SRC
  364 +#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG
  365 +#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG
  366 +#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR
  367 +#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S3_IRQ_STATUS
  368 +#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S3_X_COUNT
  369 +#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S3_X_MODIFY
  370 +#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S3_Y_COUNT
  371 +#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S3_Y_MODIFY
  372 +#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D3_CONFIG
  373 +#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D3_START_ADDR
  374 +#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D3_IRQ_STATUS
  375 +#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D3_IRQ_STATUS
  376 +#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D3_X_COUNT
  377 +#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D3_X_MODIFY
  378 +#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D3_Y_COUNT
  379 +#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D3_Y_MODIFY
  380 +#else
  381 +#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S0_CONFIG
  382 +#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S0_CONFIG
  383 +#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S0_START_ADDR
  384 +#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S0_IRQ_STATUS
  385 +#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S0_X_COUNT
  386 +#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S0_X_MODIFY
  387 +#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S0_Y_COUNT
  388 +#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S0_Y_MODIFY
  389 +#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D0_CONFIG
  390 +#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D0_START_ADDR
  391 +#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D0_IRQ_STATUS
  392 +#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D0_IRQ_STATUS
  393 +#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D0_X_COUNT
  394 +#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D0_X_MODIFY
  395 +#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D0_Y_COUNT
  396 +#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D0_Y_MODIFY
  397 +#endif
  398 +
339 399 /**
340 400 * __dma_memcpy - program the MDMA registers
341 401 *
... ... @@ -358,8 +418,8 @@
358 418 */
359 419 __builtin_bfin_ssync();
360 420  
361   - if (bfin_read_MDMA_S0_CONFIG())
362   - while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
  421 + if (bfin_read_MDMA_S_CONFIG())
  422 + while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
363 423 continue;
364 424  
365 425 if (conf & DMA2D) {
366 426  
367 427  
368 428  
369 429  
370 430  
371 431  
... ... @@ -374,39 +434,42 @@
374 434 u32 shift = abs(dmod) >> 1;
375 435 size_t ycnt = cnt >> (16 - shift);
376 436 cnt = 1 << (16 - shift);
377   - bfin_write_MDMA_D0_Y_COUNT(ycnt);
378   - bfin_write_MDMA_S0_Y_COUNT(ycnt);
379   - bfin_write_MDMA_D0_Y_MODIFY(dmod);
380   - bfin_write_MDMA_S0_Y_MODIFY(smod);
  437 + bfin_write_MDMA_D_Y_COUNT(ycnt);
  438 + bfin_write_MDMA_S_Y_COUNT(ycnt);
  439 + bfin_write_MDMA_D_Y_MODIFY(dmod);
  440 + bfin_write_MDMA_S_Y_MODIFY(smod);
381 441 }
382 442  
383   - bfin_write_MDMA_D0_START_ADDR(daddr);
384   - bfin_write_MDMA_D0_X_COUNT(cnt);
385   - bfin_write_MDMA_D0_X_MODIFY(dmod);
386   - bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  443 + bfin_write_MDMA_D_START_ADDR(daddr);
  444 + bfin_write_MDMA_D_X_COUNT(cnt);
  445 + bfin_write_MDMA_D_X_MODIFY(dmod);
  446 + bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
387 447  
388   - bfin_write_MDMA_S0_START_ADDR(saddr);
389   - bfin_write_MDMA_S0_X_COUNT(cnt);
390   - bfin_write_MDMA_S0_X_MODIFY(smod);
391   - bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  448 + bfin_write_MDMA_S_START_ADDR(saddr);
  449 + bfin_write_MDMA_S_X_COUNT(cnt);
  450 + bfin_write_MDMA_S_X_MODIFY(smod);
  451 + bfin_write_MDMA_S_IRQ_STATUS(DMA_DONE | DMA_ERR);
392 452  
393   - bfin_write_MDMA_S0_CONFIG(DMAEN | conf);
394   - bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | conf);
  453 + bfin_write_MDMA_S_CONFIG(DMAEN | conf);
  454 + if (conf & DMA2D)
  455 + bfin_write_MDMA_D_CONFIG(WNR | DI_EN_Y | DMAEN | conf);
  456 + else
  457 + bfin_write_MDMA_D_CONFIG(WNR | DI_EN_X | DMAEN | conf);
395 458  
396 459 spin_unlock_irqrestore(&mdma_lock, flags);
397 460  
398 461 SSYNC();
399 462  
400   - while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
401   - if (bfin_read_MDMA_S0_CONFIG())
  463 + while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
  464 + if (bfin_read_MDMA_S_CONFIG())
402 465 continue;
403 466 else
404 467 return;
405 468  
406   - bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  469 + bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
407 470  
408   - bfin_write_MDMA_S0_CONFIG(0);
409   - bfin_write_MDMA_D0_CONFIG(0);
  471 + bfin_write_MDMA_S_CONFIG(0);
  472 + bfin_write_MDMA_D_CONFIG(0);
410 473 }
411 474  
412 475 /**
413 476  
... ... @@ -448,8 +511,10 @@
448 511 }
449 512 size >>= shift;
450 513  
  514 +#ifndef DMA_MMR_SIZE_32
451 515 if (size > 0x10000)
452 516 conf |= DMA2D;
  517 +#endif
453 518  
454 519 __dma_memcpy(dst, mod, src, mod, size, conf);
455 520  
... ... @@ -488,6 +553,9 @@
488 553 */
489 554 void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
490 555 {
  556 +#ifdef DMA_MMR_SIZE_32
  557 + _dma_memcpy(pdst, psrc, size);
  558 +#else
491 559 size_t bulk, rest;
492 560  
493 561 bulk = size & ~0xffff;
... ... @@ -495,6 +563,7 @@
495 563 if (bulk)
496 564 _dma_memcpy(pdst, psrc, bulk);
497 565 _dma_memcpy(pdst + bulk, psrc + bulk, rest);
  566 +#endif
498 567 return pdst;
499 568 }
500 569 EXPORT_SYMBOL(dma_memcpy_nocache);
501 570  
... ... @@ -514,14 +583,14 @@
514 583 }
515 584 EXPORT_SYMBOL(safe_dma_memcpy);
516 585  
517   -static void _dma_out(unsigned long addr, unsigned long buf, unsigned short len,
  586 +static void _dma_out(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
518 587 u16 size, u16 dma_size)
519 588 {
520 589 blackfin_dcache_flush_range(buf, buf + len * size);
521 590 __dma_memcpy(addr, 0, buf, size, len, dma_size);
522 591 }
523 592  
524   -static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len,
  593 +static void _dma_in(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
525 594 u16 size, u16 dma_size)
526 595 {
527 596 blackfin_dcache_invalidate_range(buf, buf + len * size);
... ... @@ -529,7 +598,7 @@
529 598 }
530 599  
531 600 #define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \
532   -void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned short len) \
  601 +void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned DMA_MMR_SIZE_TYPE len) \
533 602 { \
534 603 _dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \
535 604 } \
arch/blackfin/kernel/bfin_gpio.c
Diff comments   View file @ b5affb0
... ... @@ -58,7 +58,7 @@
58 58 (struct gpio_port_t *) FIO0_FLAG_D,
59 59 (struct gpio_port_t *) FIO1_FLAG_D,
60 60 (struct gpio_port_t *) FIO2_FLAG_D,
61   -#elif defined(CONFIG_BF54x)
  61 +#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
62 62 (struct gpio_port_t *)PORTA_FER,
63 63 (struct gpio_port_t *)PORTB_FER,
64 64 (struct gpio_port_t *)PORTC_FER,
... ... @@ -66,6 +66,7 @@
66 66 (struct gpio_port_t *)PORTE_FER,
67 67 (struct gpio_port_t *)PORTF_FER,
68 68 (struct gpio_port_t *)PORTG_FER,
  69 +#elif defined(CONFIG_BF54x)
69 70 (struct gpio_port_t *)PORTH_FER,
70 71 (struct gpio_port_t *)PORTI_FER,
71 72 (struct gpio_port_t *)PORTJ_FER,
... ... @@ -210,7 +211,7 @@
210 211 else
211 212 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
212 213 SSYNC();
213   -#elif defined(CONFIG_BF54x)
  214 +#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
214 215 if (usage == GPIO_USAGE)
215 216 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
216 217 else
... ... @@ -299,7 +300,7 @@
299 300 pmux |= (function << offset);
300 301 bfin_write_PORT_MUX(pmux);
301 302 }
302   -#elif defined(CONFIG_BF54x)
  303 +#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
303 304 inline void portmux_setup(unsigned short per)
304 305 {
305 306 u16 ident = P_IDENT(per);
... ... @@ -377,7 +378,7 @@
377 378 }
378 379 #endif
379 380  
380   -#ifndef CONFIG_BF54x
  381 +#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
381 382 /***********************************************************
382 383 *
383 384 * FUNCTIONS: Blackfin General Purpose Ports Access Functions
... ... @@ -680,7 +681,7 @@
680 681  
681 682  
682 683 #endif
683   -#else /* CONFIG_BF54x */
  684 +#else /* CONFIG_BF54x || CONFIG_BF60x */
684 685 #ifdef CONFIG_PM
685 686  
686 687 int bfin_pm_standby_ctrl(unsigned ctrl)
... ... @@ -726,7 +727,7 @@
726 727 }
727 728 EXPORT_SYMBOL(get_gpio_dir);
728 729  
729   -#endif /* CONFIG_BF54x */
  730 +#endif /* CONFIG_BF54x || CONFIG_BF60x */
730 731  
731 732 /***********************************************************
732 733 *
... ... @@ -783,7 +784,7 @@
783 784 * be requested and used by several drivers
784 785 */
785 786  
786   -#ifdef CONFIG_BF54x
  787 +#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
787 788 if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
788 789 #else
789 790 if (!(per & P_MAYSHARE)) {
... ... @@ -937,7 +938,7 @@
937 938 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
938 939 " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
939 940 }
940   -#ifndef CONFIG_BF54x
  941 +#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
941 942 else { /* Reset POLAR setting when acquiring a gpio for the first time */
942 943 set_gpio_polar(gpio, 0);
943 944 }
... ... @@ -1110,7 +1111,7 @@
1110 1111  
1111 1112 static inline void __bfin_gpio_direction_input(unsigned gpio)
1112 1113 {
1113   -#ifdef CONFIG_BF54x
  1114 +#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1114 1115 gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
1115 1116 #else
1116 1117 gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
1117 1118  
... ... @@ -1138,13 +1139,13 @@
1138 1139  
1139 1140 void bfin_gpio_irq_prepare(unsigned gpio)
1140 1141 {
1141   -#ifdef CONFIG_BF54x
  1142 +#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1142 1143 unsigned long flags;
1143 1144 #endif
1144 1145  
1145 1146 port_setup(gpio, GPIO_USAGE);
1146 1147  
1147   -#ifdef CONFIG_BF54x
  1148 +#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1148 1149 flags = hard_local_irq_save();
1149 1150 __bfin_gpio_direction_input(gpio);
1150 1151 hard_local_irq_restore(flags);
... ... @@ -1173,7 +1174,7 @@
1173 1174  
1174 1175 gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
1175 1176 gpio_set_value(gpio, value);
1176   -#ifdef CONFIG_BF54x
  1177 +#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1177 1178 gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
1178 1179 #else
1179 1180 gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
... ... @@ -1188,7 +1189,7 @@
1188 1189  
1189 1190 int bfin_gpio_get_value(unsigned gpio)
1190 1191 {
1191   -#ifdef CONFIG_BF54x
  1192 +#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1192 1193 return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
1193 1194 #else
1194 1195 unsigned long flags;
arch/blackfin/kernel/debug-mmrs.c
Diff comments   View file @ b5affb0
... ... @@ -105,6 +105,7 @@
105 105 DEFINE_SYSREG(syscfg, , CSYNC());
106 106 #define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
107 107  
  108 +#ifndef CONFIG_BF60x
108 109 /*
109 110 * CAN
110 111 */
111 112  
... ... @@ -223,8 +224,10 @@
223 224 __DMA(CURR_DESC_PTR, curr_desc_ptr);
224 225 __DMA(CURR_ADDR, curr_addr);
225 226 __DMA(IRQ_STATUS, irq_status);
  227 +#ifndef CONFIG_BF60x
226 228 if (strcmp(pfx, "IMDMA") != 0)
227 229 __DMA(PERIPHERAL_MAP, peripheral_map);
  230 +#endif
228 231 __DMA(CURR_X_COUNT, curr_x_count);
229 232 __DMA(CURR_Y_COUNT, curr_y_count);
230 233 }
... ... @@ -568,7 +571,7 @@
568 571 #endif
569 572 }
570 573 #define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
571   -
  574 +#endif /* CONFIG_BF60x */
572 575 /*
573 576 * The actual debugfs generation
574 577 */
... ... @@ -740,7 +743,7 @@
740 743 D32(WPDACNT0);
741 744 D32(WPDACNT1);
742 745 D32(WPSTAT);
743   -
  746 +#ifndef CONFIG_BF60x
744 747 /* System MMRs */
745 748 #ifdef ATAPI_CONTROL
746 749 parent = debugfs_create_dir("atapi", top);
... ... @@ -1873,7 +1876,7 @@
1873 1876  
1874 1877 }
1875 1878 #endif /* BF54x */
1876   -
  1879 +#endif /* CONFIG_BF60x */
1877 1880 debug_mmrs_dentry = top;
1878 1881  
1879 1882 return 0;
arch/blackfin/kernel/process.c
Diff comments   View file @ b5affb0
... ... @@ -95,7 +95,9 @@
95 95 idle();
96 96 rcu_idle_exit();
97 97 tick_nohz_idle_exit();
98   - schedule_preempt_disabled();
  98 + preempt_enable_no_resched();
  99 + schedule();
  100 + preempt_disable();
99 101 }
100 102 }
101 103  
102 104  
... ... @@ -329,12 +331,16 @@
329 331 {
330 332 return in_mem_const_off(addr, size, 0, const_addr, const_size);
331 333 }
  334 +#ifdef CONFIG_BF60x
  335 +#define ASYNC_ENABLED(bnum, bctlnum) 1
  336 +#else
332 337 #define ASYNC_ENABLED(bnum, bctlnum) \
333 338 ({ \
334 339 (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
335 340 bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
336 341 1; \
337 342 })
  343 +#endif
338 344 /*
339 345 * We can't read EBIU banks that aren't enabled or we end up hanging
340 346 * on the access to the async space. Make sure we validate accesses
arch/blackfin/kernel/reboot.c
Diff comments   View file @ b5affb0
... ... @@ -22,6 +22,7 @@
22 22 __attribute__ ((__l1_text__, __noreturn__))
23 23 static void bfin_reset(void)
24 24 {
  25 +#ifndef CONFIG_BF60x
25 26 if (!ANOMALY_05000353 && !ANOMALY_05000386)
26 27 bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
27 28  
... ... @@ -57,7 +58,6 @@
57 58 if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
58 59 bfin_read_SWRST();
59 60 #endif
60   -
61 61 /* Wait for the SWRST write to complete. Cannot rely on SSYNC
62 62 * though as the System state is all reset now.
63 63 */
... ... @@ -72,6 +72,10 @@
72 72 while (1)
73 73 /* Issue core reset */
74 74 asm("raise 1");
  75 +#else
  76 + while (1)
  77 + bfin_write_RCU0_CTL(0x1);
  78 +#endif
75 79 }
76 80  
77 81 __attribute__((weak))
arch/blackfin/kernel/setup.c
Diff comments   View file @ b5affb0
... ... @@ -25,6 +25,7 @@
25 25 #include <asm/cacheflush.h>
26 26 #include <asm/blackfin.h>
27 27 #include <asm/cplbinit.h>
  28 +#include <asm/clocks.h>
28 29 #include <asm/div64.h>
29 30 #include <asm/cpu.h>
30 31 #include <asm/fixed_code.h>
... ... @@ -550,7 +551,6 @@
550 551 {
551 552 #ifdef CONFIG_MTD_UCLINUX
552 553 unsigned long mtd_phys = 0;
553   - unsigned long n;
554 554 #endif
555 555 unsigned long max_mem;
556 556  
... ... @@ -594,9 +594,9 @@
594 594 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
595 595  
596 596 # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
597   - n = ext2_image_size((void *)(mtd_phys + 0x400));
598   - if (n)
599   - mtd_size = PAGE_ALIGN(n * 1024);
  597 + if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
  598 + mtd_size =
  599 + PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
600 600 # endif
601 601  
602 602 # if defined(CONFIG_CRAMFS)
... ... @@ -612,7 +612,8 @@
612 612  
613 613 /* ROM_FS is XIP, so if we found it, we need to limit memory */
614 614 if (memory_end > max_mem) {
615   - pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20);
  615 + pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
  616 + (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
616 617 memory_end = max_mem;
617 618 }
618 619 }
... ... @@ -642,7 +643,8 @@
642 643 * doesn't exist, or we don't need to - then dont.
643 644 */
644 645 if (memory_end > max_mem) {
645   - pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20);
  646 + pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
  647 + (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
646 648 memory_end = max_mem;
647 649 }
648 650  
... ... @@ -661,8 +663,8 @@
661 663 init_mm.end_data = (unsigned long)_edata;
662 664 init_mm.brk = (unsigned long)0;
663 665  
664   - printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
665   - printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
  666 + printk(KERN_INFO "Board Memory: %ldMB\n", (physical_mem_end - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
  667 + printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
666 668  
667 669 printk(KERN_INFO "Memory map:\n"
668 670 " fixedcode = 0x%p-0x%p\n"
... ... @@ -705,7 +707,7 @@
705 707 int i;
706 708  
707 709 max_pfn = 0;
708   - min_low_pfn = memory_end;
  710 + min_low_pfn = PFN_DOWN(memory_end);
709 711  
710 712 for (i = 0; i < bfin_memmap.nr_map; i++) {
711 713 unsigned long start, end;
... ... @@ -748,8 +750,7 @@
748 750 /* pfn of the first usable page frame after kernel image*/
749 751 if (min_low_pfn < memory_start >> PAGE_SHIFT)
750 752 min_low_pfn = memory_start >> PAGE_SHIFT;
751   -
752   - start_pfn = PAGE_OFFSET >> PAGE_SHIFT;
  753 + start_pfn = CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT;
753 754 end_pfn = memory_end >> PAGE_SHIFT;
754 755  
755 756 /*
... ... @@ -794,8 +795,8 @@
794 795 }
795 796  
796 797 /* reserve memory before memory_start, including bootmap */
797   - reserve_bootmem(PAGE_OFFSET,
798   - memory_start + bootmap_size + PAGE_SIZE - 1 - PAGE_OFFSET,
  798 + reserve_bootmem(CONFIG_PHY_RAM_BASE_ADDRESS,
  799 + memory_start + bootmap_size + PAGE_SIZE - 1 - CONFIG_PHY_RAM_BASE_ADDRESS,
799 800 BOOTMEM_DEFAULT);
800 801 }
801 802  
802 803  
... ... @@ -844,13 +845,40 @@
844 845 break;
845 846 }
846 847 switch (ddrctl & 0x30000) {
847   - case DEVWD_4: ret *= 2;
848   - case DEVWD_8: ret *= 2;
849   - case DEVWD_16: break;
  848 + case DEVWD_4:
  849 + ret *= 2;
  850 + case DEVWD_8:
  851 + ret *= 2;
  852 + case DEVWD_16:
  853 + break;
850 854 }
851 855 if ((ddrctl & 0xc000) == 0x4000)
852 856 ret *= 2;
853 857 return ret;
  858 +#elif defined(CONFIG_BF60x)
  859 + u32 ddrctl = bfin_read_DDR0_CFG();
  860 + int ret;
  861 + switch (ddrctl & 0xf00) {
  862 + case DEVSZ_64:
  863 + ret = 64 / 8;
  864 + break;
  865 + case DEVSZ_128:
  866 + ret = 128 / 8;
  867 + break;
  868 + case DEVSZ_256:
  869 + ret = 256 / 8;
  870 + break;
  871 + case DEVSZ_512:
  872 + ret = 512 / 8;
  873 + break;
  874 + case DEVSZ_1G:
  875 + ret = 1024 / 8;
  876 + break;
  877 + case DEVSZ_2G:
  878 + ret = 2048 / 8;
  879 + break;
  880 + }
  881 + return ret;
854 882 #endif
855 883 BUG();
856 884 }
857 885  
... ... @@ -864,12 +892,14 @@
864 892 {
865 893 u32 mmr;
866 894 unsigned long sclk, cclk;
  895 + struct clk *clk;
867 896  
868 897 native_machine_early_platform_add_devices();
869 898  
870 899 enable_shadow_console();
871 900  
872 901 /* Check to make sure we are running on the right processor */
  902 + mmr = bfin_cpuid();
873 903 if (unlikely(CPUID != bfin_cpuid()))
874 904 printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
875 905 CPU, bfin_cpuid(), bfin_revid());
... ... @@ -890,6 +920,10 @@
890 920  
891 921 memset(&bfin_memmap, 0, sizeof(bfin_memmap));
892 922  
  923 +#ifdef CONFIG_BF60x
  924 + /* Should init clock device before parse command early */
  925 + clk_init();
  926 +#endif
893 927 /* If the user does not specify things on the command line, use
894 928 * what the bootloader set things up as
895 929 */
... ... @@ -904,6 +938,7 @@
904 938  
905 939 memory_setup();
906 940  
  941 +#ifndef CONFIG_BF60x
907 942 /* Initialize Async memory banks */
908 943 bfin_write_EBIU_AMBCTL0(AMBCTL0VAL);
909 944 bfin_write_EBIU_AMBCTL1(AMBCTL1VAL);
... ... @@ -913,6 +948,7 @@
913 948 bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
914 949 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
915 950 #endif
  951 +#endif
916 952 #ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
917 953 bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15);
918 954 bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15);
919 955  
... ... @@ -921,8 +957,24 @@
921 957 ~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
922 958 #endif
923 959  
  960 +#ifdef CONFIG_BF60x
  961 + clk = clk_get(NULL, "CCLK");
  962 + if (!IS_ERR(clk)) {
  963 + cclk = clk_get_rate(clk);
  964 + clk_put(clk);
  965 + } else
  966 + cclk = 0;
  967 +
  968 + clk = clk_get(NULL, "SCLK0");
  969 + if (!IS_ERR(clk)) {
  970 + sclk = clk_get_rate(clk);
  971 + clk_put(clk);
  972 + } else
  973 + sclk = 0;
  974 +#else
924 975 cclk = get_cclk();
925 976 sclk = get_sclk();
  977 +#endif
926 978  
927 979 if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk)
928 980 panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK");
... ... @@ -938,7 +990,7 @@
938 990 printk(KERN_INFO "Hardware Trace %s and %sabled\n",
939 991 (mmr & 0x1) ? "active" : "off",
940 992 (mmr & 0x2) ? "en" : "dis");
941   -
  993 +#ifndef CONFIG_BF60x
942 994 mmr = bfin_read_SYSCR();
943 995 printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF);
944 996  
... ... @@ -980,7 +1032,7 @@
980 1032 printk(KERN_INFO "Recovering from Watchdog event\n");
981 1033 else if (_bfin_swrst & RESET_SOFTWARE)
982 1034 printk(KERN_NOTICE "Reset caused by Software reset\n");
983   -
  1035 +#endif
984 1036 printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n");
985 1037 if (bfin_compiled_revid() == 0xffff)
986 1038 printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid());
987 1039  
... ... @@ -1060,10 +1112,12 @@
1060 1112  
1061 1113 /* Get the input clock frequency */
1062 1114 static u_long cached_clkin_hz = CONFIG_CLKIN_HZ;
  1115 +#ifndef CONFIG_BF60x
1063 1116 static u_long get_clkin_hz(void)
1064 1117 {
1065 1118 return cached_clkin_hz;
1066 1119 }
  1120 +#endif
1067 1121 static int __init early_init_clkin_hz(char *buf)
1068 1122 {
1069 1123 cached_clkin_hz = simple_strtoul(buf, NULL, 0);
... ... @@ -1075,6 +1129,7 @@
1075 1129 }
1076 1130 early_param("clkin_hz=", early_init_clkin_hz);
1077 1131  
  1132 +#ifndef CONFIG_BF60x
1078 1133 /* Get the voltage input multiplier */
1079 1134 static u_long get_vco(void)
1080 1135 {
1081 1136  
... ... @@ -1097,10 +1152,23 @@
1097 1152 cached_vco *= msel;
1098 1153 return cached_vco;
1099 1154 }
  1155 +#endif
1100 1156  
1101 1157 /* Get the Core clock */
1102 1158 u_long get_cclk(void)
1103 1159 {
  1160 +#ifdef CONFIG_BF60x
  1161 + struct clk *cclk;
  1162 + u_long cclk_rate;
  1163 +
  1164 + cclk = clk_get(NULL, "CCLK");
  1165 + if (IS_ERR(cclk))
  1166 + return 0;
  1167 +
  1168 + cclk_rate = clk_get_rate(cclk);
  1169 + clk_put(cclk);
  1170 + return cclk_rate;
  1171 +#else
1104 1172 static u_long cached_cclk_pll_div, cached_cclk;
1105 1173 u_long csel, ssel;
1106 1174  
1107 1175  
1108 1176  
... ... @@ -1120,12 +1188,66 @@
1120 1188 else
1121 1189 cached_cclk = get_vco() >> csel;
1122 1190 return cached_cclk;
  1191 +#endif
1123 1192 }
1124 1193 EXPORT_SYMBOL(get_cclk);
1125 1194  
  1195 +#ifdef CONFIG_BF60x
  1196 +/* Get the bf60x clock of SCLK0 domain */
  1197 +u_long get_sclk0(void)
  1198 +{
  1199 + struct clk *sclk0;
  1200 + u_long sclk0_rate;
  1201 +
  1202 + sclk0 = clk_get(NULL, "SCLK0");
  1203 + if (IS_ERR(sclk0))
  1204 + return 0;
  1205 +
  1206 + sclk0_rate = clk_get_rate(sclk0);
  1207 + clk_put(sclk0);
  1208 + return sclk0_rate;
  1209 +}
  1210 +EXPORT_SYMBOL(get_sclk0);
  1211 +
  1212 +/* Get the bf60x clock of SCLK1 domain */
  1213 +u_long get_sclk1(void)
  1214 +{
  1215 + struct clk *sclk1;
  1216 + u_long sclk1_rate;
  1217 +
  1218 + sclk1 = clk_get(NULL, "SCLK1");
  1219 + if (IS_ERR(sclk1))
  1220 + return 0;
  1221 +
  1222 + sclk1_rate = clk_get_rate(sclk1);
  1223 + clk_put(sclk1);
  1224 + return sclk1_rate;
  1225 +}
  1226 +EXPORT_SYMBOL(get_sclk1);
  1227 +
  1228 +/* Get the bf60x DRAM clock */
  1229 +u_long get_dclk(void)
  1230 +{
  1231 + struct clk *dclk;
  1232 + u_long dclk_rate;
  1233 +
  1234 + dclk = clk_get(NULL, "DCLK");
  1235 + if (IS_ERR(dclk))
  1236 + return 0;
  1237 +
  1238 + dclk_rate = clk_get_rate(dclk);
  1239 + clk_put(dclk);
  1240 + return dclk_rate;
  1241 +}
  1242 +EXPORT_SYMBOL(get_dclk);
  1243 +#endif
  1244 +
1126 1245 /* Get the System clock */
1127 1246 u_long get_sclk(void)
1128 1247 {
  1248 +#ifdef CONFIG_BF60x
  1249 + return get_sclk0();
  1250 +#else
1129 1251 static u_long cached_sclk;
1130 1252 u_long ssel;
1131 1253  
... ... @@ -1146,6 +1268,7 @@
1146 1268  
1147 1269 cached_sclk = get_vco() / ssel;
1148 1270 return cached_sclk;
  1271 +#endif
1149 1272 }
1150 1273 EXPORT_SYMBOL(get_sclk);
1151 1274  
arch/blackfin/kernel/shadow_console.c
Diff comments   View file @ b5affb0
... ... @@ -15,9 +15,9 @@
15 15 #include <asm/irq_handler.h>
16 16 #include <asm/early_printk.h>
17 17  
18   -#define SHADOW_CONSOLE_START (0x500)
19   -#define SHADOW_CONSOLE_END (0x1000)
20   -#define SHADOW_CONSOLE_MAGIC_LOC (0x4F0)
  18 +#define SHADOW_CONSOLE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x500)
  19 +#define SHADOW_CONSOLE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x1000)
  20 +#define SHADOW_CONSOLE_MAGIC_LOC (CONFIG_PHY_RAM_BASE_ADDRESS + 0x4F0)
21 21 #define SHADOW_CONSOLE_MAGIC (0xDEADBEEF)
22 22  
23 23 static __initdata char *shadow_console_buffer = (char *)SHADOW_CONSOLE_START;
arch/blackfin/mach-common/entry.S
Diff comments   View file @ b5affb0
... ... @@ -1141,7 +1141,8 @@
1141 1141 sti r0;
1142 1142  
1143 1143 /* finish the userspace "atomic" functions for it */
1144   - r1 = FIXED_CODE_END;
  1144 + r1.l = lo(FIXED_CODE_END);
  1145 + r1.h = hi(FIXED_CODE_END);
1145 1146 r2 = [sp + PT_PC];
1146 1147 cc = r1 <= r2;
1147 1148 if cc jump .Lresume_userspace (bp);
arch/blackfin/mach-common/head.S
Diff comments   View file @ b5affb0
... ... @@ -210,14 +210,12 @@
210 210 ENTRY(_real_start)
211 211 /* Enable nested interrupts */
212 212 [--sp] = reti;
213   -
214 213 /* watchdog off for now */
215 214 p0.l = lo(WDOG_CTL);
216 215 p0.h = hi(WDOG_CTL);
217 216 r0 = 0xAD6(z);
218 217 w[p0] = r0;
219 218 ssync;
220   -
221 219 /* Pass the u-boot arguments to the global value command line */
222 220 R0 = R7;
223 221 call _cmdline_init;
arch/blackfin/mm/init.c
Diff comments   View file @ b5affb0
... ... @@ -48,7 +48,7 @@
48 48  
49 49 unsigned long zones_size[MAX_NR_ZONES] = {
50 50 [0] = 0,
51   - [ZONE_DMA] = (end_mem - PAGE_OFFSET) >> PAGE_SHIFT,
  51 + [ZONE_DMA] = (end_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> PAGE_SHIFT,
52 52 [ZONE_NORMAL] = 0,
53 53 #ifdef CONFIG_HIGHMEM
54 54 [ZONE_HIGHMEM] = 0,
... ... @@ -60,7 +60,8 @@
60 60  
61 61 pr_debug("free_area_init -> start_mem is %#lx virtual_end is %#lx\n",
62 62 PAGE_ALIGN(memory_start), end_mem);
63   - free_area_init(zones_size);
  63 + free_area_init_node(0, zones_size,
  64 + CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT, NULL);
64 65 }
65 66  
66 67 asmlinkage void __init init_pda(void)
... ... @@ -75,9 +76,6 @@
75 76 valid pointers to it. */
76 77 memset(&cpu_pda[cpu], 0, sizeof(cpu_pda[cpu]));
77 78  
78   - cpu_pda[0].next = &cpu_pda[1];
79   - cpu_pda[1].next = &cpu_pda[0];
80   -
81 79 #ifdef CONFIG_EXCEPTION_L1_SCRATCH
82 80 cpu_pda[cpu].ex_stack = (unsigned long *)(L1_SCRATCH_START + \
83 81 L1_SCRATCH_LENGTH);
84 82  
... ... @@ -109,10 +107,10 @@
109 107 totalram_pages = free_all_bootmem();
110 108  
111 109 reservedpages = 0;
112   - for (tmp = 0; tmp < max_mapnr; tmp++)
  110 + for (tmp = ARCH_PFN_OFFSET; tmp < max_mapnr; tmp++)
113 111 if (PageReserved(pfn_to_page(tmp)))
114 112 reservedpages++;
115   - freepages = max_mapnr - reservedpages;
  113 + freepages = max_mapnr - ARCH_PFN_OFFSET - reservedpages;
116 114  
117 115 /* do not count in kernel image between _rambase and _ramstart */
118 116 reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT;
... ... @@ -127,7 +125,7 @@
127 125 printk(KERN_INFO
128 126 "Memory available: %luk/%luk RAM, "
129 127 "(%uk init code, %uk kernel code, %uk data, %uk dma, %uk reserved)\n",
130   - (unsigned long) freepages << (PAGE_SHIFT-10), _ramend >> 10,
  128 + (unsigned long) freepages << (PAGE_SHIFT-10), (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 10,
131 129 initk, codek, datak, DMA_UNCACHED_REGION >> 10, (reservedpages << (PAGE_SHIFT-10)));
132 130 }
133 131