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Commit b5bbf0080e258383ecf67e57c7b46f4249878280

Authored by Yaniv Rosner
Committed by David S. Miller
1 parent 15ddd2d0ef
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

bnx2x: Modify BCM8706 link init seq 

Modify BCM8706 link initialization sequence so that first it link up
between Serdes and BCM8706, and only then between BCM8706 to network

Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

Showing 1 changed file with 18 additions and 13 deletions Side-by-side Diff

drivers/net/bnx2x_link.c
Diff comments   View file @ b5bbf00
... ... @@ -1930,6 +1930,8 @@
1930 1930 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1931 1931 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
1932 1932 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
  1933 + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) ||
  1934 + (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1933 1935 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726))) {
1934 1936 vars->autoneg = AUTO_NEG_ENABLED;
1935 1937  
... ... @@ -3772,19 +3774,6 @@
3772 3774 }
3773 3775 }
3774 3776 /* Force speed */
3775   - /* First enable LASI */
3776   - bnx2x_cl45_write(bp, params->port,
3777   - ext_phy_type,
3778   - ext_phy_addr,
3779   - MDIO_PMA_DEVAD,
3780   - MDIO_PMA_REG_RX_ALARM_CTRL,
3781   - 0x0400);
3782   - bnx2x_cl45_write(bp, params->port,
3783   - ext_phy_type,
3784   - ext_phy_addr,
3785   - MDIO_PMA_DEVAD,
3786   - MDIO_PMA_REG_LASI_CTRL, 0x0004);
3787   -
3788 3777 if (params->req_line_speed == SPEED_10000) {
3789 3778 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
3790 3779  
... ... @@ -3794,6 +3783,9 @@
3794 3783 MDIO_PMA_DEVAD,
3795 3784 MDIO_PMA_REG_DIGITAL_CTRL,
3796 3785 0x400);
  3786 + bnx2x_cl45_write(bp, params->port, ext_phy_type,
  3787 + ext_phy_addr, MDIO_PMA_DEVAD,
  3788 + MDIO_PMA_REG_LASI_CTRL, 1);
3797 3789 } else {
3798 3790 /* Force 1Gbps using autoneg with 1G
3799 3791 advertisment */
... ... @@ -3835,6 +3827,17 @@
3835 3827 MDIO_AN_DEVAD,
3836 3828 MDIO_AN_REG_CTRL,
3837 3829 0x1200);
  3830 + bnx2x_cl45_write(bp, params->port,
  3831 + ext_phy_type,
  3832 + ext_phy_addr,
  3833 + MDIO_PMA_DEVAD,
  3834 + MDIO_PMA_REG_RX_ALARM_CTRL,
  3835 + 0x0400);
  3836 + bnx2x_cl45_write(bp, params->port,
  3837 + ext_phy_type,
  3838 + ext_phy_addr,
  3839 + MDIO_PMA_DEVAD,
  3840 + MDIO_PMA_REG_LASI_CTRL, 0x0004);
3838 3841  
3839 3842 }
3840 3843 bnx2x_save_bcm_spirom_ver(bp, params->port,
... ... @@ -5952,6 +5955,7 @@
5952 5955  
5953 5956 if (non_ext_phy ||
5954 5957 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
  5958 + (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) ||
5955 5959 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ||
5956 5960 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
5957 5961 if (params->req_line_speed == SPEED_AUTO_NEG)
... ... @@ -6421,6 +6425,7 @@
6421 6425  
6422 6426 if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
6423 6427 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) &&
  6428 + (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) &&
6424 6429 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) &&
6425 6430 (ext_phy_link_up && !vars->phy_link_up))
6426 6431 bnx2x_init_internal_phy(params, vars, 0);