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Commit b671b653da35cd38897c7b19e9baed64e7a9e1a1

Authored by Greg Ungerer
Committed by Linus Torvalds
1 parent 2082b477dc
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[PATCH] m68knommu: read/write register access for PIT timer 

Modify the m68knommu/ColdFire PIT timer code to use register offsets
with raw_read/raw_write access, instead of a mapped struct.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

Showing 2 changed files with 23 additions and 22 deletions Side-by-side Diff

arch/m68knommu/platform/5307/pit.c
Diff comments   View file @ b671b65
1 1 /***************************************************************************/
2 2  
3 3 /*
4   - * pit.c -- Motorola ColdFire PIT timer. Currently this type of
5   - * hardware timer only exists in the Motorola ColdFire
  4 + * pit.c -- Freescale ColdFire PIT timer. Currently this type of
  5 + * hardware timer only exists in the Freescale ColdFire
6 6 * 5270/5271, 5282 and other CPUs.
7 7 *
8   - * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
  8 + * Copyright (C) 1999-2006, Greg Ungerer (gerg@snapgear.com)
9 9 * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
10 10 *
11 11 */
... ... @@ -18,6 +18,7 @@
18 18 #include <linux/param.h>
19 19 #include <linux/init.h>
20 20 #include <linux/interrupt.h>
  21 +#include <asm/io.h>
21 22 #include <asm/irq.h>
22 23 #include <asm/coldfire.h>
23 24 #include <asm/mcfpit.h>
24 25  
25 26  
... ... @@ -25,13 +26,20 @@
25 26  
26 27 /***************************************************************************/
27 28  
  29 +/*
  30 + * By default use timer1 as the system clock timer.
  31 + */
  32 +#define TA(a) (MCF_IPSBAR + MCFPIT_BASE1 + (a))
  33 +
  34 +/***************************************************************************/
  35 +
28 36 void coldfire_pit_tick(void)
29 37 {
30   - volatile struct mcfpit *tp;
  38 + unsigned short pcsr;
31 39  
32 40 /* Reset the ColdFire timer */
33   - tp = (volatile struct mcfpit *) (MCF_IPSBAR + MCFPIT_BASE1);
34   - tp->pcsr |= MCFPIT_PCSR_PIF;
  41 + pcsr = __raw_readw(TA(MCFPIT_PCSR));
  42 + __raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR));
35 43 }
36 44  
37 45 /***************************************************************************/
... ... @@ -40,7 +48,6 @@
40 48 {
41 49 volatile unsigned char *icrp;
42 50 volatile unsigned long *imrp;
43   - volatile struct mcfpit *tp;
44 51  
45 52 request_irq(MCFINT_VECBASE + MCFINT_PIT1, handler, SA_INTERRUPT,
46 53 "ColdFire Timer", NULL);
47 54  
48 55  
49 56  
... ... @@ -53,27 +60,23 @@
53 60 *imrp &= ~MCFPIT_IMR_IBIT;
54 61  
55 62 /* Set up PIT timer 1 as poll clock */
56   - tp = (volatile struct mcfpit *) (MCF_IPSBAR + MCFPIT_BASE1);
57   - tp->pcsr = MCFPIT_PCSR_DISABLE;
58   -
59   - tp->pmr = ((MCF_CLK / 2) / 64) / HZ;
60   - tp->pcsr = MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | MCFPIT_PCSR_OVW |
61   - MCFPIT_PCSR_RLD | MCFPIT_PCSR_CLK64;
  63 + __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
  64 + __raw_writew(((MCF_CLK / 2) / 64) / HZ, TA(MCFPIT_PMR));
  65 + __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | MCFPIT_PCSR_OVW |
  66 + MCFPIT_PCSR_RLD | MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
62 67 }
63 68  
64 69 /***************************************************************************/
65 70  
66 71 unsigned long coldfire_pit_offset(void)
67 72 {
68   - volatile struct mcfpit *tp;
69 73 volatile unsigned long *ipr;
70 74 unsigned long pmr, pcntr, offset;
71 75  
72   - tp = (volatile struct mcfpit *) (MCF_IPSBAR + MCFPIT_BASE1);
73 76 ipr = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFPIT_IMR);
74 77  
75   - pmr = *(&tp->pmr);
76   - pcntr = *(&tp->pcntr);
  78 + pmr = __raw_readw(TA(MCFPIT_PMR));
  79 + pcntr = __raw_readw(TA(MCFPIT_PCNTR));
77 80  
78 81 /*
79 82 * If we are still in the first half of the upcount and a
include/asm-m68knommu/mcfpit.h
Diff comments   View file @ b671b65
... ... @@ -28,11 +28,9 @@
28 28 /*
29 29 * Define the PIT timer register set addresses.
30 30 */
31   -struct mcfpit {
32   - unsigned short pcsr; /* PIT control and status */
33   - unsigned short pmr; /* PIT modulus register */
34   - unsigned short pcntr; /* PIT count register */
35   -} __attribute__((packed));
  31 +#define MCFPIT_PCSR 0x0 /* PIT control register */
  32 +#define MCFPIT_PMR 0x2 /* PIT modulus register */
  33 +#define MCFPIT_PCNTR 0x4 /* PIT count register */
36 34  
37 35 /*
38 36 * Bit definitions for the PIT Control and Status register.