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Commit bbd7e5e1e90954761f766400000a8f4c882d1202

Authored by Kukjin Kim
1 parent fc351246e2
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

ARM: S3C24XX: make bast-cpld.h, bast-irq.h and bast-map.h local 

The headers can be local in mach-s3c24xx/.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

Showing 12 changed files with 242 additions and 296 deletions Side-by-side Diff

arch/arm/mach-s3c24xx/bast-ide.c
Diff comments   View file @ bbd7e5e
... ... @@ -25,21 +25,19 @@
25 25 #include <asm/mach/irq.h>
26 26  
27 27 #include <mach/map.h>
28   -#include <mach/bast-map.h>
29   -#include <mach/bast-irq.h>
30 28  
  29 +#include "bast.h"
  30 +
31 31 /* IDE ports */
32 32  
33 33 static struct pata_platform_info bast_ide_platdata = {
34 34 .ioport_shift = 5,
35 35 };
36 36  
37   -#define IDE_CS S3C2410_CS5
38   -
39 37 static struct resource bast_ide0_resource[] = {
40   - [0] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDEPRI, 8 * 0x20),
41   - [1] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20), 0x20),
42   - [2] = DEFINE_RES_IRQ(IRQ_IDE0),
  38 + [0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRI, 8 * 0x20),
  39 + [1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20), 0x20),
  40 + [2] = DEFINE_RES_IRQ(BAST_IRQ_IDE0),
43 41 };
44 42  
45 43 static struct platform_device bast_device_ide0 = {
... ... @@ -55,9 +53,9 @@
55 53 };
56 54  
57 55 static struct resource bast_ide1_resource[] = {
58   - [0] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDESEC, 8 * 0x20),
59   - [1] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), 0x20),
60   - [2] = DEFINE_RES_IRQ(IRQ_IDE1),
  56 + [0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESEC, 8 * 0x20),
  57 + [1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), 0x20),
  58 + [2] = DEFINE_RES_IRQ(BAST_IRQ_IDE1),
61 59 };
62 60  
63 61 static struct platform_device bast_device_ide1 = {
arch/arm/mach-s3c24xx/bast-irq.c
Diff comments   View file @ bbd7e5e
... ... @@ -27,27 +27,20 @@
27 27 #include <linux/device.h>
28 28 #include <linux/io.h>
29 29  
30   -#include <asm/mach-types.h>
31   -
32   -#include <mach/hardware.h>
33 30 #include <asm/irq.h>
34   -
  31 +#include <asm/mach-types.h>
35 32 #include <asm/mach/irq.h>
36 33  
  34 +#include <mach/hardware.h>
37 35 #include <mach/regs-irq.h>
38   -#include <mach/bast-map.h>
39   -#include <mach/bast-irq.h>
40 36  
41 37 #include <plat/irq.h>
42 38  
43   -#if 0
44   -#include <asm/debug-ll.h>
45   -#endif
  39 +#include "bast.h"
46 40  
47 41 #define irqdbf(x...)
48 42 #define irqdbf2(x...)
49 43  
50   -
51 44 /* handle PC104 ISA interrupts from the system CPLD */
52 45  
53 46 /* table of ISA irq nos to the relevant mask... zero means
... ... @@ -87,7 +80,7 @@
87 80 static void
88 81 bast_pc104_maskack(struct irq_data *data)
89 82 {
90   - struct irq_desc *desc = irq_desc + IRQ_ISA;
  83 + struct irq_desc *desc = irq_desc + BAST_IRQ_ISA;
91 84  
92 85 bast_pc104_mask(data);
93 86 desc->irq_data.chip->irq_ack(&desc->irq_data);
... ... @@ -122,7 +115,7 @@
122 115 if (unlikely(stat == 0)) {
123 116 /* ack if we get an irq with nothing (ie, startup) */
124 117  
125   - desc = irq_desc + IRQ_ISA;
  118 + desc = irq_desc + BAST_IRQ_ISA;
126 119 desc->irq_data.chip->irq_ack(&desc->irq_data);
127 120 } else {
128 121 /* handle the IRQ */
... ... @@ -147,7 +140,7 @@
147 140  
148 141 __raw_writeb(0x0, BAST_VA_PC104_IRQMASK);
149 142  
150   - irq_set_chained_handler(IRQ_ISA, bast_irq_pc104_demux);
  143 + irq_set_chained_handler(BAST_IRQ_ISA, bast_irq_pc104_demux);
151 144  
152 145 /* register our IRQs */
153 146  
arch/arm/mach-s3c24xx/bast.h
Diff comments   View file @ bbd7e5e
  1 +/*
  2 + * Copyright (c) 2003-2004 Simtec Electronics
  3 + * Ben Dooks <ben@simtec.co.uk>
  4 + *
  5 + * BAST - CPLD control constants
  6 + * BAST - IRQ Number definitions
  7 + * BAST - Memory map definitions
  8 + *
  9 + * This program is free software; you can redistribute it and/or modify
  10 + * it under the terms of the GNU General Public License version 2 as
  11 + * published by the Free Software Foundation.
  12 +*/
  13 +
  14 +#ifndef __MACH_S3C24XX_BAST_H
  15 +#define __MACH_S3C24XX_BAST_H __FILE__
  16 +
  17 +/* CTRL1 - Audio LR routing */
  18 +
  19 +#define BAST_CPLD_CTRL1_LRCOFF (0x00)
  20 +#define BAST_CPLD_CTRL1_LRCADC (0x01)
  21 +#define BAST_CPLD_CTRL1_LRCDAC (0x02)
  22 +#define BAST_CPLD_CTRL1_LRCARM (0x03)
  23 +#define BAST_CPLD_CTRL1_LRMASK (0x03)
  24 +
  25 +/* CTRL2 - NAND WP control, IDE Reset assert/check */
  26 +
  27 +#define BAST_CPLD_CTRL2_WNAND (0x04)
  28 +#define BAST_CPLD_CTLR2_IDERST (0x08)
  29 +
  30 +/* CTRL3 - rom write control, CPLD identity */
  31 +
  32 +#define BAST_CPLD_CTRL3_IDMASK (0x0e)
  33 +#define BAST_CPLD_CTRL3_ROMWEN (0x01)
  34 +
  35 +/* CTRL4 - 8bit LCD interface control/status */
  36 +
  37 +#define BAST_CPLD_CTRL4_LLAT (0x01)
  38 +#define BAST_CPLD_CTRL4_LCDRW (0x02)
  39 +#define BAST_CPLD_CTRL4_LCDCMD (0x04)
  40 +#define BAST_CPLD_CTRL4_LCDE2 (0x01)
  41 +
  42 +/* CTRL5 - DMA routing */
  43 +
  44 +#define BAST_CPLD_DMA0_PRIIDE (0)
  45 +#define BAST_CPLD_DMA0_SECIDE (1)
  46 +#define BAST_CPLD_DMA0_ISA15 (2)
  47 +#define BAST_CPLD_DMA0_ISA36 (3)
  48 +
  49 +#define BAST_CPLD_DMA1_PRIIDE (0 << 2)
  50 +#define BAST_CPLD_DMA1_SECIDE (1 << 2)
  51 +#define BAST_CPLD_DMA1_ISA15 (2 << 2)
  52 +#define BAST_CPLD_DMA1_ISA36 (3 << 2)
  53 +
  54 +/* irq numbers to onboard peripherals */
  55 +
  56 +#define BAST_IRQ_USBOC IRQ_EINT18
  57 +#define BAST_IRQ_IDE0 IRQ_EINT16
  58 +#define BAST_IRQ_IDE1 IRQ_EINT17
  59 +#define BAST_IRQ_PCSERIAL1 IRQ_EINT15
  60 +#define BAST_IRQ_PCSERIAL2 IRQ_EINT14
  61 +#define BAST_IRQ_PCPARALLEL IRQ_EINT13
  62 +#define BAST_IRQ_ASIX IRQ_EINT11
  63 +#define BAST_IRQ_DM9000 IRQ_EINT10
  64 +#define BAST_IRQ_ISA IRQ_EINT9
  65 +#define BAST_IRQ_SMALERT IRQ_EINT8
  66 +
  67 +/* map */
  68 +
  69 +/*
  70 + * ok, we've used up to 0x13000000, now we need to find space for the
  71 + * peripherals that live in the nGCS[x] areas, which are quite numerous
  72 + * in their space. We also have the board's CPLD to find register space
  73 + * for.
  74 + */
  75 +
  76 +#define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
  77 +
  78 +/* we put the CPLD registers next, to get them out of the way */
  79 +
  80 +#define BAST_VA_CTRL1 BAST_IOADDR(0x00000000)
  81 +#define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
  82 +
  83 +#define BAST_VA_CTRL2 BAST_IOADDR(0x00100000)
  84 +#define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
  85 +
  86 +#define BAST_VA_CTRL3 BAST_IOADDR(0x00200000)
  87 +#define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
  88 +
  89 +#define BAST_VA_CTRL4 BAST_IOADDR(0x00300000)
  90 +#define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
  91 +
  92 +/* next, we have the PC104 ISA interrupt registers */
  93 +
  94 +#define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000)
  95 +#define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000)
  96 +
  97 +#define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000)
  98 +#define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000)
  99 +
  100 +#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000)
  101 +#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
  102 +
  103 +#define BAST_PA_LCD_RCMD1 (0x8800000)
  104 +#define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000)
  105 +
  106 +#define BAST_PA_LCD_WCMD1 (0x8000000)
  107 +#define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000)
  108 +
  109 +#define BAST_PA_LCD_RDATA1 (0x9800000)
  110 +#define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000)
  111 +
  112 +#define BAST_PA_LCD_WDATA1 (0x9000000)
  113 +#define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000)
  114 +
  115 +#define BAST_PA_LCD_RCMD2 (0xA800000)
  116 +#define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000)
  117 +
  118 +#define BAST_PA_LCD_WCMD2 (0xA000000)
  119 +#define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000)
  120 +
  121 +#define BAST_PA_LCD_RDATA2 (0xB800000)
  122 +#define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000)
  123 +
  124 +#define BAST_PA_LCD_WDATA2 (0xB000000)
  125 +#define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000)
  126 +
  127 +
  128 +/*
  129 + * 0xE0000000 contains the IO space that is split by speed and
  130 + * whether the access is for 8 or 16bit IO... this ensures that
  131 + * the correct access is made
  132 + *
  133 + * 0x10000000 of space, partitioned as so:
  134 + *
  135 + * 0x00000000 to 0x04000000 8bit, slow
  136 + * 0x04000000 to 0x08000000 16bit, slow
  137 + * 0x08000000 to 0x0C000000 16bit, net
  138 + * 0x0C000000 to 0x10000000 16bit, fast
  139 + *
  140 + * each of these spaces has the following in:
  141 + *
  142 + * 0x00000000 to 0x01000000 16MB ISA IO space
  143 + * 0x01000000 to 0x02000000 16MB ISA memory space
  144 + * 0x02000000 to 0x02100000 1MB IDE primary channel
  145 + * 0x02100000 to 0x02200000 1MB IDE primary channel aux
  146 + * 0x02200000 to 0x02400000 1MB IDE secondary channel
  147 + * 0x02300000 to 0x02400000 1MB IDE secondary channel aux
  148 + * 0x02400000 to 0x02500000 1MB ASIX ethernet controller
  149 + * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller
  150 + * 0x02600000 to 0x02700000 1MB PC SuperIO controller
  151 + *
  152 + * the phyiscal layout of the zones are:
  153 + * nGCS2 - 8bit, slow
  154 + * nGCS3 - 16bit, slow
  155 + * nGCS4 - 16bit, net
  156 + * nGCS5 - 16bit, fast
  157 + */
  158 +
  159 +#define BAST_VA_MULTISPACE (0xE0000000)
  160 +
  161 +#define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000)
  162 +#define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000)
  163 +#define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000)
  164 +#define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000)
  165 +#define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000)
  166 +#define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000)
  167 +#define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000)
  168 +#define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000)
  169 +#define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000)
  170 +
  171 +#define BAST_VAM_CS2 (0x00000000)
  172 +#define BAST_VAM_CS3 (0x04000000)
  173 +#define BAST_VAM_CS4 (0x08000000)
  174 +#define BAST_VAM_CS5 (0x0C000000)
  175 +
  176 +/* physical offset addresses for the peripherals */
  177 +
  178 +#define BAST_PA_ISAIO (0x00000000)
  179 +#define BAST_PA_ASIXNET (0x01000000)
  180 +#define BAST_PA_SUPERIO (0x01800000)
  181 +#define BAST_PA_IDEPRI (0x02000000)
  182 +#define BAST_PA_IDEPRIAUX (0x02800000)
  183 +#define BAST_PA_IDESEC (0x03000000)
  184 +#define BAST_PA_IDESECAUX (0x03800000)
  185 +#define BAST_PA_ISAMEM (0x04000000)
  186 +#define BAST_PA_DM9000 (0x05000000)
  187 +
  188 +/* some configurations for the peripherals */
  189 +
  190 +#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
  191 +
  192 +#define BAST_ASIXNET_CS BAST_VAM_CS5
  193 +#define BAST_DM9000_CS BAST_VAM_CS4
  194 +
  195 +#define BAST_IDE_CS S3C2410_CS5
  196 +
  197 +#endif /* __MACH_S3C24XX_BAST_H */
arch/arm/mach-s3c24xx/include/mach/bast-cpld.h
View file @ bbd7e5e
1   -/* arch/arm/mach-s3c2410/include/mach/bast-cpld.h
2   - *
3   - * Copyright (c) 2003-2004 Simtec Electronics
4   - * Ben Dooks <ben@simtec.co.uk>
5   - *
6   - * BAST - CPLD control constants
7   - *
8   - * This program is free software; you can redistribute it and/or modify
9   - * it under the terms of the GNU General Public License version 2 as
10   - * published by the Free Software Foundation.
11   -*/
12   -
13   -#ifndef __ASM_ARCH_BASTCPLD_H
14   -#define __ASM_ARCH_BASTCPLD_H
15   -
16   -/* CTRL1 - Audio LR routing */
17   -
18   -#define BAST_CPLD_CTRL1_LRCOFF (0x00)
19   -#define BAST_CPLD_CTRL1_LRCADC (0x01)
20   -#define BAST_CPLD_CTRL1_LRCDAC (0x02)
21   -#define BAST_CPLD_CTRL1_LRCARM (0x03)
22   -#define BAST_CPLD_CTRL1_LRMASK (0x03)
23   -
24   -/* CTRL2 - NAND WP control, IDE Reset assert/check */
25   -
26   -#define BAST_CPLD_CTRL2_WNAND (0x04)
27   -#define BAST_CPLD_CTLR2_IDERST (0x08)
28   -
29   -/* CTRL3 - rom write control, CPLD identity */
30   -
31   -#define BAST_CPLD_CTRL3_IDMASK (0x0e)
32   -#define BAST_CPLD_CTRL3_ROMWEN (0x01)
33   -
34   -/* CTRL4 - 8bit LCD interface control/status */
35   -
36   -#define BAST_CPLD_CTRL4_LLAT (0x01)
37   -#define BAST_CPLD_CTRL4_LCDRW (0x02)
38   -#define BAST_CPLD_CTRL4_LCDCMD (0x04)
39   -#define BAST_CPLD_CTRL4_LCDE2 (0x01)
40   -
41   -/* CTRL5 - DMA routing */
42   -
43   -#define BAST_CPLD_DMA0_PRIIDE (0<<0)
44   -#define BAST_CPLD_DMA0_SECIDE (1<<0)
45   -#define BAST_CPLD_DMA0_ISA15 (2<<0)
46   -#define BAST_CPLD_DMA0_ISA36 (3<<0)
47   -
48   -#define BAST_CPLD_DMA1_PRIIDE (0<<2)
49   -#define BAST_CPLD_DMA1_SECIDE (1<<2)
50   -#define BAST_CPLD_DMA1_ISA15 (2<<2)
51   -#define BAST_CPLD_DMA1_ISA36 (3<<2)
52   -
53   -#endif /* __ASM_ARCH_BASTCPLD_H */
arch/arm/mach-s3c24xx/include/mach/bast-irq.h
View file @ bbd7e5e
1   -/* arch/arm/mach-s3c2410/include/mach/bast-irq.h
2   - *
3   - * Copyright (c) 2003-2004 Simtec Electronics
4   - * Ben Dooks <ben@simtec.co.uk>
5   - *
6   - * Machine BAST - IRQ Number definitions
7   - *
8   - * This program is free software; you can redistribute it and/or modify
9   - * it under the terms of the GNU General Public License version 2 as
10   - * published by the Free Software Foundation.
11   -*/
12   -
13   -#ifndef __ASM_ARCH_BASTIRQ_H
14   -#define __ASM_ARCH_BASTIRQ_H
15   -
16   -/* irq numbers to onboard peripherals */
17   -
18   -#define IRQ_USBOC IRQ_EINT18
19   -#define IRQ_IDE0 IRQ_EINT16
20   -#define IRQ_IDE1 IRQ_EINT17
21   -#define IRQ_PCSERIAL1 IRQ_EINT15
22   -#define IRQ_PCSERIAL2 IRQ_EINT14
23   -#define IRQ_PCPARALLEL IRQ_EINT13
24   -#define IRQ_ASIX IRQ_EINT11
25   -#define IRQ_DM9000 IRQ_EINT10
26   -#define IRQ_ISA IRQ_EINT9
27   -#define IRQ_SMALERT IRQ_EINT8
28   -
29   -#endif /* __ASM_ARCH_BASTIRQ_H */
arch/arm/mach-s3c24xx/include/mach/bast-map.h
View file @ bbd7e5e
1   -/* arch/arm/mach-s3c2410/include/mach/bast-map.h
2   - *
3   - * Copyright (c) 2003-2004 Simtec Electronics
4   - * Ben Dooks <ben@simtec.co.uk>
5   - *
6   - * Machine BAST - Memory map definitions
7   - *
8   - * This program is free software; you can redistribute it and/or modify
9   - * it under the terms of the GNU General Public License version 2 as
10   - * published by the Free Software Foundation.
11   -*/
12   -
13   -/* needs arch/map.h including with this */
14   -
15   -/* ok, we've used up to 0x13000000, now we need to find space for the
16   - * peripherals that live in the nGCS[x] areas, which are quite numerous
17   - * in their space. We also have the board's CPLD to find register space
18   - * for.
19   - */
20   -
21   -#ifndef __ASM_ARCH_BASTMAP_H
22   -#define __ASM_ARCH_BASTMAP_H
23   -
24   -#define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
25   -
26   -/* we put the CPLD registers next, to get them out of the way */
27   -
28   -#define BAST_VA_CTRL1 BAST_IOADDR(0x00000000) /* 0x01300000 */
29   -#define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
30   -
31   -#define BAST_VA_CTRL2 BAST_IOADDR(0x00100000) /* 0x01400000 */
32   -#define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
33   -
34   -#define BAST_VA_CTRL3 BAST_IOADDR(0x00200000) /* 0x01500000 */
35   -#define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
36   -
37   -#define BAST_VA_CTRL4 BAST_IOADDR(0x00300000) /* 0x01600000 */
38   -#define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
39   -
40   -/* next, we have the PC104 ISA interrupt registers */
41   -
42   -#define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
43   -#define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000)
44   -
45   -#define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
46   -#define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000)
47   -
48   -#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
49   -#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
50   -
51   -#define BAST_PA_LCD_RCMD1 (0x8800000)
52   -#define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000)
53   -
54   -#define BAST_PA_LCD_WCMD1 (0x8000000)
55   -#define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000)
56   -
57   -#define BAST_PA_LCD_RDATA1 (0x9800000)
58   -#define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000)
59   -
60   -#define BAST_PA_LCD_WDATA1 (0x9000000)
61   -#define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000)
62   -
63   -#define BAST_PA_LCD_RCMD2 (0xA800000)
64   -#define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000)
65   -
66   -#define BAST_PA_LCD_WCMD2 (0xA000000)
67   -#define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000)
68   -
69   -#define BAST_PA_LCD_RDATA2 (0xB800000)
70   -#define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000)
71   -
72   -#define BAST_PA_LCD_WDATA2 (0xB000000)
73   -#define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000)
74   -
75   -
76   -/* 0xE0000000 contains the IO space that is split by speed and
77   - * whether the access is for 8 or 16bit IO... this ensures that
78   - * the correct access is made
79   - *
80   - * 0x10000000 of space, partitioned as so:
81   - *
82   - * 0x00000000 to 0x04000000 8bit, slow
83   - * 0x04000000 to 0x08000000 16bit, slow
84   - * 0x08000000 to 0x0C000000 16bit, net
85   - * 0x0C000000 to 0x10000000 16bit, fast
86   - *
87   - * each of these spaces has the following in:
88   - *
89   - * 0x00000000 to 0x01000000 16MB ISA IO space
90   - * 0x01000000 to 0x02000000 16MB ISA memory space
91   - * 0x02000000 to 0x02100000 1MB IDE primary channel
92   - * 0x02100000 to 0x02200000 1MB IDE primary channel aux
93   - * 0x02200000 to 0x02400000 1MB IDE secondary channel
94   - * 0x02300000 to 0x02400000 1MB IDE secondary channel aux
95   - * 0x02400000 to 0x02500000 1MB ASIX ethernet controller
96   - * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller
97   - * 0x02600000 to 0x02700000 1MB PC SuperIO controller
98   - *
99   - * the phyiscal layout of the zones are:
100   - * nGCS2 - 8bit, slow
101   - * nGCS3 - 16bit, slow
102   - * nGCS4 - 16bit, net
103   - * nGCS5 - 16bit, fast
104   - */
105   -
106   -#define BAST_VA_MULTISPACE (0xE0000000)
107   -
108   -#define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000)
109   -#define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000)
110   -#define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000)
111   -#define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000)
112   -#define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000)
113   -#define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000)
114   -#define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000)
115   -#define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000)
116   -#define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000)
117   -
118   -#define BAST_VA_MULTISPACE (0xE0000000)
119   -
120   -#define BAST_VAM_CS2 (0x00000000)
121   -#define BAST_VAM_CS3 (0x04000000)
122   -#define BAST_VAM_CS4 (0x08000000)
123   -#define BAST_VAM_CS5 (0x0C000000)
124   -
125   -/* physical offset addresses for the peripherals */
126   -
127   -#define BAST_PA_ISAIO (0x00000000)
128   -#define BAST_PA_ASIXNET (0x01000000)
129   -#define BAST_PA_SUPERIO (0x01800000)
130   -#define BAST_PA_IDEPRI (0x02000000)
131   -#define BAST_PA_IDEPRIAUX (0x02800000)
132   -#define BAST_PA_IDESEC (0x03000000)
133   -#define BAST_PA_IDESECAUX (0x03800000)
134   -#define BAST_PA_ISAMEM (0x04000000)
135   -#define BAST_PA_DM9000 (0x05000000)
136   -
137   -/* some configurations for the peripherals */
138   -
139   -#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
140   -/* */
141   -
142   -#define BAST_ASIXNET_CS BAST_VAM_CS5
143   -#define BAST_IDE_CS BAST_VAM_CS5
144   -#define BAST_DM9000_CS BAST_VAM_CS4
145   -
146   -#endif /* __ASM_ARCH_BASTMAP_H */
arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
Diff comments   View file @ bbd7e5e
... ... @@ -21,9 +21,7 @@
21 21 #ifndef __ASM_ARCH_VR1000MAP_H
22 22 #define __ASM_ARCH_VR1000MAP_H
23 23  
24   -#include <mach/bast-map.h>
25   -
26   -#define VR1000_IOADDR(x) BAST_IOADDR(x)
  24 +#define VR1000_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
27 25  
28 26 /* we put the CPLD registers next, to get them out of the way */
29 27  
arch/arm/mach-s3c24xx/mach-bast.c
Diff comments   View file @ bbd7e5e
... ... @@ -24,48 +24,42 @@
24 24 #include <linux/ata_platform.h>
25 25 #include <linux/i2c.h>
26 26 #include <linux/io.h>
  27 +#include <linux/serial_8250.h>
27 28  
  29 +#include <linux/mtd/mtd.h>
  30 +#include <linux/mtd/nand.h>
  31 +#include <linux/mtd/nand_ecc.h>
  32 +#include <linux/mtd/partitions.h>
  33 +
  34 +#include <linux/platform_data/asoc-s3c24xx_simtec.h>
  35 +#include <linux/platform_data/hwmon-s3c.h>
  36 +#include <linux/platform_data/i2c-s3c2410.h>
  37 +#include <linux/platform_data/mtd-nand-s3c2410.h>
  38 +
28 39 #include <net/ax88796.h>
29 40  
  41 +#include <asm/irq.h>
30 42 #include <asm/mach/arch.h>
31 43 #include <asm/mach/map.h>
32 44 #include <asm/mach/irq.h>
33   -
34   -#include <mach/bast-map.h>
35   -#include <mach/bast-irq.h>
36   -#include <mach/bast-cpld.h>
37   -
38   -#include <mach/hardware.h>
39   -#include <asm/irq.h>
40 45 #include <asm/mach-types.h>
41 46  
42   -//#include <asm/debug-ll.h>
43   -#include <plat/regs-serial.h>
  47 +#include <mach/fb.h>
  48 +#include <mach/hardware.h>
44 49 #include <mach/regs-gpio.h>
45   -#include <mach/regs-mem.h>
46 50 #include <mach/regs-lcd.h>
  51 +#include <mach/regs-mem.h>
47 52  
48   -#include <linux/platform_data/hwmon-s3c.h>
49   -#include <linux/platform_data/mtd-nand-s3c2410.h>
50   -#include <linux/platform_data/i2c-s3c2410.h>
51   -#include <mach/fb.h>
52   -
53   -#include <linux/mtd/mtd.h>
54   -#include <linux/mtd/nand.h>
55   -#include <linux/mtd/nand_ecc.h>
56   -#include <linux/mtd/partitions.h>
57   -
58   -#include <linux/serial_8250.h>
59   -
60 53 #include <plat/clock.h>
61   -#include <plat/devs.h>
62 54 #include <plat/cpu.h>
63 55 #include <plat/cpu-freq.h>
  56 +#include <plat/devs.h>
64 57 #include <plat/gpio-cfg.h>
65   -#include <linux/platform_data/asoc-s3c24xx_simtec.h>
  58 +#include <plat/regs-serial.h>
66 59  
67   -#include "simtec.h"
  60 +#include "bast.h"
68 61 #include "common.h"
  62 +#include "simtec.h"
69 63  
70 64 #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
71 65  
... ... @@ -312,7 +306,7 @@
312 306 static struct resource bast_dm9k_resource[] = {
313 307 [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4),
314 308 [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40),
315   - [2] = DEFINE_RES_NAMED(IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
  309 + [2] = DEFINE_RES_NAMED(BAST_IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
316 310 | IORESOURCE_IRQ_HIGHLEVEL),
317 311 };
318 312  
... ... @@ -343,7 +337,7 @@
343 337 static struct plat_serial8250_port bast_sio_data[] = {
344 338 [0] = {
345 339 .mapbase = SERIAL_BASE + 0x2f8,
346   - .irq = IRQ_PCSERIAL1,
  340 + .irq = BAST_IRQ_PCSERIAL1,
347 341 .flags = SERIAL_FLAGS,
348 342 .iotype = UPIO_MEM,
349 343 .regshift = 0,
... ... @@ -351,7 +345,7 @@
351 345 },
352 346 [1] = {
353 347 .mapbase = SERIAL_BASE + 0x3f8,
354   - .irq = IRQ_PCSERIAL2,
  348 + .irq = BAST_IRQ_PCSERIAL2,
355 349 .flags = SERIAL_FLAGS,
356 350 .iotype = UPIO_MEM,
357 351 .regshift = 0,
... ... @@ -390,7 +384,7 @@
390 384 static struct resource bast_asix_resource[] = {
391 385 [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20),
392 386 [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1),
393   - [2] = DEFINE_RES_IRQ(IRQ_ASIX),
  387 + [2] = DEFINE_RES_IRQ(BAST_IRQ_ASIX),
394 388 };
395 389  
396 390 static struct platform_device bast_device_asix = {
arch/arm/mach-s3c24xx/mach-vr1000.c
Diff comments   View file @ bbd7e5e
... ... @@ -32,7 +32,6 @@
32 32 #include <asm/mach/map.h>
33 33 #include <asm/mach/irq.h>
34 34  
35   -#include <mach/bast-map.h>
36 35 #include <mach/vr1000-map.h>
37 36 #include <mach/vr1000-irq.h>
38 37 #include <mach/vr1000-cpld.h>
39 38  
... ... @@ -51,8 +50,9 @@
51 50 #include <linux/platform_data/i2c-s3c2410.h>
52 51 #include <linux/platform_data/asoc-s3c24xx_simtec.h>
53 52  
54   -#include "simtec.h"
  53 +#include "bast.h"
55 54 #include "common.h"
  55 +#include "simtec.h"
56 56  
57 57 /* macros for virtual address mods for the io space entries */
58 58 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
arch/arm/mach-s3c24xx/simtec-audio.c
Diff comments   View file @ bbd7e5e
... ... @@ -17,16 +17,13 @@
17 17 #include <linux/device.h>
18 18 #include <linux/io.h>
19 19  
20   -#include <mach/bast-map.h>
21   -#include <mach/bast-irq.h>
22   -#include <mach/bast-cpld.h>
23   -
24 20 #include <mach/hardware.h>
25 21 #include <mach/regs-gpio.h>
26 22  
27 23 #include <linux/platform_data/asoc-s3c24xx_simtec.h>
28 24 #include <plat/devs.h>
29 25  
  26 +#include "bast.h"
30 27 #include "simtec.h"
31 28  
32 29 /* platform ops for audio */
arch/arm/mach-s3c24xx/simtec-nor.c
Diff comments   View file @ bbd7e5e
... ... @@ -27,9 +27,8 @@
27 27 #include <asm/mach/irq.h>
28 28  
29 29 #include <mach/map.h>
30   -#include <mach/bast-map.h>
31   -#include <mach/bast-cpld.h>
32 30  
  31 +#include "bast.h"
33 32 #include "simtec.h"
34 33  
35 34 static void simtec_nor_vpp(struct platform_device *pdev, int vpp)
arch/arm/mach-s3c24xx/simtec-usb.c
Diff comments   View file @ bbd7e5e
... ... @@ -28,15 +28,13 @@
28 28 #include <asm/mach/map.h>
29 29 #include <asm/mach/irq.h>
30 30  
31   -#include <mach/bast-map.h>
32   -#include <mach/bast-irq.h>
33   -
34 31 #include <mach/hardware.h>
35 32 #include <asm/irq.h>
36 33  
37 34 #include <linux/platform_data/usb-ohci-s3c2410.h>
38 35 #include <plat/devs.h>
39 36  
  37 +#include "bast.h"
40 38 #include "simtec.h"
41 39  
42 40 /* control power and monitor over-current events on various Simtec
... ... @@ -79,7 +77,7 @@
79 77 int ret;
80 78  
81 79 if (on) {
82   - ret = request_irq(IRQ_USBOC, usb_simtec_ocirq,
  80 + ret = request_irq(BAST_IRQ_USBOC, usb_simtec_ocirq,
83 81 IRQF_DISABLED | IRQF_TRIGGER_RISING |
84 82 IRQF_TRIGGER_FALLING,
85 83 "USB Over-current", info);
... ... @@ -87,7 +85,7 @@
87 85 printk(KERN_ERR "failed to request usb oc irq\n");
88 86 }
89 87 } else {
90   - free_irq(IRQ_USBOC, info);
  88 + free_irq(BAST_IRQ_USBOC, info);
91 89 }
92 90 }
93 91