Doug / smarc-fsl-linux-kernel

Download as
Browse Code ยป

Commit be41cf589b0b7613c845802878afabc7e214cb79

Authored by Laurent Navet
Committed by Linus Walleij
1 parent e37f4af762
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

gpio: gpio-sch.c: fix checkpatch error 

Fix :
 gpio/gpio-sch.c:206: ERROR: switch and case should be at the same indent

Also remove blank lines

Signed-off-by: Laurent Navet <laurent.navet@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Showing 1 changed file with 35 additions and 39 deletions Side-by-side Diff

drivers/gpio/gpio-sch.c
Diff comments   View file @ be41cf5
... ... @@ -221,45 +221,41 @@
221 221 gpio_ba = res->start;
222 222  
223 223 switch (id) {
224   - case PCI_DEVICE_ID_INTEL_SCH_LPC:
225   - sch_gpio_core.base = 0;
226   - sch_gpio_core.ngpio = 10;
  224 + case PCI_DEVICE_ID_INTEL_SCH_LPC:
  225 + sch_gpio_core.base = 0;
  226 + sch_gpio_core.ngpio = 10;
  227 + sch_gpio_resume.base = 10;
  228 + sch_gpio_resume.ngpio = 4;
  229 + /*
  230 + * GPIO[6:0] enabled by default
  231 + * GPIO7 is configured by the CMC as SLPIOVR
  232 + * Enable GPIO[9:8] core powered gpios explicitly
  233 + */
  234 + outb(0x3, gpio_ba + CGEN + 1);
  235 + /*
  236 + * SUS_GPIO[2:0] enabled by default
  237 + * Enable SUS_GPIO3 resume powered gpio explicitly
  238 + */
  239 + outb(0x8, gpio_ba + RGEN);
  240 + break;
227 241  
228   - sch_gpio_resume.base = 10;
229   - sch_gpio_resume.ngpio = 4;
  242 + case PCI_DEVICE_ID_INTEL_ITC_LPC:
  243 + sch_gpio_core.base = 0;
  244 + sch_gpio_core.ngpio = 5;
  245 + sch_gpio_resume.base = 5;
  246 + sch_gpio_resume.ngpio = 9;
  247 + break;
230 248  
231   - /*
232   - * GPIO[6:0] enabled by default
233   - * GPIO7 is configured by the CMC as SLPIOVR
234   - * Enable GPIO[9:8] core powered gpios explicitly
235   - */
236   - outb(0x3, gpio_ba + CGEN + 1);
237   - /*
238   - * SUS_GPIO[2:0] enabled by default
239   - * Enable SUS_GPIO3 resume powered gpio explicitly
240   - */
241   - outb(0x8, gpio_ba + RGEN);
242   - break;
  249 + case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
  250 + sch_gpio_core.base = 0;
  251 + sch_gpio_core.ngpio = 21;
  252 + sch_gpio_resume.base = 21;
  253 + sch_gpio_resume.ngpio = 9;
  254 + break;
243 255  
244   - case PCI_DEVICE_ID_INTEL_ITC_LPC:
245   - sch_gpio_core.base = 0;
246   - sch_gpio_core.ngpio = 5;
247   -
248   - sch_gpio_resume.base = 5;
249   - sch_gpio_resume.ngpio = 9;
250   - break;
251   -
252   - case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
253   - sch_gpio_core.base = 0;
254   - sch_gpio_core.ngpio = 21;
255   -
256   - sch_gpio_resume.base = 21;
257   - sch_gpio_resume.ngpio = 9;
258   - break;
259   -
260   - default:
261   - err = -ENODEV;
262   - goto err_sch_gpio_core;
  256 + default:
  257 + err = -ENODEV;
  258 + goto err_sch_gpio_core;
263 259 }
264 260  
265 261 sch_gpio_core.dev = &pdev->dev;