ARC: No need to flush the TLB in early boot

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

ARC: No need to flush the TLB in early boot
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Vineet Gupta
1 parent 483e9bcb01
Showing 1 changed file with 0 additions and 7 deletions Side-by-side Diff
arch/arc/mm/tlb.c
@@ -577,13 +577,6 @@
 	if (mmu->pg_sz != PAGE_SIZE)
 		panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));
  
-	/*
-	 * ASID mgmt data structures are compile time init
-	 *  asid_cache = FIRST_ASID and asid_mm_map[] all zeroes
-	 */
-
-	local_flush_tlb_all();
-
 	/* Enable the MMU */
 	write_aux_reg(ARC_REG_PID, MMU_ENABLE);
...	...	@@ -577,13 +577,6 @@
577	577	if (mmu->pg_sz != PAGE_SIZE)
578	578	panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));
579	579
580		- /*
581		- * ASID mgmt data structures are compile time init
582		- * asid_cache = FIRST_ASID and asid_mm_map[] all zeroes
583		- */
584		-
585		- local_flush_tlb_all();
586		-
587	580	/* Enable the MMU */
588	581	write_aux_reg(ARC_REG_PID, MMU_ENABLE);
589	582