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Commit c220153654ede57b41900159eb8d1f6029d85642

Authored by Mark A. Greer
Committed by Paul Mackerras
1 parent 16e9f99444
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[POWERPC] todc: add support for Time-Of-Day-Clock 

This is a resubmit with a proper subject and with all comments addressed.
Applies cleanly to powerpc.git 649e85797259162f7fdc696420e7492f20226f2d

Mark
--

The todc code from arch/ppc supports many todc/rtc chips and is needed
in arch/powerpc.  This patch adds the todc code to arch/powerpc.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
--

 arch/powerpc/Kconfig         |    7
 arch/powerpc/sysdev/Makefile |    1
 arch/powerpc/sysdev/todc.c   |  392 ++++++++++++++++++++++++++++++++++
 include/asm-powerpc/todc.h   |  487 +++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 887 insertions(+)
--
Signed-off-by: Paul Mackerras <paulus@samba.org>

Showing 4 changed files with 887 additions and 0 deletions Side-by-side Diff

arch/powerpc/Kconfig
Diff comments   View file @ c220153
... ... @@ -563,6 +563,13 @@
563 563 /proc/cpuinfo.
564 564  
565 565 If in doubt, say N here.
  566 +
  567 +config PPC_TODC
  568 + depends on EMBEDDED6xx
  569 + bool "Generic Time-of-day Clock (TODC) support"
  570 + ---help---
  571 + This adds support for many TODC/RTC chips.
  572 +
566 573 endmenu
567 574  
568 575 source arch/powerpc/platforms/embedded6xx/Kconfig
arch/powerpc/sysdev/Makefile
Diff comments   View file @ c220153
... ... @@ -12,5 +12,6 @@
12 12 obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
13 13 obj-$(CONFIG_PPC_83xx) += ipic.o
14 14 obj-$(CONFIG_FSL_SOC) += fsl_soc.o
  15 +obj-$(CONFIG_PPC_TODC) += todc.o
15 16 obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
arch/powerpc/sysdev/todc.c
Diff comments   View file @ c220153
  1 +/*
  2 + * Time of Day Clock support for the M48T35, M48T37, M48T59, and MC146818
  3 + * Real Time Clocks/Timekeepers.
  4 + *
  5 + * Author: Mark A. Greer <mgreer@mvista.com>
  6 + *
  7 + * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
  8 + * the terms of the GNU General Public License version 2. This program
  9 + * is licensed "as is" without any warranty of any kind, whether express
  10 + * or implied.
  11 + */
  12 +#include <linux/errno.h>
  13 +#include <linux/init.h>
  14 +#include <linux/kernel.h>
  15 +#include <linux/time.h>
  16 +#include <linux/timex.h>
  17 +#include <linux/bcd.h>
  18 +#include <linux/mc146818rtc.h>
  19 +
  20 +#include <asm/machdep.h>
  21 +#include <asm/io.h>
  22 +#include <asm/time.h>
  23 +#include <asm/todc.h>
  24 +
  25 +/*
  26 + * Depending on the hardware on your board and your board design, the
  27 + * RTC/NVRAM may be accessed either directly (like normal memory) or via
  28 + * address/data registers. If your board uses the direct method, set
  29 + * 'nvram_data' to the base address of your nvram and leave 'nvram_as0' and
  30 + * 'nvram_as1' NULL. If your board uses address/data regs to access nvram,
  31 + * set 'nvram_as0' to the address of the lower byte, set 'nvram_as1' to the
  32 + * address of the upper byte (leave NULL if using mc146818), and set
  33 + * 'nvram_data' to the address of the 8-bit data register.
  34 + *
  35 + * Note: Even though the documentation for the various RTC chips say that it
  36 + * take up to a second before it starts updating once the 'R' bit is
  37 + * cleared, they always seem to update even though we bang on it many
  38 + * times a second. This is true, except for the Dallas Semi 1746/1747
  39 + * (possibly others). Those chips seem to have a real problem whenever
  40 + * we set the 'R' bit before reading them, they basically stop counting.
  41 + * --MAG
  42 + */
  43 +
  44 +/*
  45 + * 'todc_info' should be initialized in your *_setup.c file to
  46 + * point to a fully initialized 'todc_info_t' structure.
  47 + * This structure holds all the register offsets for your particular
  48 + * TODC/RTC chip.
  49 + * TODC_ALLOC()/TODC_INIT() will allocate and initialize this table for you.
  50 + */
  51 +
  52 +#ifdef RTC_FREQ_SELECT
  53 +#undef RTC_FREQ_SELECT
  54 +#define RTC_FREQ_SELECT control_b /* Register A */
  55 +#endif
  56 +
  57 +#ifdef RTC_CONTROL
  58 +#undef RTC_CONTROL
  59 +#define RTC_CONTROL control_a /* Register B */
  60 +#endif
  61 +
  62 +#ifdef RTC_INTR_FLAGS
  63 +#undef RTC_INTR_FLAGS
  64 +#define RTC_INTR_FLAGS watchdog /* Register C */
  65 +#endif
  66 +
  67 +#ifdef RTC_VALID
  68 +#undef RTC_VALID
  69 +#define RTC_VALID interrupts /* Register D */
  70 +#endif
  71 +
  72 +/* Access routines when RTC accessed directly (like normal memory) */
  73 +u_char
  74 +todc_direct_read_val(int addr)
  75 +{
  76 + return readb((void __iomem *)(todc_info->nvram_data + addr));
  77 +}
  78 +
  79 +void
  80 +todc_direct_write_val(int addr, unsigned char val)
  81 +{
  82 + writeb(val, (void __iomem *)(todc_info->nvram_data + addr));
  83 + return;
  84 +}
  85 +
  86 +/* Access routines for accessing m48txx type chips via addr/data regs */
  87 +u_char
  88 +todc_m48txx_read_val(int addr)
  89 +{
  90 + outb(addr, todc_info->nvram_as0);
  91 + outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
  92 + return inb(todc_info->nvram_data);
  93 +}
  94 +
  95 +void
  96 +todc_m48txx_write_val(int addr, unsigned char val)
  97 +{
  98 + outb(addr, todc_info->nvram_as0);
  99 + outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
  100 + outb(val, todc_info->nvram_data);
  101 + return;
  102 +}
  103 +
  104 +/* Access routines for accessing mc146818 type chips via addr/data regs */
  105 +u_char
  106 +todc_mc146818_read_val(int addr)
  107 +{
  108 + outb_p(addr, todc_info->nvram_as0);
  109 + return inb_p(todc_info->nvram_data);
  110 +}
  111 +
  112 +void
  113 +todc_mc146818_write_val(int addr, unsigned char val)
  114 +{
  115 + outb_p(addr, todc_info->nvram_as0);
  116 + outb_p(val, todc_info->nvram_data);
  117 +}
  118 +
  119 +
  120 +/*
  121 + * Routines to make RTC chips with NVRAM buried behind an addr/data pair
  122 + * have the NVRAM and clock regs appear at the same level.
  123 + * The NVRAM will appear to start at addr 0 and the clock regs will appear
  124 + * to start immediately after the NVRAM (actually, start at offset
  125 + * todc_info->nvram_size).
  126 + */
  127 +static inline u_char
  128 +todc_read_val(int addr)
  129 +{
  130 + u_char val;
  131 +
  132 + if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
  133 + if (addr < todc_info->nvram_size) { /* NVRAM */
  134 + ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
  135 + val = ppc_md.rtc_read_val(todc_info->nvram_data_reg);
  136 + } else { /* Clock Reg */
  137 + addr -= todc_info->nvram_size;
  138 + val = ppc_md.rtc_read_val(addr);
  139 + }
  140 + } else
  141 + val = ppc_md.rtc_read_val(addr);
  142 +
  143 + return val;
  144 +}
  145 +
  146 +static inline void
  147 +todc_write_val(int addr, u_char val)
  148 +{
  149 + if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
  150 + if (addr < todc_info->nvram_size) { /* NVRAM */
  151 + ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
  152 + ppc_md.rtc_write_val(todc_info->nvram_data_reg, val);
  153 + } else { /* Clock Reg */
  154 + addr -= todc_info->nvram_size;
  155 + ppc_md.rtc_write_val(addr, val);
  156 + }
  157 + } else
  158 + ppc_md.rtc_write_val(addr, val);
  159 +}
  160 +
  161 +/*
  162 + * TODC routines
  163 + *
  164 + * There is some ugly stuff in that there are assumptions for the mc146818.
  165 + *
  166 + * Assumptions:
  167 + * - todc_info->control_a has the offset as mc146818 Register B reg
  168 + * - todc_info->control_b has the offset as mc146818 Register A reg
  169 + * - m48txx control reg's write enable or 'W' bit is same as
  170 + * mc146818 Register B 'SET' bit (i.e., 0x80)
  171 + *
  172 + * These assumptions were made to make the code simpler.
  173 + */
  174 +long __init
  175 +todc_time_init(void)
  176 +{
  177 + u_char cntl_b;
  178 +
  179 + if (!ppc_md.rtc_read_val)
  180 + ppc_md.rtc_read_val = ppc_md.nvram_read_val;
  181 + if (!ppc_md.rtc_write_val)
  182 + ppc_md.rtc_write_val = ppc_md.nvram_write_val;
  183 +
  184 + cntl_b = todc_read_val(todc_info->control_b);
  185 +
  186 + if (todc_info->rtc_type == TODC_TYPE_MC146818) {
  187 + if ((cntl_b & 0x70) != 0x20) {
  188 + printk(KERN_INFO "TODC real-time-clock was stopped."
  189 + " Now starting...");
  190 + cntl_b &= ~0x70;
  191 + cntl_b |= 0x20;
  192 + }
  193 +
  194 + todc_write_val(todc_info->control_b, cntl_b);
  195 + } else if (todc_info->rtc_type == TODC_TYPE_DS17285) {
  196 + u_char mode;
  197 +
  198 + mode = todc_read_val(TODC_TYPE_DS17285_CNTL_A);
  199 + /* Make sure countdown clear is not set */
  200 + mode &= ~0x40;
  201 + /* Enable oscillator, extended register set */
  202 + mode |= 0x30;
  203 + todc_write_val(TODC_TYPE_DS17285_CNTL_A, mode);
  204 +
  205 + } else if (todc_info->rtc_type == TODC_TYPE_DS1501) {
  206 + u_char month;
  207 +
  208 + todc_info->enable_read = TODC_DS1501_CNTL_B_TE;
  209 + todc_info->enable_write = TODC_DS1501_CNTL_B_TE;
  210 +
  211 + month = todc_read_val(todc_info->month);
  212 +
  213 + if ((month & 0x80) == 0x80) {
  214 + printk(KERN_INFO "TODC %s %s\n",
  215 + "real-time-clock was stopped.",
  216 + "Now starting...");
  217 + month &= ~0x80;
  218 + todc_write_val(todc_info->month, month);
  219 + }
  220 +
  221 + cntl_b &= ~TODC_DS1501_CNTL_B_TE;
  222 + todc_write_val(todc_info->control_b, cntl_b);
  223 + } else { /* must be a m48txx type */
  224 + u_char cntl_a;
  225 +
  226 + todc_info->enable_read = TODC_MK48TXX_CNTL_A_R;
  227 + todc_info->enable_write = TODC_MK48TXX_CNTL_A_W;
  228 +
  229 + cntl_a = todc_read_val(todc_info->control_a);
  230 +
  231 + /* Check & clear STOP bit in control B register */
  232 + if (cntl_b & TODC_MK48TXX_DAY_CB) {
  233 + printk(KERN_INFO "TODC %s %s\n",
  234 + "real-time-clock was stopped.",
  235 + "Now starting...");
  236 +
  237 + cntl_a |= todc_info->enable_write;
  238 + cntl_b &= ~TODC_MK48TXX_DAY_CB;/* Start Oscil */
  239 +
  240 + todc_write_val(todc_info->control_a, cntl_a);
  241 + todc_write_val(todc_info->control_b, cntl_b);
  242 + }
  243 +
  244 + /* Make sure READ & WRITE bits are cleared. */
  245 + cntl_a &= ~(todc_info->enable_write | todc_info->enable_read);
  246 + todc_write_val(todc_info->control_a, cntl_a);
  247 + }
  248 +
  249 + return 0;
  250 +}
  251 +
  252 +/*
  253 + * There is some ugly stuff in that there are assumptions that for a mc146818,
  254 + * the todc_info->control_a has the offset of the mc146818 Register B reg and
  255 + * that the register'ss 'SET' bit is the same as the m48txx's write enable
  256 + * bit in the control register of the m48txx (i.e., 0x80).
  257 + *
  258 + * It was done to make the code look simpler.
  259 + */
  260 +void
  261 +todc_get_rtc_time(struct rtc_time *tm)
  262 +{
  263 + uint year = 0, mon = 0, mday = 0, hour = 0, min = 0, sec = 0;
  264 + uint limit, i;
  265 + u_char save_control, uip = 0;
  266 + extern void GregorianDay(struct rtc_time *);
  267 +
  268 + spin_lock(&rtc_lock);
  269 + save_control = todc_read_val(todc_info->control_a);
  270 +
  271 + if (todc_info->rtc_type != TODC_TYPE_MC146818) {
  272 + limit = 1;
  273 +
  274 + switch (todc_info->rtc_type) {
  275 + case TODC_TYPE_DS1553:
  276 + case TODC_TYPE_DS1557:
  277 + case TODC_TYPE_DS1743:
  278 + case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
  279 + case TODC_TYPE_DS1747:
  280 + case TODC_TYPE_DS17285:
  281 + break;
  282 + default:
  283 + todc_write_val(todc_info->control_a,
  284 + (save_control | todc_info->enable_read));
  285 + }
  286 + } else
  287 + limit = 100000000;
  288 +
  289 + for (i=0; i<limit; i++) {
  290 + if (todc_info->rtc_type == TODC_TYPE_MC146818)
  291 + uip = todc_read_val(todc_info->RTC_FREQ_SELECT);
  292 +
  293 + sec = todc_read_val(todc_info->seconds) & 0x7f;
  294 + min = todc_read_val(todc_info->minutes) & 0x7f;
  295 + hour = todc_read_val(todc_info->hours) & 0x3f;
  296 + mday = todc_read_val(todc_info->day_of_month) & 0x3f;
  297 + mon = todc_read_val(todc_info->month) & 0x1f;
  298 + year = todc_read_val(todc_info->year) & 0xff;
  299 +
  300 + if (todc_info->rtc_type == TODC_TYPE_MC146818) {
  301 + uip |= todc_read_val(todc_info->RTC_FREQ_SELECT);
  302 + if ((uip & RTC_UIP) == 0)
  303 + break;
  304 + }
  305 + }
  306 +
  307 + if (todc_info->rtc_type != TODC_TYPE_MC146818) {
  308 + switch (todc_info->rtc_type) {
  309 + case TODC_TYPE_DS1553:
  310 + case TODC_TYPE_DS1557:
  311 + case TODC_TYPE_DS1743:
  312 + case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
  313 + case TODC_TYPE_DS1747:
  314 + case TODC_TYPE_DS17285:
  315 + break;
  316 + default:
  317 + save_control &= ~(todc_info->enable_read);
  318 + todc_write_val(todc_info->control_a, save_control);
  319 + }
  320 + }
  321 + spin_unlock(&rtc_lock);
  322 +
  323 + if ((todc_info->rtc_type != TODC_TYPE_MC146818)
  324 + || ((save_control & RTC_DM_BINARY) == 0)
  325 + || RTC_ALWAYS_BCD) {
  326 + BCD_TO_BIN(sec);
  327 + BCD_TO_BIN(min);
  328 + BCD_TO_BIN(hour);
  329 + BCD_TO_BIN(mday);
  330 + BCD_TO_BIN(mon);
  331 + BCD_TO_BIN(year);
  332 + }
  333 +
  334 + if ((year + 1900) < 1970) {
  335 + year += 100;
  336 + }
  337 +
  338 + tm->tm_sec = sec;
  339 + tm->tm_min = min;
  340 + tm->tm_hour = hour;
  341 + tm->tm_mday = mday;
  342 + tm->tm_mon = mon;
  343 + tm->tm_year = year;
  344 +
  345 + GregorianDay(tm);
  346 +}
  347 +
  348 +int
  349 +todc_set_rtc_time(struct rtc_time *tm)
  350 +{
  351 + u_char save_control, save_freq_select = 0;
  352 +
  353 + spin_lock(&rtc_lock);
  354 + save_control = todc_read_val(todc_info->control_a);
  355 +
  356 + /* Assuming MK48T59_RTC_CA_WRITE & RTC_SET are equal */
  357 + todc_write_val(todc_info->control_a,
  358 + (save_control | todc_info->enable_write));
  359 + save_control &= ~(todc_info->enable_write); /* in case it was set */
  360 +
  361 + if (todc_info->rtc_type == TODC_TYPE_MC146818) {
  362 + save_freq_select = todc_read_val(todc_info->RTC_FREQ_SELECT);
  363 + todc_write_val(todc_info->RTC_FREQ_SELECT,
  364 + save_freq_select | RTC_DIV_RESET2);
  365 + }
  366 +
  367 + if ((todc_info->rtc_type != TODC_TYPE_MC146818)
  368 + || ((save_control & RTC_DM_BINARY) == 0)
  369 + || RTC_ALWAYS_BCD) {
  370 + BIN_TO_BCD(tm->tm_sec);
  371 + BIN_TO_BCD(tm->tm_min);
  372 + BIN_TO_BCD(tm->tm_hour);
  373 + BIN_TO_BCD(tm->tm_mon);
  374 + BIN_TO_BCD(tm->tm_mday);
  375 + BIN_TO_BCD(tm->tm_year);
  376 + }
  377 +
  378 + todc_write_val(todc_info->seconds, tm->tm_sec);
  379 + todc_write_val(todc_info->minutes, tm->tm_min);
  380 + todc_write_val(todc_info->hours, tm->tm_hour);
  381 + todc_write_val(todc_info->month, tm->tm_mon);
  382 + todc_write_val(todc_info->day_of_month, tm->tm_mday);
  383 + todc_write_val(todc_info->year, tm->tm_year);
  384 +
  385 + todc_write_val(todc_info->control_a, save_control);
  386 +
  387 + if (todc_info->rtc_type == TODC_TYPE_MC146818)
  388 + todc_write_val(todc_info->RTC_FREQ_SELECT, save_freq_select);
  389 +
  390 + spin_unlock(&rtc_lock);
  391 + return 0;
  392 +}
include/asm-powerpc/todc.h
Diff comments   View file @ c220153
  1 +/*
  2 + * Definitions for the M48Txx and mc146818 series of Time of day/Real Time
  3 + * Clock chips.
  4 + *
  5 + * Author: Mark A. Greer <mgreer@mvista.com>
  6 + *
  7 + * 2001 (c) MontaVista, Software, Inc. This file is licensed under
  8 + * the terms of the GNU General Public License version 2. This program
  9 + * is licensed "as is" without any warranty of any kind, whether express
  10 + * or implied.
  11 + */
  12 +
  13 +/*
  14 + * Support for the M48T37/M48T59/.../mc146818 Real Time Clock chips.
  15 + * Purpose is to make one generic file that handles all of these chips instead
  16 + * of every platform implementing the same code over & over again.
  17 + */
  18 +
  19 +#ifndef __PPC_KERNEL_TODC_H
  20 +#define __PPC_KERNEL_TODC_H
  21 +
  22 +typedef struct {
  23 + uint rtc_type; /* your particular chip */
  24 +
  25 + /*
  26 + * Following are the addresses of the AS0, AS1, and DATA registers
  27 + * of these chips. Note that these are board-specific.
  28 + */
  29 + unsigned int nvram_as0;
  30 + unsigned int nvram_as1;
  31 + unsigned int nvram_data;
  32 +
  33 + /*
  34 + * Define bits to stop external set of regs from changing so
  35 + * the chip can be read/written reliably.
  36 + */
  37 + unsigned char enable_read;
  38 + unsigned char enable_write;
  39 +
  40 + /*
  41 + * Following is the number of AS0 address bits. This is normally
  42 + * 8 but some bad hardware routes address lines incorrectly.
  43 + */
  44 + int as0_bits;
  45 +
  46 + int nvram_size; /* Size of NVRAM on chip */
  47 + int sw_flags; /* Software control flags */
  48 +
  49 + /* Following are the register offsets for the particular chip */
  50 + int year;
  51 + int month;
  52 + int day_of_month;
  53 + int day_of_week;
  54 + int hours;
  55 + int minutes;
  56 + int seconds;
  57 + int control_b;
  58 + int control_a;
  59 + int watchdog;
  60 + int interrupts;
  61 + int alarm_date;
  62 + int alarm_hour;
  63 + int alarm_minutes;
  64 + int alarm_seconds;
  65 + int century;
  66 + int flags;
  67 +
  68 + /*
  69 + * Some RTC chips have their NVRAM buried behind a addr/data pair of
  70 + * regs on the first level/clock registers. The following fields
  71 + * are the addresses for those addr/data regs.
  72 + */
  73 + int nvram_addr_reg;
  74 + int nvram_data_reg;
  75 +} todc_info_t;
  76 +
  77 +/*
  78 + * Define the types of TODC/RTC variants that are supported in
  79 + * arch/ppc/kernel/todc_time.c
  80 + * Make a new one of these for any chip somehow differs from what's already
  81 + * defined. That way, if you ever need to put in code to touch those
  82 + * bits/registers in todc_time.c, you can put it inside an
  83 + * 'if (todc_info->rtc_type == TODC_TYPE_XXX)' so you won't break
  84 + * anyone else.
  85 + */
  86 +#define TODC_TYPE_MK48T35 1
  87 +#define TODC_TYPE_MK48T37 2
  88 +#define TODC_TYPE_MK48T59 3
  89 +#define TODC_TYPE_DS1693 4 /* Dallas DS1693 RTC */
  90 +#define TODC_TYPE_DS1743 5 /* Dallas DS1743 RTC */
  91 +#define TODC_TYPE_DS1746 6 /* Dallas DS1746 RTC */
  92 +#define TODC_TYPE_DS1747 7 /* Dallas DS1747 RTC */
  93 +#define TODC_TYPE_DS1501 8 /* Dallas DS1501 RTC */
  94 +#define TODC_TYPE_DS1643 9 /* Dallas DS1643 RTC */
  95 +#define TODC_TYPE_PC97307 10 /* PC97307 internal RTC */
  96 +#define TODC_TYPE_DS1557 11 /* Dallas DS1557 RTC */
  97 +#define TODC_TYPE_DS17285 12 /* Dallas DS17285 RTC */
  98 +#define TODC_TYPE_DS1553 13 /* Dallas DS1553 RTC */
  99 +#define TODC_TYPE_MC146818 100 /* Leave room for m48txx's */
  100 +
  101 +/*
  102 + * Bit to clear/set to enable reads/writes to the chip
  103 + */
  104 +#define TODC_MK48TXX_CNTL_A_R 0x40
  105 +#define TODC_MK48TXX_CNTL_A_W 0x80
  106 +#define TODC_MK48TXX_DAY_CB 0x80
  107 +
  108 +#define TODC_DS1501_CNTL_B_TE 0x80
  109 +
  110 +/*
  111 + * Define flag bits used by todc routines.
  112 + */
  113 +#define TODC_FLAG_2_LEVEL_NVRAM 0x00000001
  114 +
  115 +/*
  116 + * Define the values for the various RTC's that should to into the todc_info
  117 + * table.
  118 + * Note: The XXX_NVRAM_SIZE, XXX_NVRAM_ADDR_REG, and XXX_NVRAM_DATA_REG only
  119 + * matter if XXX_SW_FLAGS has TODC_FLAG_2_LEVEL_NVRAM set.
  120 + */
  121 +#define TODC_TYPE_MK48T35_NVRAM_SIZE 0x7ff8
  122 +#define TODC_TYPE_MK48T35_SW_FLAGS 0
  123 +#define TODC_TYPE_MK48T35_YEAR 0x7fff
  124 +#define TODC_TYPE_MK48T35_MONTH 0x7ffe
  125 +#define TODC_TYPE_MK48T35_DOM 0x7ffd /* Day of Month */
  126 +#define TODC_TYPE_MK48T35_DOW 0x7ffc /* Day of Week */
  127 +#define TODC_TYPE_MK48T35_HOURS 0x7ffb
  128 +#define TODC_TYPE_MK48T35_MINUTES 0x7ffa
  129 +#define TODC_TYPE_MK48T35_SECONDS 0x7ff9
  130 +#define TODC_TYPE_MK48T35_CNTL_B 0x7ff9
  131 +#define TODC_TYPE_MK48T35_CNTL_A 0x7ff8
  132 +#define TODC_TYPE_MK48T35_WATCHDOG 0x0000
  133 +#define TODC_TYPE_MK48T35_INTERRUPTS 0x0000
  134 +#define TODC_TYPE_MK48T35_ALARM_DATE 0x0000
  135 +#define TODC_TYPE_MK48T35_ALARM_HOUR 0x0000
  136 +#define TODC_TYPE_MK48T35_ALARM_MINUTES 0x0000
  137 +#define TODC_TYPE_MK48T35_ALARM_SECONDS 0x0000
  138 +#define TODC_TYPE_MK48T35_CENTURY 0x0000
  139 +#define TODC_TYPE_MK48T35_FLAGS 0x0000
  140 +#define TODC_TYPE_MK48T35_NVRAM_ADDR_REG 0
  141 +#define TODC_TYPE_MK48T35_NVRAM_DATA_REG 0
  142 +
  143 +#define TODC_TYPE_MK48T37_NVRAM_SIZE 0x7ff0
  144 +#define TODC_TYPE_MK48T37_SW_FLAGS 0
  145 +#define TODC_TYPE_MK48T37_YEAR 0x7fff
  146 +#define TODC_TYPE_MK48T37_MONTH 0x7ffe
  147 +#define TODC_TYPE_MK48T37_DOM 0x7ffd /* Day of Month */
  148 +#define TODC_TYPE_MK48T37_DOW 0x7ffc /* Day of Week */
  149 +#define TODC_TYPE_MK48T37_HOURS 0x7ffb
  150 +#define TODC_TYPE_MK48T37_MINUTES 0x7ffa
  151 +#define TODC_TYPE_MK48T37_SECONDS 0x7ff9
  152 +#define TODC_TYPE_MK48T37_CNTL_B 0x7ff9
  153 +#define TODC_TYPE_MK48T37_CNTL_A 0x7ff8
  154 +#define TODC_TYPE_MK48T37_WATCHDOG 0x7ff7
  155 +#define TODC_TYPE_MK48T37_INTERRUPTS 0x7ff6
  156 +#define TODC_TYPE_MK48T37_ALARM_DATE 0x7ff5
  157 +#define TODC_TYPE_MK48T37_ALARM_HOUR 0x7ff4
  158 +#define TODC_TYPE_MK48T37_ALARM_MINUTES 0x7ff3
  159 +#define TODC_TYPE_MK48T37_ALARM_SECONDS 0x7ff2
  160 +#define TODC_TYPE_MK48T37_CENTURY 0x7ff1
  161 +#define TODC_TYPE_MK48T37_FLAGS 0x7ff0
  162 +#define TODC_TYPE_MK48T37_NVRAM_ADDR_REG 0
  163 +#define TODC_TYPE_MK48T37_NVRAM_DATA_REG 0
  164 +
  165 +#define TODC_TYPE_MK48T59_NVRAM_SIZE 0x1ff0
  166 +#define TODC_TYPE_MK48T59_SW_FLAGS 0
  167 +#define TODC_TYPE_MK48T59_YEAR 0x1fff
  168 +#define TODC_TYPE_MK48T59_MONTH 0x1ffe
  169 +#define TODC_TYPE_MK48T59_DOM 0x1ffd /* Day of Month */
  170 +#define TODC_TYPE_MK48T59_DOW 0x1ffc /* Day of Week */
  171 +#define TODC_TYPE_MK48T59_HOURS 0x1ffb
  172 +#define TODC_TYPE_MK48T59_MINUTES 0x1ffa
  173 +#define TODC_TYPE_MK48T59_SECONDS 0x1ff9
  174 +#define TODC_TYPE_MK48T59_CNTL_B 0x1ff9
  175 +#define TODC_TYPE_MK48T59_CNTL_A 0x1ff8
  176 +#define TODC_TYPE_MK48T59_WATCHDOG 0x1fff
  177 +#define TODC_TYPE_MK48T59_INTERRUPTS 0x1fff
  178 +#define TODC_TYPE_MK48T59_ALARM_DATE 0x1fff
  179 +#define TODC_TYPE_MK48T59_ALARM_HOUR 0x1fff
  180 +#define TODC_TYPE_MK48T59_ALARM_MINUTES 0x1fff
  181 +#define TODC_TYPE_MK48T59_ALARM_SECONDS 0x1fff
  182 +#define TODC_TYPE_MK48T59_CENTURY 0x1fff
  183 +#define TODC_TYPE_MK48T59_FLAGS 0x1fff
  184 +#define TODC_TYPE_MK48T59_NVRAM_ADDR_REG 0
  185 +#define TODC_TYPE_MK48T59_NVRAM_DATA_REG 0
  186 +
  187 +#define TODC_TYPE_DS1501_NVRAM_SIZE 0x100
  188 +#define TODC_TYPE_DS1501_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM
  189 +#define TODC_TYPE_DS1501_YEAR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x06)
  190 +#define TODC_TYPE_DS1501_MONTH (TODC_TYPE_DS1501_NVRAM_SIZE + 0x05)
  191 +#define TODC_TYPE_DS1501_DOM (TODC_TYPE_DS1501_NVRAM_SIZE + 0x04)
  192 +#define TODC_TYPE_DS1501_DOW (TODC_TYPE_DS1501_NVRAM_SIZE + 0x03)
  193 +#define TODC_TYPE_DS1501_HOURS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x02)
  194 +#define TODC_TYPE_DS1501_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x01)
  195 +#define TODC_TYPE_DS1501_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x00)
  196 +#define TODC_TYPE_DS1501_CNTL_B (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
  197 +#define TODC_TYPE_DS1501_CNTL_A (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
  198 +#define TODC_TYPE_DS1501_WATCHDOG (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
  199 +#define TODC_TYPE_DS1501_INTERRUPTS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
  200 +#define TODC_TYPE_DS1501_ALARM_DATE (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0b)
  201 +#define TODC_TYPE_DS1501_ALARM_HOUR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0a)
  202 +#define TODC_TYPE_DS1501_ALARM_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x09)
  203 +#define TODC_TYPE_DS1501_ALARM_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x08)
  204 +#define TODC_TYPE_DS1501_CENTURY (TODC_TYPE_DS1501_NVRAM_SIZE + 0x07)
  205 +#define TODC_TYPE_DS1501_FLAGS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
  206 +#define TODC_TYPE_DS1501_NVRAM_ADDR_REG 0x10
  207 +#define TODC_TYPE_DS1501_NVRAM_DATA_REG 0x13
  208 +
  209 +#define TODC_TYPE_DS1553_NVRAM_SIZE 0x1ff0
  210 +#define TODC_TYPE_DS1553_SW_FLAGS 0
  211 +#define TODC_TYPE_DS1553_YEAR 0x1fff
  212 +#define TODC_TYPE_DS1553_MONTH 0x1ffe
  213 +#define TODC_TYPE_DS1553_DOM 0x1ffd /* Day of Month */
  214 +#define TODC_TYPE_DS1553_DOW 0x1ffc /* Day of Week */
  215 +#define TODC_TYPE_DS1553_HOURS 0x1ffb
  216 +#define TODC_TYPE_DS1553_MINUTES 0x1ffa
  217 +#define TODC_TYPE_DS1553_SECONDS 0x1ff9
  218 +#define TODC_TYPE_DS1553_CNTL_B 0x1ff9
  219 +#define TODC_TYPE_DS1553_CNTL_A 0x1ff8 /* control_a R/W regs */
  220 +#define TODC_TYPE_DS1553_WATCHDOG 0x1ff7
  221 +#define TODC_TYPE_DS1553_INTERRUPTS 0x1ff6
  222 +#define TODC_TYPE_DS1553_ALARM_DATE 0x1ff5
  223 +#define TODC_TYPE_DS1553_ALARM_HOUR 0x1ff4
  224 +#define TODC_TYPE_DS1553_ALARM_MINUTES 0x1ff3
  225 +#define TODC_TYPE_DS1553_ALARM_SECONDS 0x1ff2
  226 +#define TODC_TYPE_DS1553_CENTURY 0x1ff8
  227 +#define TODC_TYPE_DS1553_FLAGS 0x1ff0
  228 +#define TODC_TYPE_DS1553_NVRAM_ADDR_REG 0
  229 +#define TODC_TYPE_DS1553_NVRAM_DATA_REG 0
  230 +
  231 +#define TODC_TYPE_DS1557_NVRAM_SIZE 0x7fff0
  232 +#define TODC_TYPE_DS1557_SW_FLAGS 0
  233 +#define TODC_TYPE_DS1557_YEAR 0x7ffff
  234 +#define TODC_TYPE_DS1557_MONTH 0x7fffe
  235 +#define TODC_TYPE_DS1557_DOM 0x7fffd /* Day of Month */
  236 +#define TODC_TYPE_DS1557_DOW 0x7fffc /* Day of Week */
  237 +#define TODC_TYPE_DS1557_HOURS 0x7fffb
  238 +#define TODC_TYPE_DS1557_MINUTES 0x7fffa
  239 +#define TODC_TYPE_DS1557_SECONDS 0x7fff9
  240 +#define TODC_TYPE_DS1557_CNTL_B 0x7fff9
  241 +#define TODC_TYPE_DS1557_CNTL_A 0x7fff8 /* control_a R/W regs */
  242 +#define TODC_TYPE_DS1557_WATCHDOG 0x7fff7
  243 +#define TODC_TYPE_DS1557_INTERRUPTS 0x7fff6
  244 +#define TODC_TYPE_DS1557_ALARM_DATE 0x7fff5
  245 +#define TODC_TYPE_DS1557_ALARM_HOUR 0x7fff4
  246 +#define TODC_TYPE_DS1557_ALARM_MINUTES 0x7fff3
  247 +#define TODC_TYPE_DS1557_ALARM_SECONDS 0x7fff2
  248 +#define TODC_TYPE_DS1557_CENTURY 0x7fff8
  249 +#define TODC_TYPE_DS1557_FLAGS 0x7fff0
  250 +#define TODC_TYPE_DS1557_NVRAM_ADDR_REG 0
  251 +#define TODC_TYPE_DS1557_NVRAM_DATA_REG 0
  252 +
  253 +#define TODC_TYPE_DS1643_NVRAM_SIZE 0x1ff8
  254 +#define TODC_TYPE_DS1643_SW_FLAGS 0
  255 +#define TODC_TYPE_DS1643_YEAR 0x1fff
  256 +#define TODC_TYPE_DS1643_MONTH 0x1ffe
  257 +#define TODC_TYPE_DS1643_DOM 0x1ffd /* Day of Month */
  258 +#define TODC_TYPE_DS1643_DOW 0x1ffc /* Day of Week */
  259 +#define TODC_TYPE_DS1643_HOURS 0x1ffb
  260 +#define TODC_TYPE_DS1643_MINUTES 0x1ffa
  261 +#define TODC_TYPE_DS1643_SECONDS 0x1ff9
  262 +#define TODC_TYPE_DS1643_CNTL_B 0x1ff9
  263 +#define TODC_TYPE_DS1643_CNTL_A 0x1ff8 /* control_a R/W regs */
  264 +#define TODC_TYPE_DS1643_WATCHDOG 0x1fff
  265 +#define TODC_TYPE_DS1643_INTERRUPTS 0x1fff
  266 +#define TODC_TYPE_DS1643_ALARM_DATE 0x1fff
  267 +#define TODC_TYPE_DS1643_ALARM_HOUR 0x1fff
  268 +#define TODC_TYPE_DS1643_ALARM_MINUTES 0x1fff
  269 +#define TODC_TYPE_DS1643_ALARM_SECONDS 0x1fff
  270 +#define TODC_TYPE_DS1643_CENTURY 0x1ff8
  271 +#define TODC_TYPE_DS1643_FLAGS 0x1fff
  272 +#define TODC_TYPE_DS1643_NVRAM_ADDR_REG 0
  273 +#define TODC_TYPE_DS1643_NVRAM_DATA_REG 0
  274 +
  275 +#define TODC_TYPE_DS1693_NVRAM_SIZE 0 /* Not handled yet */
  276 +#define TODC_TYPE_DS1693_SW_FLAGS 0
  277 +#define TODC_TYPE_DS1693_YEAR 0x09
  278 +#define TODC_TYPE_DS1693_MONTH 0x08
  279 +#define TODC_TYPE_DS1693_DOM 0x07 /* Day of Month */
  280 +#define TODC_TYPE_DS1693_DOW 0x06 /* Day of Week */
  281 +#define TODC_TYPE_DS1693_HOURS 0x04
  282 +#define TODC_TYPE_DS1693_MINUTES 0x02
  283 +#define TODC_TYPE_DS1693_SECONDS 0x00
  284 +#define TODC_TYPE_DS1693_CNTL_B 0x0b
  285 +#define TODC_TYPE_DS1693_CNTL_A 0x0a
  286 +#define TODC_TYPE_DS1693_WATCHDOG 0xff
  287 +#define TODC_TYPE_DS1693_INTERRUPTS 0xff
  288 +#define TODC_TYPE_DS1693_ALARM_DATE 0x49
  289 +#define TODC_TYPE_DS1693_ALARM_HOUR 0x05
  290 +#define TODC_TYPE_DS1693_ALARM_MINUTES 0x03
  291 +#define TODC_TYPE_DS1693_ALARM_SECONDS 0x01
  292 +#define TODC_TYPE_DS1693_CENTURY 0x48
  293 +#define TODC_TYPE_DS1693_FLAGS 0xff
  294 +#define TODC_TYPE_DS1693_NVRAM_ADDR_REG 0
  295 +#define TODC_TYPE_DS1693_NVRAM_DATA_REG 0
  296 +
  297 +#define TODC_TYPE_DS1743_NVRAM_SIZE 0x1ff8
  298 +#define TODC_TYPE_DS1743_SW_FLAGS 0
  299 +#define TODC_TYPE_DS1743_YEAR 0x1fff
  300 +#define TODC_TYPE_DS1743_MONTH 0x1ffe
  301 +#define TODC_TYPE_DS1743_DOM 0x1ffd /* Day of Month */
  302 +#define TODC_TYPE_DS1743_DOW 0x1ffc /* Day of Week */
  303 +#define TODC_TYPE_DS1743_HOURS 0x1ffb
  304 +#define TODC_TYPE_DS1743_MINUTES 0x1ffa
  305 +#define TODC_TYPE_DS1743_SECONDS 0x1ff9
  306 +#define TODC_TYPE_DS1743_CNTL_B 0x1ff9
  307 +#define TODC_TYPE_DS1743_CNTL_A 0x1ff8 /* control_a R/W regs */
  308 +#define TODC_TYPE_DS1743_WATCHDOG 0x1fff
  309 +#define TODC_TYPE_DS1743_INTERRUPTS 0x1fff
  310 +#define TODC_TYPE_DS1743_ALARM_DATE 0x1fff
  311 +#define TODC_TYPE_DS1743_ALARM_HOUR 0x1fff
  312 +#define TODC_TYPE_DS1743_ALARM_MINUTES 0x1fff
  313 +#define TODC_TYPE_DS1743_ALARM_SECONDS 0x1fff
  314 +#define TODC_TYPE_DS1743_CENTURY 0x1ff8
  315 +#define TODC_TYPE_DS1743_FLAGS 0x1fff
  316 +#define TODC_TYPE_DS1743_NVRAM_ADDR_REG 0
  317 +#define TODC_TYPE_DS1743_NVRAM_DATA_REG 0
  318 +
  319 +#define TODC_TYPE_DS1746_NVRAM_SIZE 0x1fff8
  320 +#define TODC_TYPE_DS1746_SW_FLAGS 0
  321 +#define TODC_TYPE_DS1746_YEAR 0x1ffff
  322 +#define TODC_TYPE_DS1746_MONTH 0x1fffe
  323 +#define TODC_TYPE_DS1746_DOM 0x1fffd /* Day of Month */
  324 +#define TODC_TYPE_DS1746_DOW 0x1fffc /* Day of Week */
  325 +#define TODC_TYPE_DS1746_HOURS 0x1fffb
  326 +#define TODC_TYPE_DS1746_MINUTES 0x1fffa
  327 +#define TODC_TYPE_DS1746_SECONDS 0x1fff9
  328 +#define TODC_TYPE_DS1746_CNTL_B 0x1fff9
  329 +#define TODC_TYPE_DS1746_CNTL_A 0x1fff8 /* control_a R/W regs */
  330 +#define TODC_TYPE_DS1746_WATCHDOG 0x00000
  331 +#define TODC_TYPE_DS1746_INTERRUPTS 0x00000
  332 +#define TODC_TYPE_DS1746_ALARM_DATE 0x00000
  333 +#define TODC_TYPE_DS1746_ALARM_HOUR 0x00000
  334 +#define TODC_TYPE_DS1746_ALARM_MINUTES 0x00000
  335 +#define TODC_TYPE_DS1746_ALARM_SECONDS 0x00000
  336 +#define TODC_TYPE_DS1746_CENTURY 0x00000
  337 +#define TODC_TYPE_DS1746_FLAGS 0x00000
  338 +#define TODC_TYPE_DS1746_NVRAM_ADDR_REG 0
  339 +#define TODC_TYPE_DS1746_NVRAM_DATA_REG 0
  340 +
  341 +#define TODC_TYPE_DS1747_NVRAM_SIZE 0x7fff8
  342 +#define TODC_TYPE_DS1747_SW_FLAGS 0
  343 +#define TODC_TYPE_DS1747_YEAR 0x7ffff
  344 +#define TODC_TYPE_DS1747_MONTH 0x7fffe
  345 +#define TODC_TYPE_DS1747_DOM 0x7fffd /* Day of Month */
  346 +#define TODC_TYPE_DS1747_DOW 0x7fffc /* Day of Week */
  347 +#define TODC_TYPE_DS1747_HOURS 0x7fffb
  348 +#define TODC_TYPE_DS1747_MINUTES 0x7fffa
  349 +#define TODC_TYPE_DS1747_SECONDS 0x7fff9
  350 +#define TODC_TYPE_DS1747_CNTL_B 0x7fff9
  351 +#define TODC_TYPE_DS1747_CNTL_A 0x7fff8 /* control_a R/W regs */
  352 +#define TODC_TYPE_DS1747_WATCHDOG 0x00000
  353 +#define TODC_TYPE_DS1747_INTERRUPTS 0x00000
  354 +#define TODC_TYPE_DS1747_ALARM_DATE 0x00000
  355 +#define TODC_TYPE_DS1747_ALARM_HOUR 0x00000
  356 +#define TODC_TYPE_DS1747_ALARM_MINUTES 0x00000
  357 +#define TODC_TYPE_DS1747_ALARM_SECONDS 0x00000
  358 +#define TODC_TYPE_DS1747_CENTURY 0x00000
  359 +#define TODC_TYPE_DS1747_FLAGS 0x00000
  360 +#define TODC_TYPE_DS1747_NVRAM_ADDR_REG 0
  361 +#define TODC_TYPE_DS1747_NVRAM_DATA_REG 0
  362 +
  363 +#define TODC_TYPE_DS17285_NVRAM_SIZE (0x1000-0x80) /* 4Kx8 NVRAM (minus RTC regs) */
  364 +#define TODC_TYPE_DS17285_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM
  365 +#define TODC_TYPE_DS17285_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x00)
  366 +#define TODC_TYPE_DS17285_ALARM_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x01)
  367 +#define TODC_TYPE_DS17285_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x02)
  368 +#define TODC_TYPE_DS17285_ALARM_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x03)
  369 +#define TODC_TYPE_DS17285_HOURS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x04)
  370 +#define TODC_TYPE_DS17285_ALARM_HOUR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x05)
  371 +#define TODC_TYPE_DS17285_DOW (TODC_TYPE_DS17285_NVRAM_SIZE + 0x06)
  372 +#define TODC_TYPE_DS17285_DOM (TODC_TYPE_DS17285_NVRAM_SIZE + 0x07)
  373 +#define TODC_TYPE_DS17285_MONTH (TODC_TYPE_DS17285_NVRAM_SIZE + 0x08)
  374 +#define TODC_TYPE_DS17285_YEAR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x09)
  375 +#define TODC_TYPE_DS17285_CNTL_A (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0A)
  376 +#define TODC_TYPE_DS17285_CNTL_B (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0B)
  377 +#define TODC_TYPE_DS17285_CNTL_C (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0C)
  378 +#define TODC_TYPE_DS17285_CNTL_D (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0D)
  379 +#define TODC_TYPE_DS17285_WATCHDOG 0
  380 +#define TODC_TYPE_DS17285_INTERRUPTS 0
  381 +#define TODC_TYPE_DS17285_ALARM_DATE 0
  382 +#define TODC_TYPE_DS17285_CENTURY 0
  383 +#define TODC_TYPE_DS17285_FLAGS 0
  384 +#define TODC_TYPE_DS17285_NVRAM_ADDR_REG 0x50
  385 +#define TODC_TYPE_DS17285_NVRAM_DATA_REG 0x53
  386 +
  387 +#define TODC_TYPE_MC146818_NVRAM_SIZE 0 /* XXXX */
  388 +#define TODC_TYPE_MC146818_SW_FLAGS 0
  389 +#define TODC_TYPE_MC146818_YEAR 0x09
  390 +#define TODC_TYPE_MC146818_MONTH 0x08
  391 +#define TODC_TYPE_MC146818_DOM 0x07 /* Day of Month */
  392 +#define TODC_TYPE_MC146818_DOW 0x06 /* Day of Week */
  393 +#define TODC_TYPE_MC146818_HOURS 0x04
  394 +#define TODC_TYPE_MC146818_MINUTES 0x02
  395 +#define TODC_TYPE_MC146818_SECONDS 0x00
  396 +#define TODC_TYPE_MC146818_CNTL_B 0x0a
  397 +#define TODC_TYPE_MC146818_CNTL_A 0x0b /* control_a R/W regs */
  398 +#define TODC_TYPE_MC146818_WATCHDOG 0
  399 +#define TODC_TYPE_MC146818_INTERRUPTS 0x0c
  400 +#define TODC_TYPE_MC146818_ALARM_DATE 0xff
  401 +#define TODC_TYPE_MC146818_ALARM_HOUR 0x05
  402 +#define TODC_TYPE_MC146818_ALARM_MINUTES 0x03
  403 +#define TODC_TYPE_MC146818_ALARM_SECONDS 0x01
  404 +#define TODC_TYPE_MC146818_CENTURY 0xff
  405 +#define TODC_TYPE_MC146818_FLAGS 0xff
  406 +#define TODC_TYPE_MC146818_NVRAM_ADDR_REG 0
  407 +#define TODC_TYPE_MC146818_NVRAM_DATA_REG 0
  408 +
  409 +#define TODC_TYPE_PC97307_NVRAM_SIZE 0 /* No NVRAM? */
  410 +#define TODC_TYPE_PC97307_SW_FLAGS 0
  411 +#define TODC_TYPE_PC97307_YEAR 0x09
  412 +#define TODC_TYPE_PC97307_MONTH 0x08
  413 +#define TODC_TYPE_PC97307_DOM 0x07 /* Day of Month */
  414 +#define TODC_TYPE_PC97307_DOW 0x06 /* Day of Week */
  415 +#define TODC_TYPE_PC97307_HOURS 0x04
  416 +#define TODC_TYPE_PC97307_MINUTES 0x02
  417 +#define TODC_TYPE_PC97307_SECONDS 0x00
  418 +#define TODC_TYPE_PC97307_CNTL_B 0x0a
  419 +#define TODC_TYPE_PC97307_CNTL_A 0x0b /* control_a R/W regs */
  420 +#define TODC_TYPE_PC97307_WATCHDOG 0x0c
  421 +#define TODC_TYPE_PC97307_INTERRUPTS 0x0d
  422 +#define TODC_TYPE_PC97307_ALARM_DATE 0xff
  423 +#define TODC_TYPE_PC97307_ALARM_HOUR 0x05
  424 +#define TODC_TYPE_PC97307_ALARM_MINUTES 0x03
  425 +#define TODC_TYPE_PC97307_ALARM_SECONDS 0x01
  426 +#define TODC_TYPE_PC97307_CENTURY 0xff
  427 +#define TODC_TYPE_PC97307_FLAGS 0xff
  428 +#define TODC_TYPE_PC97307_NVRAM_ADDR_REG 0
  429 +#define TODC_TYPE_PC97307_NVRAM_DATA_REG 0
  430 +
  431 +/*
  432 + * Define macros to allocate and init the todc_info_t table that will
  433 + * be used by the todc_time.c routines.
  434 + */
  435 +#define TODC_ALLOC() \
  436 + static todc_info_t todc_info_alloc; \
  437 + todc_info_t *todc_info = &todc_info_alloc;
  438 +
  439 +#define TODC_INIT(clock_type, as0, as1, data, bits) { \
  440 + todc_info->rtc_type = clock_type; \
  441 + \
  442 + todc_info->nvram_as0 = (unsigned int)(as0); \
  443 + todc_info->nvram_as1 = (unsigned int)(as1); \
  444 + todc_info->nvram_data = (unsigned int)(data); \
  445 + \
  446 + todc_info->as0_bits = (bits); \
  447 + \
  448 + todc_info->nvram_size = clock_type ##_NVRAM_SIZE; \
  449 + todc_info->sw_flags = clock_type ##_SW_FLAGS; \
  450 + \
  451 + todc_info->year = clock_type ##_YEAR; \
  452 + todc_info->month = clock_type ##_MONTH; \
  453 + todc_info->day_of_month = clock_type ##_DOM; \
  454 + todc_info->day_of_week = clock_type ##_DOW; \
  455 + todc_info->hours = clock_type ##_HOURS; \
  456 + todc_info->minutes = clock_type ##_MINUTES; \
  457 + todc_info->seconds = clock_type ##_SECONDS; \
  458 + todc_info->control_b = clock_type ##_CNTL_B; \
  459 + todc_info->control_a = clock_type ##_CNTL_A; \
  460 + todc_info->watchdog = clock_type ##_WATCHDOG; \
  461 + todc_info->interrupts = clock_type ##_INTERRUPTS; \
  462 + todc_info->alarm_date = clock_type ##_ALARM_DATE; \
  463 + todc_info->alarm_hour = clock_type ##_ALARM_HOUR; \
  464 + todc_info->alarm_minutes = clock_type ##_ALARM_MINUTES; \
  465 + todc_info->alarm_seconds = clock_type ##_ALARM_SECONDS; \
  466 + todc_info->century = clock_type ##_CENTURY; \
  467 + todc_info->flags = clock_type ##_FLAGS; \
  468 + \
  469 + todc_info->nvram_addr_reg = clock_type ##_NVRAM_ADDR_REG; \
  470 + todc_info->nvram_data_reg = clock_type ##_NVRAM_DATA_REG; \
  471 +}
  472 +
  473 +extern todc_info_t *todc_info;
  474 +
  475 +unsigned char todc_direct_read_val(int addr);
  476 +void todc_direct_write_val(int addr, unsigned char val);
  477 +unsigned char todc_m48txx_read_val(int addr);
  478 +void todc_m48txx_write_val(int addr, unsigned char val);
  479 +unsigned char todc_mc146818_read_val(int addr);
  480 +void todc_mc146818_write_val(int addr, unsigned char val);
  481 +
  482 +long todc_time_init(void);
  483 +void todc_get_rtc_time(struct rtc_time *);
  484 +int todc_set_rtc_time(struct rtc_time *);
  485 +void todc_calibrate_decr(void);
  486 +
  487 +#endif /* __PPC_KERNEL_TODC_H */