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Commit c3567f8a359b7917dcffa442301f88ed0a75211f

Authored by Noam Camus
Committed by Linus Torvalds
1 parent d5d04bb48f
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

ARC: SMP failed to boot due to missing IVT setup 

Commit 05b016ecf5e7a "ARC: Setup Vector Table Base in early boot" moved
the Interrupt vector Table setup out of arc_init_IRQ() which is called
for all CPUs, to entry point of boot cpu only, breaking booting of others.

Fix by adding the same to entry point of non-boot CPUs too.

read_arc_build_cfg_regs() printing IVT Base Register didn't help the
casue since it prints a synthetic value if zero which is totally bogus,
so fix that to print the exact Register.

[vgupta: Remove the now stale comment from header of arc_init_IRQ and
also added the commentary for halt-on-reset]

Cc: Gilad Ben-Yossef <gilad@benyossef.com>
Cc: Cc: <stable@vger.kernel.org> #3.11
Signed-off-by: Noam Camus <noamc@ezchip.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Showing 4 changed files with 5 additions and 5 deletions Side-by-side Diff

arch/arc/include/asm/sections.h
Diff comments   View file @ c3567f8
... ... @@ -11,7 +11,6 @@
11 11  
12 12 #include <asm-generic/sections.h>
13 13  
14   -extern char _int_vec_base_lds[];
15 14 extern char __arc_dccm_base[];
16 15 extern char __dtb_start[];
17 16  
arch/arc/kernel/head.S
Diff comments   View file @ c3567f8
... ... @@ -34,6 +34,9 @@
34 34 ; IDENTITY Reg [ 3 2 1 0 ]
35 35 ; (cpu-id) ^^^ => Zero for UP ARC700
36 36 ; => #Core-ID if SMP (Master 0)
  37 + ; Note that non-boot CPUs might not land here if halt-on-reset and
  38 + ; instead breath life from @first_lines_of_secondary, but we still
  39 + ; need to make sure only boot cpu takes this path.
37 40 GET_CPU_ID r5
38 41 cmp r5, 0
39 42 jnz arc_platform_smp_wait_to_boot
... ... @@ -97,6 +100,8 @@
97 100 .globl first_lines_of_secondary
98 101  
99 102 first_lines_of_secondary:
  103 +
  104 + sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
100 105  
101 106 ; setup per-cpu idle task as "current" on this CPU
102 107 ld r0, [@secondary_idle_tsk]
arch/arc/kernel/irq.c
Diff comments   View file @ c3567f8
... ... @@ -24,7 +24,6 @@
24 24 * -Needed for each CPU (hence not foldable into init_IRQ)
25 25 *
26 26 * what it does ?
27   - * -setup Vector Table Base Reg - in case Linux not linked at 0x8000_0000
28 27 * -Disable all IRQs (on CPU side)
29 28 * -Optionally, setup the High priority Interrupts as Level 2 IRQs
30 29 */
arch/arc/kernel/setup.c
Diff comments   View file @ c3567f8
... ... @@ -47,10 +47,7 @@
47 47 READ_BCR(AUX_IDENTITY, cpu->core);
48 48  
49 49 cpu->timers = read_aux_reg(ARC_REG_TIMERS_BCR);
50   -
51 50 cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
52   - if (cpu->vec_base == 0)
53   - cpu->vec_base = (unsigned int)_int_vec_base_lds;
54 51  
55 52 READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space);
56 53 cpu->uncached_base = uncached_space.start << 24;