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Commit c5a48ff81e25c8585dae981a6cc19ed55788cadf

Authored by Jayachandran C
Committed by Ralf Baechle
1 parent 51d1eac0cd
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

MIPS: Netlogic: Remove NETLOGIC_ prefix 

Remove NETLOGIC_ prefix from gpio register definitions, this will
bring it in-line with the other Netlogic headers.

Having NETLOGIC prefix here is misleading because these are XLR/XLS
specific register definitions.

Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3754/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Showing 2 changed files with 31 additions and 30 deletions Side-by-side Diff

arch/mips/include/asm/netlogic/xlr/gpio.h
Diff comments   View file @ c5a48ff
... ... @@ -35,40 +35,41 @@
35 35 #ifndef _ASM_NLM_GPIO_H
36 36 #define _ASM_NLM_GPIO_H
37 37  
38   -#define NETLOGIC_GPIO_INT_EN_REG 0
39   -#define NETLOGIC_GPIO_INPUT_INVERSION_REG 1
40   -#define NETLOGIC_GPIO_IO_DIR_REG 2
41   -#define NETLOGIC_GPIO_IO_DATA_WR_REG 3
42   -#define NETLOGIC_GPIO_IO_DATA_RD_REG 4
  38 +#define GPIO_INT_EN_REG 0
  39 +#define GPIO_INPUT_INVERSION_REG 1
  40 +#define GPIO_IO_DIR_REG 2
  41 +#define GPIO_IO_DATA_WR_REG 3
  42 +#define GPIO_IO_DATA_RD_REG 4
43 43  
44   -#define NETLOGIC_GPIO_SWRESET_REG 8
45   -#define NETLOGIC_GPIO_DRAM1_CNTRL_REG 9
46   -#define NETLOGIC_GPIO_DRAM1_RATIO_REG 10
47   -#define NETLOGIC_GPIO_DRAM1_RESET_REG 11
48   -#define NETLOGIC_GPIO_DRAM1_STATUS_REG 12
49   -#define NETLOGIC_GPIO_DRAM2_CNTRL_REG 13
50   -#define NETLOGIC_GPIO_DRAM2_RATIO_REG 14
51   -#define NETLOGIC_GPIO_DRAM2_RESET_REG 15
52   -#define NETLOGIC_GPIO_DRAM2_STATUS_REG 16
  44 +#define GPIO_SWRESET_REG 8
  45 +#define GPIO_DRAM1_CNTRL_REG 9
  46 +#define GPIO_DRAM1_RATIO_REG 10
  47 +#define GPIO_DRAM1_RESET_REG 11
  48 +#define GPIO_DRAM1_STATUS_REG 12
  49 +#define GPIO_DRAM2_CNTRL_REG 13
  50 +#define GPIO_DRAM2_RATIO_REG 14
  51 +#define GPIO_DRAM2_RESET_REG 15
  52 +#define GPIO_DRAM2_STATUS_REG 16
53 53  
54   -#define NETLOGIC_GPIO_PWRON_RESET_CFG_REG 21
55   -#define NETLOGIC_GPIO_BIST_ALL_GO_STATUS_REG 24
56   -#define NETLOGIC_GPIO_BIST_CPU_GO_STATUS_REG 25
57   -#define NETLOGIC_GPIO_BIST_DEV_GO_STATUS_REG 26
  54 +#define GPIO_PWRON_RESET_CFG_REG 21
  55 +#define GPIO_BIST_ALL_GO_STATUS_REG 24
  56 +#define GPIO_BIST_CPU_GO_STATUS_REG 25
  57 +#define GPIO_BIST_DEV_GO_STATUS_REG 26
58 58  
59   -#define NETLOGIC_GPIO_FUSE_BANK_REG 35
60   -#define NETLOGIC_GPIO_CPU_RESET_REG 40
61   -#define NETLOGIC_GPIO_RNG_REG 43
  59 +#define GPIO_FUSE_BANK_REG 35
  60 +#define GPIO_CPU_RESET_REG 40
  61 +#define GPIO_RNG_REG 43
62 62  
63   -#define NETLOGIC_PWRON_RESET_PCMCIA_BOOT 17
64   -#define NETLOGIC_GPIO_LED_BITMAP 0x1700000
65   -#define NETLOGIC_GPIO_LED_0_SHIFT 20
66   -#define NETLOGIC_GPIO_LED_1_SHIFT 24
  63 +#define PWRON_RESET_PCMCIA_BOOT 17
67 64  
68   -#define NETLOGIC_GPIO_LED_OUTPUT_CODE_RESET 0x01
69   -#define NETLOGIC_GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02
70   -#define NETLOGIC_GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03
71   -#define NETLOGIC_GPIO_LED_OUTPUT_CODE_MAIN 0x04
  65 +#define GPIO_LED_BITMAP 0x1700000
  66 +#define GPIO_LED_0_SHIFT 20
  67 +#define GPIO_LED_1_SHIFT 24
  68 +
  69 +#define GPIO_LED_OUTPUT_CODE_RESET 0x01
  70 +#define GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02
  71 +#define GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03
  72 +#define GPIO_LED_OUTPUT_CODE_MAIN 0x04
72 73  
73 74 #endif
arch/mips/netlogic/xlr/setup.c
Diff comments   View file @ c5a48ff
... ... @@ -85,7 +85,7 @@
85 85  
86 86 gpiobase = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
87 87 /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */
88   - nlm_write_reg(gpiobase, NETLOGIC_GPIO_SWRESET_REG, 1);
  88 + nlm_write_reg(gpiobase, GPIO_SWRESET_REG, 1);
89 89 for ( ; ; )
90 90 cpu_wait();
91 91 }