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Commit c640e8ca172c6a5c45abe8e2e8353900a84427fa

Authored by Dave Airlie
1 parent fdc315a19a
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

drm/radeon: fix page flipping hangs on r300/r400 

We've been getting reports of complete system lockups with rv3xx hw on
AGP and PCIE when running gnome-shell or kwin with compositing.

It appears the hw really doesn't like setting these registers while
stuff is running, this moves the setting of the registers into the modeset
since they aren't required to be changed anywhere else.

fixes: https://bugs.freedesktop.org/show_bug.cgi?id=35183

Reported-and-tested-by: Álmos <aaalmosss@gmail.com
Signed-off-by: Dave Airlie <airlied@redhat.com>

Showing 2 changed files with 2 additions and 18 deletions Side-by-side Diff

drivers/gpu/drm/radeon/r100.c
Diff comments   View file @ c640e8c
... ... @@ -70,23 +70,6 @@
70 70  
71 71 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
72 72 {
73   - struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
74   - u32 tmp;
75   -
76   - /* make sure flip is at vb rather than hb */
77   - tmp = RREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset);
78   - tmp &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
79   - /* make sure pending bit is asserted */
80   - tmp |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
81   - WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, tmp);
82   -
83   - /* set pageflip to happen as late as possible in the vblank interval.
84   - * same field for crtc1/2
85   - */
86   - tmp = RREG32(RADEON_CRTC_GEN_CNTL);
87   - tmp &= ~RADEON_CRTC_VSTAT_MODE_MASK;
88   - WREG32(RADEON_CRTC_GEN_CNTL, tmp);
89   -
90 73 /* enable the pflip int */
91 74 radeon_irq_kms_pflip_irq_get(rdev, crtc);
92 75 }
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
Diff comments   View file @ c640e8c
... ... @@ -443,7 +443,7 @@
443 443 (target_fb->bits_per_pixel * 8));
444 444 crtc_pitch |= crtc_pitch << 16;
445 445  
446   -
  446 + crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
447 447 if (tiling_flags & RADEON_TILING_MACRO) {
448 448 if (ASIC_IS_R300(rdev))
449 449 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
... ... @@ -502,6 +502,7 @@
502 502 gen_cntl_val = RREG32(gen_cntl_reg);
503 503 gen_cntl_val &= ~(0xf << 8);
504 504 gen_cntl_val |= (format << 8);
  505 + gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK;
505 506 WREG32(gen_cntl_reg, gen_cntl_val);
506 507  
507 508 crtc_offset = (u32)base;