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Commit c6a2d839d0dba8a06f55c7b06f8ce33bdbe4aea3

Authored by Tero Kristo
Committed by Paul Walmsley
1 parent 7a90da2ad3
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

ARM: OMAP3: CM/control: move CM scratchpad save to CM driver 

OMAP3 PM code for off-mode currently saves the scratchpad contents for CM
registers within OMAP control module driver. However, as we are separating
CM code into its own driver, this must be moved also. This patch adds a
new API for saving the CM scratchpad contents and uses this from the high
level scratchpad save function.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

Showing 3 changed files with 27 additions and 39 deletions Side-by-side Diff

arch/arm/mach-omap2/cm3xxx.c
Diff comments   View file @ c6a2d83
... ... @@ -636,6 +636,28 @@
636 636 OMAP3_CM_CLKOUT_CTRL_OFFSET);
637 637 }
638 638  
  639 +void omap3_cm_save_scratchpad_contents(u32 *ptr)
  640 +{
  641 + *ptr++ = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
  642 + *ptr++ = omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
  643 + *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
  644 +
  645 + /*
  646 + * As per erratum i671, ROM code does not respect the PER DPLL
  647 + * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
  648 + * Then, in anycase, clear these bits to avoid extra latencies.
  649 + */
  650 + *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
  651 + ~OMAP3430_AUTO_PERIPH_DPLL_MASK;
  652 + *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
  653 + *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
  654 + *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
  655 + *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
  656 + *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
  657 + *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
  658 + *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
  659 +}
  660 +
639 661 /*
640 662 *
641 663 */
arch/arm/mach-omap2/cm3xxx.h
Diff comments   View file @ c6a2d83
... ... @@ -83,6 +83,7 @@
83 83  
84 84 extern void omap3_cm_save_context(void);
85 85 extern void omap3_cm_restore_context(void);
  86 +extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
86 87  
87 88 extern int __init omap3xxx_cm_init(void);
88 89  
arch/arm/mach-omap2/control.c
Diff comments   View file @ c6a2d83
... ... @@ -46,17 +46,7 @@
46 46 struct omap3_scratchpad_prcm_block {
47 47 u32 prm_clksrc_ctrl;
48 48 u32 prm_clksel;
49   - u32 cm_clksel_core;
50   - u32 cm_clksel_wkup;
51   - u32 cm_clken_pll;
52   - u32 cm_autoidle_pll;
53   - u32 cm_clksel1_pll;
54   - u32 cm_clksel2_pll;
55   - u32 cm_clksel3_pll;
56   - u32 cm_clken_pll_mpu;
57   - u32 cm_autoidle_pll_mpu;
58   - u32 cm_clksel1_pll_mpu;
59   - u32 cm_clksel2_pll_mpu;
  49 + u32 cm_contents[11];
60 50 u32 prcm_block_size;
61 51 };
62 52  
... ... @@ -347,34 +337,9 @@
347 337 prcm_block_contents.prm_clksel =
348 338 omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
349 339 OMAP3_PRM_CLKSEL_OFFSET);
350   - prcm_block_contents.cm_clksel_core =
351   - omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
352   - prcm_block_contents.cm_clksel_wkup =
353   - omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
354   - prcm_block_contents.cm_clken_pll =
355   - omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
356   - /*
357   - * As per erratum i671, ROM code does not respect the PER DPLL
358   - * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
359   - * Then, in anycase, clear these bits to avoid extra latencies.
360   - */
361   - prcm_block_contents.cm_autoidle_pll =
362   - omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
363   - ~OMAP3430_AUTO_PERIPH_DPLL_MASK;
364   - prcm_block_contents.cm_clksel1_pll =
365   - omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
366   - prcm_block_contents.cm_clksel2_pll =
367   - omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
368   - prcm_block_contents.cm_clksel3_pll =
369   - omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
370   - prcm_block_contents.cm_clken_pll_mpu =
371   - omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
372   - prcm_block_contents.cm_autoidle_pll_mpu =
373   - omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
374   - prcm_block_contents.cm_clksel1_pll_mpu =
375   - omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
376   - prcm_block_contents.cm_clksel2_pll_mpu =
377   - omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
  340 +
  341 + omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
  342 +
378 343 prcm_block_contents.prcm_block_size = 0x0;
379 344  
380 345 /* Populate the SDRC block contents */