znet: fix build failure from i82593.h relocation

znet was including "wireless/i82593.h" (which is a bit wierd), and I missed that when I relocated i82593.h to drivers/staging/wavelan. Since I don't have ISA turned-on in my normal .config, I didn't see the build failures -- mea culpa! Signed-off-by: John W. Linville <linville@tuxdriver.com>

znet: fix build failure from i82593.h relocation
znet was including "wireless/i82593.h" (which is a bit wierd), and I missed that when I relocated i82593.h to drivers/staging/wavelan. Since I don't have ISA turned-on in my normal .config, I didn't see the build failures -- mea culpa! Signed-off-by: John W. Linville <linville@tuxdriver.com>
John W. Linville
1 parent b23709248f
Showing 4 changed files with 231 additions and 232 deletions Side-by-side Diff
drivers/net/znet.c
drivers/staging/wavelan/i82593.h
drivers/staging/wavelan/wavelan_cs.p.h
include/linux/i82593.h
@@ -103,8 +103,7 @@
 #include <asm/io.h>
 #include <asm/dma.h>
  
-/* This include could be elsewhere, since it is not wireless specific */
-#include "wireless/i82593.h"
+#include <linux/i82593.h>
  
 static char version[] __initdata = "znet.c:v1.02 9/23/94 becker@scyld.com\n";
  
-/*
- * Definitions for Intel 82593 CSMA/CD Core LAN Controller
- * The definitions are taken from the 1992 users manual with Intel
- * order number 297125-001.
- *
- * /usr/src/pc/RCS/i82593.h,v 1.1 1996/07/17 15:23:12 root Exp
- *
- * Copyright 1994, Anders Klemets <klemets@it.kth.se>
- *
- * HISTORY
- * i82593.h,v
- * Revision 1.4  2005/11/4  09:15:00  baroniunas
- * Modified copyright with permission of author as follows:
- *
- *   "If I82539.H is the only file with my copyright statement
- *    that is included in the Source Forge project, then you have
- *    my approval to change the copyright statement to be a GPL
- *    license, in the way you proposed on October 10."
- *
- * Revision 1.1  1996/07/17 15:23:12  root
- * Initial revision
- *
- * Revision 1.3  1995/04/05  15:13:58  adj
- * Initial alpha release
- *
- * Revision 1.2  1994/06/16  23:57:31  klemets
- * Mirrored all the fields in the configuration block.
- *
- * Revision 1.1  1994/06/02  20:25:34  klemets
- * Initial revision
- *
- *
- */
-#ifndef	_I82593_H
-#define	_I82593_H
-
-/* Intel 82593 CSMA/CD Core LAN Controller */
-
-/* Port 0 Command Register definitions */
-
-/* Execution operations */
-#define OP0_NOP			0	/* CHNL = 0 */
-#define OP0_SWIT_TO_PORT_1	0	/* CHNL = 1 */
-#define OP0_IA_SETUP		1
-#define OP0_CONFIGURE		2
-#define OP0_MC_SETUP		3
-#define OP0_TRANSMIT		4
-#define OP0_TDR			5
-#define OP0_DUMP		6
-#define OP0_DIAGNOSE		7
-#define OP0_TRANSMIT_NO_CRC	9
-#define OP0_RETRANSMIT		12
-#define OP0_ABORT		13
-/* Reception operations */
-#define OP0_RCV_ENABLE		8
-#define OP0_RCV_DISABLE		10
-#define OP0_STOP_RCV		11
-/* Status pointer control operations */
-#define OP0_FIX_PTR		15	/* CHNL = 1 */
-#define OP0_RLS_PTR		15	/* CHNL = 0 */
-#define OP0_RESET		14
-
-#define CR0_CHNL		(1 << 4)	/* 0=Channel 0, 1=Channel 1 */
-#define CR0_STATUS_0		0x00
-#define CR0_STATUS_1		0x20
-#define CR0_STATUS_2		0x40
-#define CR0_STATUS_3		0x60
-#define CR0_INT_ACK		(1 << 7)	/* 0=No ack, 1=acknowledge */
-
-/* Port 0 Status Register definitions */
-
-#define SR0_NO_RESULT		0		/* dummy */
-#define SR0_EVENT_MASK		0x0f
-#define SR0_IA_SETUP_DONE	1
-#define SR0_CONFIGURE_DONE	2
-#define SR0_MC_SETUP_DONE	3
-#define SR0_TRANSMIT_DONE	4
-#define SR0_TDR_DONE		5
-#define SR0_DUMP_DONE		6
-#define SR0_DIAGNOSE_PASSED	7
-#define SR0_TRANSMIT_NO_CRC_DONE 9
-#define SR0_RETRANSMIT_DONE	12
-#define SR0_EXECUTION_ABORTED	13
-#define SR0_END_OF_FRAME	8
-#define SR0_RECEPTION_ABORTED	10
-#define SR0_DIAGNOSE_FAILED	15
-#define SR0_STOP_REG_HIT	11
-
-#define SR0_CHNL		(1 << 4)
-#define SR0_EXECUTION		(1 << 5)
-#define SR0_RECEPTION		(1 << 6)
-#define SR0_INTERRUPT		(1 << 7)
-#define SR0_BOTH_RX_TX		(SR0_EXECUTION | SR0_RECEPTION)
-
-#define SR3_EXEC_STATE_MASK	0x03
-#define SR3_EXEC_IDLE		0
-#define SR3_TX_ABORT_IN_PROGRESS 1
-#define SR3_EXEC_ACTIVE		2
-#define SR3_ABORT_IN_PROGRESS	3
-#define SR3_EXEC_CHNL		(1 << 2)
-#define SR3_STP_ON_NO_RSRC	(1 << 3)
-#define SR3_RCVING_NO_RSRC	(1 << 4)
-#define SR3_RCV_STATE_MASK	0x60
-#define SR3_RCV_IDLE		0x00
-#define SR3_RCV_READY		0x20
-#define SR3_RCV_ACTIVE		0x40
-#define SR3_RCV_STOP_IN_PROG	0x60
-#define SR3_RCV_CHNL		(1 << 7)
-
-/* Port 1 Command Register definitions */
-
-#define OP1_NOP			0
-#define OP1_SWIT_TO_PORT_0	1
-#define OP1_INT_DISABLE		2
-#define OP1_INT_ENABLE		3
-#define OP1_SET_TS		5
-#define OP1_RST_TS		7
-#define OP1_POWER_DOWN		8
-#define OP1_RESET_RING_MNGMT	11
-#define OP1_RESET		14
-#define OP1_SEL_RST		15
-
-#define CR1_STATUS_4		0x00
-#define CR1_STATUS_5		0x20
-#define CR1_STATUS_6		0x40
-#define CR1_STOP_REG_UPDATE	(1 << 7)
-
-/* Receive frame status bits */
-
-#define	RX_RCLD			(1 << 0)
-#define RX_IA_MATCH		(1 << 1)
-#define	RX_NO_AD_MATCH		(1 << 2)
-#define RX_NO_SFD		(1 << 3)
-#define RX_SRT_FRM		(1 << 7)
-#define RX_OVRRUN		(1 << 8)
-#define RX_ALG_ERR		(1 << 10)
-#define RX_CRC_ERR		(1 << 11)
-#define RX_LEN_ERR		(1 << 12)
-#define RX_RCV_OK		(1 << 13)
-#define RX_TYP_LEN		(1 << 15)
-
-/* Transmit status bits */
-
-#define TX_NCOL_MASK		0x0f
-#define TX_FRTL			(1 << 4)
-#define TX_MAX_COL		(1 << 5)
-#define TX_HRT_BEAT		(1 << 6)
-#define TX_DEFER		(1 << 7)
-#define TX_UND_RUN		(1 << 8)
-#define TX_LOST_CTS		(1 << 9)
-#define TX_LOST_CRS		(1 << 10)
-#define TX_LTCOL		(1 << 11)
-#define TX_OK			(1 << 13)
-#define TX_COLL			(1 << 15)
-
-struct i82593_conf_block {
-  u_char fifo_limit : 4,
-  	 forgnesi   : 1,
-  	 fifo_32    : 1,
-  	 d6mod      : 1,
-  	 throttle_enb : 1;
-  u_char throttle   : 6,
-	 cntrxint   : 1,
-	 contin	    : 1;
-  u_char addr_len   : 3,
-  	 acloc 	    : 1,
- 	 preamb_len : 2,
-  	 loopback   : 2;
-  u_char lin_prio   : 3,
-	 tbofstop   : 1,
-	 exp_prio   : 3,
-	 bof_met    : 1;
-  u_char	    : 4,
-	 ifrm_spc   : 4;
-  u_char	    : 5,
-	 slottim_low : 3;
-  u_char slottim_hi : 3,
-		    : 1,
-	 max_retr   : 4;
-  u_char prmisc     : 1,
-	 bc_dis     : 1,
-  		    : 1,
-	 crs_1	    : 1,
-	 nocrc_ins  : 1,
-	 crc_1632   : 1,
-  	 	    : 1,
-  	 crs_cdt    : 1;
-  u_char cs_filter  : 3,
-	 crs_src    : 1,
-	 cd_filter  : 3,
-		    : 1;
-  u_char	    : 2,
-  	 min_fr_len : 6;
-  u_char lng_typ    : 1,
-	 lng_fld    : 1,
-	 rxcrc_xf   : 1,
-	 artx	    : 1,
-	 sarec	    : 1,
-	 tx_jabber  : 1,	/* why is this called max_len in the manual? */
-	 hash_1	    : 1,
-  	 lbpkpol    : 1;
-  u_char	    : 6,
-  	 fdx	    : 1,
-  	  	    : 1;
-  u_char dummy_6    : 6,	/* supposed to be ones */
-  	 mult_ia    : 1,
-  	 dis_bof    : 1;
-  u_char dummy_1    : 1,	/* supposed to be one */
-	 tx_ifs_retrig : 2,
-	 mc_all     : 1,
-	 rcv_mon    : 2,
-	 frag_acpt  : 1,
-  	 tstrttrs   : 1;
-  u_char fretx	    : 1,
-	 runt_eop   : 1,
-	 hw_sw_pin  : 1,
-	 big_endn   : 1,
-	 syncrqs    : 1,
-	 sttlen     : 1,
-	 tx_eop     : 1,
-  	 rx_eop	    : 1;
-  u_char rbuf_size  : 5,
-	 rcvstop    : 1,
-  	 	    : 2;
-};
-
-#define I82593_MAX_MULTICAST_ADDRESSES	128	/* Hardware hashed filter */
-
-#endif /* _I82593_H */
@@ -446,7 +446,7 @@
 #include <pcmcia/ds.h>
  
 /* Wavelan declarations */
-#include "i82593.h"	/* Definitions for the Intel chip */
+#include <linux/i82593.h>	/* Definitions for the Intel chip */
  
 #include "wavelan_cs.h"	/* Others bits of the hardware */
  
+/*
+ * Definitions for Intel 82593 CSMA/CD Core LAN Controller
+ * The definitions are taken from the 1992 users manual with Intel
+ * order number 297125-001.
+ *
+ * /usr/src/pc/RCS/i82593.h,v 1.1 1996/07/17 15:23:12 root Exp
+ *
+ * Copyright 1994, Anders Klemets <klemets@it.kth.se>
+ *
+ * HISTORY
+ * i82593.h,v
+ * Revision 1.4  2005/11/4  09:15:00  baroniunas
+ * Modified copyright with permission of author as follows:
+ *
+ *   "If I82539.H is the only file with my copyright statement
+ *    that is included in the Source Forge project, then you have
+ *    my approval to change the copyright statement to be a GPL
+ *    license, in the way you proposed on October 10."
+ *
+ * Revision 1.1  1996/07/17 15:23:12  root
+ * Initial revision
+ *
+ * Revision 1.3  1995/04/05  15:13:58  adj
+ * Initial alpha release
+ *
+ * Revision 1.2  1994/06/16  23:57:31  klemets
+ * Mirrored all the fields in the configuration block.
+ *
+ * Revision 1.1  1994/06/02  20:25:34  klemets
+ * Initial revision
+ *
+ *
+ */
+#ifndef	_I82593_H
+#define	_I82593_H
+
+/* Intel 82593 CSMA/CD Core LAN Controller */
+
+/* Port 0 Command Register definitions */
+
+/* Execution operations */
+#define OP0_NOP			0	/* CHNL = 0 */
+#define OP0_SWIT_TO_PORT_1	0	/* CHNL = 1 */
+#define OP0_IA_SETUP		1
+#define OP0_CONFIGURE		2
+#define OP0_MC_SETUP		3
+#define OP0_TRANSMIT		4
+#define OP0_TDR			5
+#define OP0_DUMP		6
+#define OP0_DIAGNOSE		7
+#define OP0_TRANSMIT_NO_CRC	9
+#define OP0_RETRANSMIT		12
+#define OP0_ABORT		13
+/* Reception operations */
+#define OP0_RCV_ENABLE		8
+#define OP0_RCV_DISABLE		10
+#define OP0_STOP_RCV		11
+/* Status pointer control operations */
+#define OP0_FIX_PTR		15	/* CHNL = 1 */
+#define OP0_RLS_PTR		15	/* CHNL = 0 */
+#define OP0_RESET		14
+
+#define CR0_CHNL		(1 << 4)	/* 0=Channel 0, 1=Channel 1 */
+#define CR0_STATUS_0		0x00
+#define CR0_STATUS_1		0x20
+#define CR0_STATUS_2		0x40
+#define CR0_STATUS_3		0x60
+#define CR0_INT_ACK		(1 << 7)	/* 0=No ack, 1=acknowledge */
+
+/* Port 0 Status Register definitions */
+
+#define SR0_NO_RESULT		0		/* dummy */
+#define SR0_EVENT_MASK		0x0f
+#define SR0_IA_SETUP_DONE	1
+#define SR0_CONFIGURE_DONE	2
+#define SR0_MC_SETUP_DONE	3
+#define SR0_TRANSMIT_DONE	4
+#define SR0_TDR_DONE		5
+#define SR0_DUMP_DONE		6
+#define SR0_DIAGNOSE_PASSED	7
+#define SR0_TRANSMIT_NO_CRC_DONE 9
+#define SR0_RETRANSMIT_DONE	12
+#define SR0_EXECUTION_ABORTED	13
+#define SR0_END_OF_FRAME	8
+#define SR0_RECEPTION_ABORTED	10
+#define SR0_DIAGNOSE_FAILED	15
+#define SR0_STOP_REG_HIT	11
+
+#define SR0_CHNL		(1 << 4)
+#define SR0_EXECUTION		(1 << 5)
+#define SR0_RECEPTION		(1 << 6)
+#define SR0_INTERRUPT		(1 << 7)
+#define SR0_BOTH_RX_TX		(SR0_EXECUTION | SR0_RECEPTION)
+
+#define SR3_EXEC_STATE_MASK	0x03
+#define SR3_EXEC_IDLE		0
+#define SR3_TX_ABORT_IN_PROGRESS 1
+#define SR3_EXEC_ACTIVE		2
+#define SR3_ABORT_IN_PROGRESS	3
+#define SR3_EXEC_CHNL		(1 << 2)
+#define SR3_STP_ON_NO_RSRC	(1 << 3)
+#define SR3_RCVING_NO_RSRC	(1 << 4)
+#define SR3_RCV_STATE_MASK	0x60
+#define SR3_RCV_IDLE		0x00
+#define SR3_RCV_READY		0x20
+#define SR3_RCV_ACTIVE		0x40
+#define SR3_RCV_STOP_IN_PROG	0x60
+#define SR3_RCV_CHNL		(1 << 7)
+
+/* Port 1 Command Register definitions */
+
+#define OP1_NOP			0
+#define OP1_SWIT_TO_PORT_0	1
+#define OP1_INT_DISABLE		2
+#define OP1_INT_ENABLE		3
+#define OP1_SET_TS		5
+#define OP1_RST_TS		7
+#define OP1_POWER_DOWN		8
+#define OP1_RESET_RING_MNGMT	11
+#define OP1_RESET		14
+#define OP1_SEL_RST		15
+
+#define CR1_STATUS_4		0x00
+#define CR1_STATUS_5		0x20
+#define CR1_STATUS_6		0x40
+#define CR1_STOP_REG_UPDATE	(1 << 7)
+
+/* Receive frame status bits */
+
+#define	RX_RCLD			(1 << 0)
+#define RX_IA_MATCH		(1 << 1)
+#define	RX_NO_AD_MATCH		(1 << 2)
+#define RX_NO_SFD		(1 << 3)
+#define RX_SRT_FRM		(1 << 7)
+#define RX_OVRRUN		(1 << 8)
+#define RX_ALG_ERR		(1 << 10)
+#define RX_CRC_ERR		(1 << 11)
+#define RX_LEN_ERR		(1 << 12)
+#define RX_RCV_OK		(1 << 13)
+#define RX_TYP_LEN		(1 << 15)
+
+/* Transmit status bits */
+
+#define TX_NCOL_MASK		0x0f
+#define TX_FRTL			(1 << 4)
+#define TX_MAX_COL		(1 << 5)
+#define TX_HRT_BEAT		(1 << 6)
+#define TX_DEFER		(1 << 7)
+#define TX_UND_RUN		(1 << 8)
+#define TX_LOST_CTS		(1 << 9)
+#define TX_LOST_CRS		(1 << 10)
+#define TX_LTCOL		(1 << 11)
+#define TX_OK			(1 << 13)
+#define TX_COLL			(1 << 15)
+
+struct i82593_conf_block {
+  u_char fifo_limit : 4,
+  	 forgnesi   : 1,
+  	 fifo_32    : 1,
+  	 d6mod      : 1,
+  	 throttle_enb : 1;
+  u_char throttle   : 6,
+	 cntrxint   : 1,
+	 contin	    : 1;
+  u_char addr_len   : 3,
+  	 acloc 	    : 1,
+ 	 preamb_len : 2,
+  	 loopback   : 2;
+  u_char lin_prio   : 3,
+	 tbofstop   : 1,
+	 exp_prio   : 3,
+	 bof_met    : 1;
+  u_char	    : 4,
+	 ifrm_spc   : 4;
+  u_char	    : 5,
+	 slottim_low : 3;
+  u_char slottim_hi : 3,
+		    : 1,
+	 max_retr   : 4;
+  u_char prmisc     : 1,
+	 bc_dis     : 1,
+  		    : 1,
+	 crs_1	    : 1,
+	 nocrc_ins  : 1,
+	 crc_1632   : 1,
+  	 	    : 1,
+  	 crs_cdt    : 1;
+  u_char cs_filter  : 3,
+	 crs_src    : 1,
+	 cd_filter  : 3,
+		    : 1;
+  u_char	    : 2,
+  	 min_fr_len : 6;
+  u_char lng_typ    : 1,
+	 lng_fld    : 1,
+	 rxcrc_xf   : 1,
+	 artx	    : 1,
+	 sarec	    : 1,
+	 tx_jabber  : 1,	/* why is this called max_len in the manual? */
+	 hash_1	    : 1,
+  	 lbpkpol    : 1;
+  u_char	    : 6,
+  	 fdx	    : 1,
+  	  	    : 1;
+  u_char dummy_6    : 6,	/* supposed to be ones */
+  	 mult_ia    : 1,
+  	 dis_bof    : 1;
+  u_char dummy_1    : 1,	/* supposed to be one */
+	 tx_ifs_retrig : 2,
+	 mc_all     : 1,
+	 rcv_mon    : 2,
+	 frag_acpt  : 1,
+  	 tstrttrs   : 1;
+  u_char fretx	    : 1,
+	 runt_eop   : 1,
+	 hw_sw_pin  : 1,
+	 big_endn   : 1,
+	 syncrqs    : 1,
+	 sttlen     : 1,
+	 tx_eop     : 1,
+  	 rx_eop	    : 1;
+  u_char rbuf_size  : 5,
+	 rcvstop    : 1,
+  	 	    : 2;
+};
+
+#define I82593_MAX_MULTICAST_ADDRESSES	128	/* Hardware hashed filter */
+
+#endif /* _I82593_H */
...	...	@@ -103,8 +103,7 @@
103	103	#include <asm/io.h>
104	104	#include <asm/dma.h>
105	105
106		-/* This include could be elsewhere, since it is not wireless specific */
107		-#include "wireless/i82593.h"
	106	+#include <linux/i82593.h>
108	107
109	108	static char version[] __initdata = "znet.c:v1.02 9/23/94 becker@scyld.com\n";
110	109
1		-/*
2		- * Definitions for Intel 82593 CSMA/CD Core LAN Controller
3		- * The definitions are taken from the 1992 users manual with Intel
4		- * order number 297125-001.
5		- *
6		- * /usr/src/pc/RCS/i82593.h,v 1.1 1996/07/17 15:23:12 root Exp
7		- *
8		- * Copyright 1994, Anders Klemets <klemets@it.kth.se>
9		- *
10		- * HISTORY
11		- * i82593.h,v
12		- * Revision 1.4 2005/11/4 09:15:00 baroniunas
13		- * Modified copyright with permission of author as follows:
14		- *
15		- * "If I82539.H is the only file with my copyright statement
16		- * that is included in the Source Forge project, then you have
17		- * my approval to change the copyright statement to be a GPL
18		- * license, in the way you proposed on October 10."
19		- *
20		- * Revision 1.1 1996/07/17 15:23:12 root
21		- * Initial revision
22		- *
23		- * Revision 1.3 1995/04/05 15:13:58 adj
24		- * Initial alpha release
25		- *
26		- * Revision 1.2 1994/06/16 23:57:31 klemets
27		- * Mirrored all the fields in the configuration block.
28		- *
29		- * Revision 1.1 1994/06/02 20:25:34 klemets
30		- * Initial revision
31		- *
32		- *
33		- */
34		-#ifndef _I82593_H
35		-#define _I82593_H
36		-
37		-/* Intel 82593 CSMA/CD Core LAN Controller */
38		-
39		-/* Port 0 Command Register definitions */
40		-
41		-/* Execution operations */
42		-#define OP0_NOP 0 /* CHNL = 0 */
43		-#define OP0_SWIT_TO_PORT_1 0 /* CHNL = 1 */
44		-#define OP0_IA_SETUP 1
45		-#define OP0_CONFIGURE 2
46		-#define OP0_MC_SETUP 3
47		-#define OP0_TRANSMIT 4
48		-#define OP0_TDR 5
49		-#define OP0_DUMP 6
50		-#define OP0_DIAGNOSE 7
51		-#define OP0_TRANSMIT_NO_CRC 9
52		-#define OP0_RETRANSMIT 12
53		-#define OP0_ABORT 13
54		-/* Reception operations */
55		-#define OP0_RCV_ENABLE 8
56		-#define OP0_RCV_DISABLE 10
57		-#define OP0_STOP_RCV 11
58		-/* Status pointer control operations */
59		-#define OP0_FIX_PTR 15 /* CHNL = 1 */
60		-#define OP0_RLS_PTR 15 /* CHNL = 0 */
61		-#define OP0_RESET 14
62		-
63		-#define CR0_CHNL (1 << 4) /* 0=Channel 0, 1=Channel 1 */
64		-#define CR0_STATUS_0 0x00
65		-#define CR0_STATUS_1 0x20
66		-#define CR0_STATUS_2 0x40
67		-#define CR0_STATUS_3 0x60
68		-#define CR0_INT_ACK (1 << 7) /* 0=No ack, 1=acknowledge */
69		-
70		-/* Port 0 Status Register definitions */
71		-
72		-#define SR0_NO_RESULT 0 /* dummy */
73		-#define SR0_EVENT_MASK 0x0f
74		-#define SR0_IA_SETUP_DONE 1
75		-#define SR0_CONFIGURE_DONE 2
76		-#define SR0_MC_SETUP_DONE 3
77		-#define SR0_TRANSMIT_DONE 4
78		-#define SR0_TDR_DONE 5
79		-#define SR0_DUMP_DONE 6
80		-#define SR0_DIAGNOSE_PASSED 7
81		-#define SR0_TRANSMIT_NO_CRC_DONE 9
82		-#define SR0_RETRANSMIT_DONE 12
83		-#define SR0_EXECUTION_ABORTED 13
84		-#define SR0_END_OF_FRAME 8
85		-#define SR0_RECEPTION_ABORTED 10
86		-#define SR0_DIAGNOSE_FAILED 15
87		-#define SR0_STOP_REG_HIT 11
88		-
89		-#define SR0_CHNL (1 << 4)
90		-#define SR0_EXECUTION (1 << 5)
91		-#define SR0_RECEPTION (1 << 6)
92		-#define SR0_INTERRUPT (1 << 7)
93		-#define SR0_BOTH_RX_TX (SR0_EXECUTION \| SR0_RECEPTION)
94		-
95		-#define SR3_EXEC_STATE_MASK 0x03
96		-#define SR3_EXEC_IDLE 0
97		-#define SR3_TX_ABORT_IN_PROGRESS 1
98		-#define SR3_EXEC_ACTIVE 2
99		-#define SR3_ABORT_IN_PROGRESS 3
100		-#define SR3_EXEC_CHNL (1 << 2)
101		-#define SR3_STP_ON_NO_RSRC (1 << 3)
102		-#define SR3_RCVING_NO_RSRC (1 << 4)
103		-#define SR3_RCV_STATE_MASK 0x60
104		-#define SR3_RCV_IDLE 0x00
105		-#define SR3_RCV_READY 0x20
106		-#define SR3_RCV_ACTIVE 0x40
107		-#define SR3_RCV_STOP_IN_PROG 0x60
108		-#define SR3_RCV_CHNL (1 << 7)
109		-
110		-/* Port 1 Command Register definitions */
111		-
112		-#define OP1_NOP 0
113		-#define OP1_SWIT_TO_PORT_0 1
114		-#define OP1_INT_DISABLE 2
115		-#define OP1_INT_ENABLE 3
116		-#define OP1_SET_TS 5
117		-#define OP1_RST_TS 7
118		-#define OP1_POWER_DOWN 8
119		-#define OP1_RESET_RING_MNGMT 11
120		-#define OP1_RESET 14
121		-#define OP1_SEL_RST 15
122		-
123		-#define CR1_STATUS_4 0x00
124		-#define CR1_STATUS_5 0x20
125		-#define CR1_STATUS_6 0x40
126		-#define CR1_STOP_REG_UPDATE (1 << 7)
127		-
128		-/* Receive frame status bits */
129		-
130		-#define RX_RCLD (1 << 0)
131		-#define RX_IA_MATCH (1 << 1)
132		-#define RX_NO_AD_MATCH (1 << 2)
133		-#define RX_NO_SFD (1 << 3)
134		-#define RX_SRT_FRM (1 << 7)
135		-#define RX_OVRRUN (1 << 8)
136		-#define RX_ALG_ERR (1 << 10)
137		-#define RX_CRC_ERR (1 << 11)
138		-#define RX_LEN_ERR (1 << 12)
139		-#define RX_RCV_OK (1 << 13)
140		-#define RX_TYP_LEN (1 << 15)
141		-
142		-/* Transmit status bits */
143		-
144		-#define TX_NCOL_MASK 0x0f
145		-#define TX_FRTL (1 << 4)
146		-#define TX_MAX_COL (1 << 5)
147		-#define TX_HRT_BEAT (1 << 6)
148		-#define TX_DEFER (1 << 7)
149		-#define TX_UND_RUN (1 << 8)
150		-#define TX_LOST_CTS (1 << 9)
151		-#define TX_LOST_CRS (1 << 10)
152		-#define TX_LTCOL (1 << 11)
153		-#define TX_OK (1 << 13)
154		-#define TX_COLL (1 << 15)
155		-
156		-struct i82593_conf_block {
157		- u_char fifo_limit : 4,
158		- forgnesi : 1,
159		- fifo_32 : 1,
160		- d6mod : 1,
161		- throttle_enb : 1;
162		- u_char throttle : 6,
163		- cntrxint : 1,
164		- contin : 1;
165		- u_char addr_len : 3,
166		- acloc : 1,
167		- preamb_len : 2,
168		- loopback : 2;
169		- u_char lin_prio : 3,
170		- tbofstop : 1,
171		- exp_prio : 3,
172		- bof_met : 1;
173		- u_char : 4,
174		- ifrm_spc : 4;
175		- u_char : 5,
176		- slottim_low : 3;
177		- u_char slottim_hi : 3,
178		- : 1,
179		- max_retr : 4;
180		- u_char prmisc : 1,
181		- bc_dis : 1,
182		- : 1,
183		- crs_1 : 1,
184		- nocrc_ins : 1,
185		- crc_1632 : 1,
186		- : 1,
187		- crs_cdt : 1;
188		- u_char cs_filter : 3,
189		- crs_src : 1,
190		- cd_filter : 3,
191		- : 1;
192		- u_char : 2,
193		- min_fr_len : 6;
194		- u_char lng_typ : 1,
195		- lng_fld : 1,
196		- rxcrc_xf : 1,
197		- artx : 1,
198		- sarec : 1,
199		- tx_jabber : 1, /* why is this called max_len in the manual? */
200		- hash_1 : 1,
201		- lbpkpol : 1;
202		- u_char : 6,
203		- fdx : 1,
204		- : 1;
205		- u_char dummy_6 : 6, /* supposed to be ones */
206		- mult_ia : 1,
207		- dis_bof : 1;
208		- u_char dummy_1 : 1, /* supposed to be one */
209		- tx_ifs_retrig : 2,
210		- mc_all : 1,
211		- rcv_mon : 2,
212		- frag_acpt : 1,
213		- tstrttrs : 1;
214		- u_char fretx : 1,
215		- runt_eop : 1,
216		- hw_sw_pin : 1,
217		- big_endn : 1,
218		- syncrqs : 1,
219		- sttlen : 1,
220		- tx_eop : 1,
221		- rx_eop : 1;
222		- u_char rbuf_size : 5,
223		- rcvstop : 1,
224		- : 2;
225		-};
226		-
227		-#define I82593_MAX_MULTICAST_ADDRESSES 128 /* Hardware hashed filter */
228		-
229		-#endif /* _I82593_H */
...	...	@@ -446,7 +446,7 @@
446	446	#include <pcmcia/ds.h>
447	447
448	448	/* Wavelan declarations */
449		-#include "i82593.h" /* Definitions for the Intel chip */
	449	+#include <linux/i82593.h> /* Definitions for the Intel chip */
450	450
451	451	#include "wavelan_cs.h" /* Others bits of the hardware */
452	452
	1	+/*
	2	+ * Definitions for Intel 82593 CSMA/CD Core LAN Controller
	3	+ * The definitions are taken from the 1992 users manual with Intel
	4	+ * order number 297125-001.
	5	+ *
	6	+ * /usr/src/pc/RCS/i82593.h,v 1.1 1996/07/17 15:23:12 root Exp
	7	+ *
	8	+ * Copyright 1994, Anders Klemets <klemets@it.kth.se>
	9	+ *
	10	+ * HISTORY
	11	+ * i82593.h,v
	12	+ * Revision 1.4 2005/11/4 09:15:00 baroniunas
	13	+ * Modified copyright with permission of author as follows:
	14	+ *
	15	+ * "If I82539.H is the only file with my copyright statement
	16	+ * that is included in the Source Forge project, then you have
	17	+ * my approval to change the copyright statement to be a GPL
	18	+ * license, in the way you proposed on October 10."
	19	+ *
	20	+ * Revision 1.1 1996/07/17 15:23:12 root
	21	+ * Initial revision
	22	+ *
	23	+ * Revision 1.3 1995/04/05 15:13:58 adj
	24	+ * Initial alpha release
	25	+ *
	26	+ * Revision 1.2 1994/06/16 23:57:31 klemets
	27	+ * Mirrored all the fields in the configuration block.
	28	+ *
	29	+ * Revision 1.1 1994/06/02 20:25:34 klemets
	30	+ * Initial revision
	31	+ *
	32	+ *
	33	+ */
	34	+#ifndef _I82593_H
	35	+#define _I82593_H
	36	+
	37	+/* Intel 82593 CSMA/CD Core LAN Controller */
	38	+
	39	+/* Port 0 Command Register definitions */
	40	+
	41	+/* Execution operations */
	42	+#define OP0_NOP 0 /* CHNL = 0 */
	43	+#define OP0_SWIT_TO_PORT_1 0 /* CHNL = 1 */
	44	+#define OP0_IA_SETUP 1
	45	+#define OP0_CONFIGURE 2
	46	+#define OP0_MC_SETUP 3
	47	+#define OP0_TRANSMIT 4
	48	+#define OP0_TDR 5
	49	+#define OP0_DUMP 6
	50	+#define OP0_DIAGNOSE 7
	51	+#define OP0_TRANSMIT_NO_CRC 9
	52	+#define OP0_RETRANSMIT 12
	53	+#define OP0_ABORT 13
	54	+/* Reception operations */
	55	+#define OP0_RCV_ENABLE 8
	56	+#define OP0_RCV_DISABLE 10
	57	+#define OP0_STOP_RCV 11
	58	+/* Status pointer control operations */
	59	+#define OP0_FIX_PTR 15 /* CHNL = 1 */
	60	+#define OP0_RLS_PTR 15 /* CHNL = 0 */
	61	+#define OP0_RESET 14
	62	+
	63	+#define CR0_CHNL (1 << 4) /* 0=Channel 0, 1=Channel 1 */
	64	+#define CR0_STATUS_0 0x00
	65	+#define CR0_STATUS_1 0x20
	66	+#define CR0_STATUS_2 0x40
	67	+#define CR0_STATUS_3 0x60
	68	+#define CR0_INT_ACK (1 << 7) /* 0=No ack, 1=acknowledge */
	69	+
	70	+/* Port 0 Status Register definitions */
	71	+
	72	+#define SR0_NO_RESULT 0 /* dummy */
	73	+#define SR0_EVENT_MASK 0x0f
	74	+#define SR0_IA_SETUP_DONE 1
	75	+#define SR0_CONFIGURE_DONE 2
	76	+#define SR0_MC_SETUP_DONE 3
	77	+#define SR0_TRANSMIT_DONE 4
	78	+#define SR0_TDR_DONE 5
	79	+#define SR0_DUMP_DONE 6
	80	+#define SR0_DIAGNOSE_PASSED 7
	81	+#define SR0_TRANSMIT_NO_CRC_DONE 9
	82	+#define SR0_RETRANSMIT_DONE 12
	83	+#define SR0_EXECUTION_ABORTED 13
	84	+#define SR0_END_OF_FRAME 8
	85	+#define SR0_RECEPTION_ABORTED 10
	86	+#define SR0_DIAGNOSE_FAILED 15
	87	+#define SR0_STOP_REG_HIT 11
	88	+
	89	+#define SR0_CHNL (1 << 4)
	90	+#define SR0_EXECUTION (1 << 5)
	91	+#define SR0_RECEPTION (1 << 6)
	92	+#define SR0_INTERRUPT (1 << 7)
	93	+#define SR0_BOTH_RX_TX (SR0_EXECUTION \| SR0_RECEPTION)
	94	+
	95	+#define SR3_EXEC_STATE_MASK 0x03
	96	+#define SR3_EXEC_IDLE 0
	97	+#define SR3_TX_ABORT_IN_PROGRESS 1
	98	+#define SR3_EXEC_ACTIVE 2
	99	+#define SR3_ABORT_IN_PROGRESS 3
	100	+#define SR3_EXEC_CHNL (1 << 2)
	101	+#define SR3_STP_ON_NO_RSRC (1 << 3)
	102	+#define SR3_RCVING_NO_RSRC (1 << 4)
	103	+#define SR3_RCV_STATE_MASK 0x60
	104	+#define SR3_RCV_IDLE 0x00
	105	+#define SR3_RCV_READY 0x20
	106	+#define SR3_RCV_ACTIVE 0x40
	107	+#define SR3_RCV_STOP_IN_PROG 0x60
	108	+#define SR3_RCV_CHNL (1 << 7)
	109	+
	110	+/* Port 1 Command Register definitions */
	111	+
	112	+#define OP1_NOP 0
	113	+#define OP1_SWIT_TO_PORT_0 1
	114	+#define OP1_INT_DISABLE 2
	115	+#define OP1_INT_ENABLE 3
	116	+#define OP1_SET_TS 5
	117	+#define OP1_RST_TS 7
	118	+#define OP1_POWER_DOWN 8
	119	+#define OP1_RESET_RING_MNGMT 11
	120	+#define OP1_RESET 14
	121	+#define OP1_SEL_RST 15
	122	+
	123	+#define CR1_STATUS_4 0x00
	124	+#define CR1_STATUS_5 0x20
	125	+#define CR1_STATUS_6 0x40
	126	+#define CR1_STOP_REG_UPDATE (1 << 7)
	127	+
	128	+/* Receive frame status bits */
	129	+
	130	+#define RX_RCLD (1 << 0)
	131	+#define RX_IA_MATCH (1 << 1)
	132	+#define RX_NO_AD_MATCH (1 << 2)
	133	+#define RX_NO_SFD (1 << 3)
	134	+#define RX_SRT_FRM (1 << 7)
	135	+#define RX_OVRRUN (1 << 8)
	136	+#define RX_ALG_ERR (1 << 10)
	137	+#define RX_CRC_ERR (1 << 11)
	138	+#define RX_LEN_ERR (1 << 12)
	139	+#define RX_RCV_OK (1 << 13)
	140	+#define RX_TYP_LEN (1 << 15)
	141	+
	142	+/* Transmit status bits */
	143	+
	144	+#define TX_NCOL_MASK 0x0f
	145	+#define TX_FRTL (1 << 4)
	146	+#define TX_MAX_COL (1 << 5)
	147	+#define TX_HRT_BEAT (1 << 6)
	148	+#define TX_DEFER (1 << 7)
	149	+#define TX_UND_RUN (1 << 8)
	150	+#define TX_LOST_CTS (1 << 9)
	151	+#define TX_LOST_CRS (1 << 10)
	152	+#define TX_LTCOL (1 << 11)
	153	+#define TX_OK (1 << 13)
	154	+#define TX_COLL (1 << 15)
	155	+
	156	+struct i82593_conf_block {
	157	+ u_char fifo_limit : 4,
	158	+ forgnesi : 1,
	159	+ fifo_32 : 1,
	160	+ d6mod : 1,
	161	+ throttle_enb : 1;
	162	+ u_char throttle : 6,
	163	+ cntrxint : 1,
	164	+ contin : 1;
	165	+ u_char addr_len : 3,
	166	+ acloc : 1,
	167	+ preamb_len : 2,
	168	+ loopback : 2;
	169	+ u_char lin_prio : 3,
	170	+ tbofstop : 1,
	171	+ exp_prio : 3,
	172	+ bof_met : 1;
	173	+ u_char : 4,
	174	+ ifrm_spc : 4;
	175	+ u_char : 5,
	176	+ slottim_low : 3;
	177	+ u_char slottim_hi : 3,
	178	+ : 1,
	179	+ max_retr : 4;
	180	+ u_char prmisc : 1,
	181	+ bc_dis : 1,
	182	+ : 1,
	183	+ crs_1 : 1,
	184	+ nocrc_ins : 1,
	185	+ crc_1632 : 1,
	186	+ : 1,
	187	+ crs_cdt : 1;
	188	+ u_char cs_filter : 3,
	189	+ crs_src : 1,
	190	+ cd_filter : 3,
	191	+ : 1;
	192	+ u_char : 2,
	193	+ min_fr_len : 6;
	194	+ u_char lng_typ : 1,
	195	+ lng_fld : 1,
	196	+ rxcrc_xf : 1,
	197	+ artx : 1,
	198	+ sarec : 1,
	199	+ tx_jabber : 1, /* why is this called max_len in the manual? */
	200	+ hash_1 : 1,
	201	+ lbpkpol : 1;
	202	+ u_char : 6,
	203	+ fdx : 1,
	204	+ : 1;
	205	+ u_char dummy_6 : 6, /* supposed to be ones */
	206	+ mult_ia : 1,
	207	+ dis_bof : 1;
	208	+ u_char dummy_1 : 1, /* supposed to be one */
	209	+ tx_ifs_retrig : 2,
	210	+ mc_all : 1,
	211	+ rcv_mon : 2,
	212	+ frag_acpt : 1,
	213	+ tstrttrs : 1;
	214	+ u_char fretx : 1,
	215	+ runt_eop : 1,
	216	+ hw_sw_pin : 1,
	217	+ big_endn : 1,
	218	+ syncrqs : 1,
	219	+ sttlen : 1,
	220	+ tx_eop : 1,
	221	+ rx_eop : 1;
	222	+ u_char rbuf_size : 5,
	223	+ rcvstop : 1,
	224	+ : 2;
	225	+};
	226	+
	227	+#define I82593_MAX_MULTICAST_ADDRESSES 128 /* Hardware hashed filter */
	228	+
	229	+#endif /* _I82593_H */